JP3561626B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly, to a structure in which a BPSG film is formed for the purpose of planarization, and Ti / TiN / W (or Al) is favorably formed in a contact hole formed here. is there.
[0002]
[Prior art]
Hereinafter, a conventional semiconductor device and a method for manufacturing the same will be described with reference to the drawings.
First, in FIG. 5, a contact hole 3 is formed in the insulating film 2 by anisotropic etching through a photoresist film in which a region corresponding to the contact hole 3 to be formed is opened in the insulating film 2 on the semiconductor substrate 1. Form. The contact hole 3 exposes a diffusion region formed on the surface of the semiconductor substrate 1.
[0003]
Here, four contact holes 3 are formed, and the corresponding drawing is shown in FIG. 8, and the diffusion region 4 of the transistor is shown by a two-dot chain line, and both sides of the gate 6 shown by a one-dot chain line. Are formed with four contact holes 3.
Subsequently, as shown in FIGS. 5 and 8, an impurity (for example, boron, phosphorus, arsenic, or the like) for the purpose of reducing the contact resistance is ion-implanted into the diffusion region 4 through the mask 5.
[0004]
Subsequently, as shown in FIG. 6, a barrier metal film is formed by sequentially forming a Ti film 7 and a TiN film 8 on the entire surface including the contact hole 3 by a sputtering method. Then, as shown in FIG. Was formed, a W film (or aluminum film) 9 was formed.
In recent years, the aspect ratio of a contact hole tends to increase with the progress of high integration and multilayer wiring of a semiconductor integrated circuit, and therefore, step coverage of a metal wiring film in the contact hole deteriorates, As a technique for solving the above-mentioned problem, a contact plug made of a tungsten film or the like is buried in the contact hole via the barrier metal film, and a wiring is formed on the contact plug as a technique for solving the above problem. .
[0005]
That is, a W film 9 is formed by a CVD method via a barrier metal film formed by sequentially forming a Ti film 7 and a TiN film 8 on the entire surface including the contact hole 3 by a sputtering method, and the W film is etched back. A tungsten plug is buried in the contact hole 3, and a wiring film made of an aluminum film or the like is formed on the tungsten plug.
[0006]
These techniques are described in, for example, JP-A-63-133648.
[0007]
[Problems to be solved by the invention]
In FIG. 7, a gate insulating film is formed in the lowermost layer of the insulating film 2, and several layers of a TEOS film, a glass film, and the like are stacked thereon, and finally, in order to flatten the surface. A BPSG film 10 is formed. When impurities are ion-implanted into the contact hole 3 of FIG. 5, a plurality of contacts are collectively surrounded by a resist mask 5 and ion-implanted at once as shown in FIG. For example, here, the contacts of one transistor, that is, eight contact holes are surrounded by the resist mask 5 and ion-implanted at one time.
[0008]
In FIG. 7, the ones indicated by the crosses are the impurities that have been ion-implanted, and are naturally also ion-implanted into the BPSG film 10 in the region surrounded by the resist mask 5.
However, after this ion implantation, an annealing step of, for example, about 700 to 800 degrees is required to diffuse impurities. At this time, the BPSG film is divided into a part where the impurity is further concentrated and introduced (region marked with x) and a BPSG film with a lower concentration (region not marked with x), and is subjected to the heat treatment. However, there is a problem that the contact is distorted.
[0009]
In particular, in FIG. 7, the BPSG film marked with a cross is denatured due to the ion implantation, the original stretchability is weakened, and the stretched BPSG film not marked with a cross is marked. It is thought that it cannot cope with the movement of. In particular, it is considered that the portion marked with x is formed of a hard film which expands due to heat but is hard to shrink. As a result, when many contacts are arranged, it is considered that the contacts at both ends may be inclined.
[0010]
Then, an eave is formed as shown by reference numeral 13, Ti is exposed from TiN 8, a radical reaction portion 14 with W, which is called a so-called volcano, occurs, and there is a problem that a contact failure occurs.
Referring to FIG. 8, the opening of the mask 5 is horizontally long, and the degree of distortion changes between the vertical side (the right side 15 and the left side 16) and the horizontal side (the upper and lower sides). In particular, it is considered that the contacts located near the right side 15 and the left side 16 tilt outward for the above-described reason.
[0011]
In addition, even in the case of Al, there is a problem that the step coverage is deteriorated at the eaves portion, and the resistance value is increased, the disconnection is caused, and the like.
[0012]
[Means for Solving the Problems]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problem, and both of the first and second embodiments have an impurity that is implanted on the surface of a BPSG film so as to reduce the contact resistance of a diffusion region, and is not implanted into the BPSG film. The problem is solved by providing an injection blocking film.
[0013]
Third, the problem is solved by forming the impurity injection blocking film from a SiO2 film or a TEOS film having a higher etching rate than the BPSG film.
Fourth, the problem is solved by forming a resist mask surrounding the contact hole to be long in one direction.
Particularly, in the case of the BPSG film, a contact hole is distorted during annealing due to a difference in impurity concentration. Therefore, if an insulating film serving as an impurity injection blocking film is provided so that impurities are not directly injected, the entire region of the BPSG film is not implanted with impurities, so that distortion during annealing can be balanced and deformation of contacts can be prevented.
[0014]
Further, if the impurity implantation preventing film is a SiO2 film or a TEOS film having an etching rate higher than that of the BPSG film, the surface of the opening portion is formed first by etching a natural oxide film in the contact hole or by a separately provided etching process. Due to the etching, a slight taper is formed, which further prevents the formation of the eaves.
Further, since the resist mask is provided, the deformation of the contact hole can be suppressed even if the resist mask into which the impurities are introduced has an unbalanced shape. Therefore, even if the size of the contact hole becomes smaller in the future and it becomes difficult to match the resist mask to each contact hole, ions can be implanted collectively in a certain group of contact holes.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of a semiconductor device and a method of manufacturing the same according to the present invention will be described with reference to the drawings.
First, in FIG. 1, a diffusion region 22 such as a source region and a drain region of a transistor as shown in FIG. 8, for example, is formed on a semiconductor substrate 21 of one conductivity type, and a substantially silicon oxide film is formed thereon. As the insulating film 23, a gate insulating film, a TEOS film and a glass film are laminated in several layers, and finally, a BPSG film 24 and a TEOS film 25 are laminated. If necessary, an NSG film (non-doped glass film) is laminated below the BPSG film 24.
[0016]
The BPSG film 24 is a Si glass film in which P is mixed at about 3 to 4 wt% and B is about 4 to 5 wt%. ing. If necessary, the BPSG film is etched back, and after the film formation, it is annealed in an N2 atmosphere at about 700 to 900 degrees for about 30 minutes. (However, some materials do not require annealing.) The NSG film functions as a stopper for impurities and is formed at about 2000 °.
[0017]
Subsequently, a photoresist (not shown) is formed, and the contact hole 26 is formed through an opening corresponding to the contact hole 26 to be formed. The etching here is realized by anisotropic plasma etching, and the gas is mainly CHF3 + CF4 + Ar.
Further, as described in FIG. 8, ions are implanted into the diffusion region 22 through a mask (photoresist in this case) 27 surrounding a group of the contact holes 26. In this case, the impurity is BF ions, and the conditions are an acceleration voltage of about 40 KeV and a dose of 3 × 10 15 / cm 2.
[0018]
Subsequently, after the resist 27 is removed, annealing is performed at 750 ° C. in an N 2 atmosphere for about 30 minutes for the purpose of diffusing the impurities. Wet etching is performed using an aqueous solution containing ammonium.
Here, a feature of the present invention is the impurity injection blocking film 25 formed on the BPSG film.
[0019]
Particularly, in the BPSG film, a strain is applied to the contact hole during the annealing due to a difference in impurity concentration. Therefore, if a film serving as a mask is provided so that the impurity is not implanted, the impurity is not implanted in the entire BPSG film. Therefore, the unbalance of the distortion of the BPSG film at the time of annealing can be removed over the entire region, and the deformation of the contact can be prevented.
[0020]
Further, if a SiO2 film or a TEOS film having an etching rate faster than that of the BPSG film is used, when the natural oxide film exposed in the contact hole is etched, the impurity implantation preventing film on the surface of the opening is etched first, so that a slight taper is formed. Formed, preventing the formation of eaves.
Even if the resist mask into which the impurities are introduced has an unbalanced shape as shown in FIG. 8, since the impurity injection blocking film 25 is provided, the BPSG film can be prevented from being deteriorated, and the deformation of the contact hole can be suppressed. it can. Therefore, even if the size of the contact holes becomes smaller in the future and it becomes difficult to align a mask with each contact hole, it is possible to implant ions collectively in a certain group of contact holes.
[0021]
Subsequently, as shown in FIG. 2, a barrier metal film is formed on the entire surface including the contact hole 26 by sequentially forming a Ti film 28 and a TiN film 29 by a sputtering method. Subsequently, as shown in FIG. Alternatively, a wiring film 30 made of an aluminum film is formed.
Here, when a contact plug made of a W film is buried in the contact hole via the barrier metal film and a wiring is formed on the contact plug, a W film 30 is formed by a CVD method as shown in FIG. Then, the tungsten film 31 is buried in the contact hole 26 by etching back the W film, and a wiring film 32 made of an aluminum film or the like is formed on the tungsten plug 31.
[0022]
As described above, if the impurity implantation blocking film 25 is provided on the BPSG film 24, the impurity for ion implantation is not introduced into the BPSG film by the impurity implantation blocking film. The distortion due to the heat treatment can be eliminated, and the formation of the eave as described in the conventional problem can be prevented.
Therefore, the barrier metal film composed of two layers can be uniformly laminated, Ti is not exposed from TiN, and volcano can be eliminated.
[0023]
In addition, as described above, when the SiO2 film or the TEOS film having an etching rate higher than that of the BPSG film is used, when the natural oxide film at the bottom of the contact hole is etched, the surface of the opening is etched first, so that a slight taper is formed. Thus, the formation of eaves can be prevented, and the volcano can be further suppressed.
On the other hand, the impurity injection blocking film 25 will be described briefly. For example, in the case of a TEOS film, there is a change in the film quality between the very surface portion of the ion-implanted TEOS film and the lower TEOS film not ion-implanted.
[0024]
That is, the surface of the ion-implanted TEOS film becomes hard, and the wet etching rate is lower than that of the other lower TEOS films.
Since anisotropic dry etching is employed in the etching of the contact hole in FIG. 1, the insulating film 23 including the substantial TEOS film 28 is cut almost vertically.
However, in the step of removing the natural oxide film at the bottom of the contact hole generated in the annealing step, since the above-described etchant (hydrofluoric acid + ammonium fluoride) is used, the TEOS film surface is hardly etched, and the TEOS film thereunder is etched. Have a tendency to be caught. As a result, some eaves are formed on the surface of the TEOS film.
[0025]
Therefore, in the present invention, the step of wet-etching the TEOS film is employed at the time of etching this natural oxide film or before this etching step, so that the eaves of the TEOS film can be removed, and the step generated here can be made smooth. it can.
An embodiment applied to a nonvolatile semiconductor memory device having a floating gate will be described with reference to FIGS.
[0026]
In FIG. 9, a source region 42 and a drain region 43 are formed on a surface layer of a P-type silicon semiconductor substrate 41 so as to be separated from each other. On both sides of the source region 42, floating gates 45 made of a polysilicon film made conductive via an insulating film 44 are formed. A control gate 47 made of a polysilicon film and a tungsten silicide (WSix) film is formed between the source region 42 and the drain region 43 with an insulating film 46 interposed therebetween. The end of the control gate 47 on the source region 42 side is disposed above the floating gate 45 with the insulating film 46 interposed therebetween.
[0027]
The source region 42 and the control gate 47 both extend in one direction (perpendicular to the plane of the paper), and a plurality of drain regions 43 and a plurality of control gates 47 are provided on both sides of the source region 42 in the one direction. Are arranged along. Then, the control gate 47 functions as a word line of the nonvolatile semiconductor memory device.
[0028]
On the silicon substrate 41, an interlayer insulating film 48 made of a TEOS film and a BPSG film is formed so as to cover the floating gate 45 and the control gate 47. A wiring film which is in contact with the drain region 43 through the contact hole 49 and functions as a bit line of the nonvolatile semiconductor memory device is formed.
[0029]
Here, the contact hole 49 in which the above-described wiring film is formed is formed in a high step portion of the nonvolatile semiconductor memory device in which the floating gate 45 and the control gate 47 are stacked as shown in FIG. Inevitably, when a wiring film formed by laminating aluminum, W, or the like in such a contact hole 49 via a barrier metal film is formed, the step coverage is deteriorated.
[0030]
In addition, step coverage is further deteriorated by the following points. The left side of FIG. 9 shows the cells of the nonvolatile semiconductor memory device as described above, and the right side shows one transistor 50 of a driving circuit for driving these memory cells. Impurities need to be implanted into the source / drain regions of the transistor 50 in order to reduce the contact resistance.
[0031]
By this ion implantation, since the uppermost insulating film has conventionally been a BPSG film, the characteristics of the BPSG film slightly change in the cell region where the ion implantation is not performed and the driving circuit region around the ion implantation. Further, after that, annealing for diffusing impurities of ion implantation is performed, so that distortion is applied between the cell region and the surrounding driving circuit group, and an eave is formed.
[0032]
In other words, in the stack of Ti, TiN, W plug, and Al, a volcano is generated by the eaves as shown in FIG. 7, and in the stack of Ti, TiN, and Al, there is a problem such as disconnection of Al.
However, in the present invention, a film 52 that does not allow impurities during ion implantation to reach the BPSG film 51 and is more easily etched than the BPSG film, here, a TEOS film or a SiO 2 film by CVD is provided on the BPSG film 51. I have.
[0033]
Therefore, since the impurity injection blocking film 52 is provided, the BPSG film 51 itself has a uniform impurity distribution over the entire region, and thus can suppress the eaves generated during annealing.
Thereafter, in the annealing step, a natural oxide film is formed on the exposed portion of the Si in the contact hole 49, so that hydrofluoric acid and ammonium fluoride (1: 100 is usually called buffered hydrofluoric acid) are used. Perform wet etching with an aqueous solution. In this wet etching, the opening is formed as a gentle step because the impurity injection blocking film is more positively etched than the BPSG film. Therefore, the coverage of the barrier metal is further improved.
[0034]
Here, if the amount of hydrofluoric acid in this etchant is small, the eaves may not be removed, but in this case, the amount of hydrofluoric acid may be increased.
As described above, the stacking of Ti, TiN, W plugs, and Al can prevent volcano and disconnection, and the stacking of Ti, TiN, and Al can prevent Al disconnection and the like.
[0035]
Subsequently, as shown in FIG. 10, a W film 54 is formed by a CVD method via a barrier metal film formed by sequentially forming a Ti film 52 and a TiN film 53 on the entire surface including the contact hole 49 by a sputtering method. By etching back the film, a tungsten plug is embedded in the contact hole 49, and a wiring film 55 made of an aluminum film or the like is formed on the tungsten plug.
[0036]
In this embodiment, an example in which the present invention is applied to a so-called split gate nonvolatile semiconductor memory device is described, but the present invention may be applied to a stacked gate nonvolatile memory device.
Further, the present invention can be applied to a single-layer film or a multilayer film having three or more layers as an insulating film.
[0037]
【The invention's effect】
According to the present invention, first, an impurity injection blocking film is provided on the surface of the BPSG film so that an impurity injected to lower the contact resistance of the diffusion region is not injected into the BPSG film. The impurity distribution becomes uniform, and the eaves of the contact generated at the time of annealing can be prevented.
[0038]
Further, by forming the impurity implantation preventing film from a SiO2 film or a TEOS film having a higher etching rate than the BPSG film, the impurity implantation inhibiting film is slightly etched in the etching of the natural oxide film generated in the exposed portion of the contact hole. As a result, a gentle step can be formed.
In addition, since there is an impurity injection blocking film, there is no problem if the conventional process of ion-implanting a plurality of contact holes at once, that is, the resist mask surrounding the contact holes is lengthened in one direction. Disappears.
[0039]
As a result, when W is adopted, the deterioration of volcano and step coverage can be prevented, and when Al is adopted, the step coverage can be prevented.
[Brief description of the drawings]
FIG. 1 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 4 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 5 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.
FIG. 6 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
FIG. 7 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
FIG. 8 is a view of a portion having a contact hole.
FIG. 9 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.
FIG. 10 is a sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

Claims (4)

A plurality of contact holes formed on an insulating film on a diffusion region in the semiconductor substrate and arranged in a row in one region; Ti and TiN are sequentially formed on a surface in the contact hole and a surface of the semiconductor substrate; In a semiconductor device having W or Al embedded thereon,
The impurities are implanted into the substrate surface of the contact hole, said insulating layer, lower layer rather is faster etching rate than the BPSG film is thereon a BPSG film, TEOS for preventing injection of the impurities relative to the BPSG film A semiconductor device characterized by stacking films. An insulating film formed on a semiconductor substrate, and at least an impurity injection blocking film formed thereon and having an etching rate higher than that of the insulating film, wherein the semiconductor substrate is formed by opening the impurity injection blocking film and the insulating film; A semiconductor device having a plurality of contact holes exposing the substrate and forming a row in one region,
  Impurities are implanted into the semiconductor substrate and the impurity implantation blocking film exposed to the plurality of contact holes in the one region, and the contact holes are filled with W through Ti and TiN formed on the surface of the contact holes. Alternatively, a semiconductor device having Al embedded therein. The semiconductor device according to claim 1, wherein the impurity is implanted into a region that is long in one direction and includes a plurality of contact holes in the one region. Forming a first insulating film on a surface of a semiconductor substrate having a diffusion region and planarizing the first insulating film; and forming a second insulating film having a higher etching rate than the first insulating film on the first insulating film. When,
  A plurality of contact holes arranged in rows are formed in the first and second insulating films, and a resist mask exposing a region where the plurality of contact holes are arranged is formed on the second insulating film. Process and
  Implanting impurities into the contact hole exposed in the one region and the second insulating film around the contact hole;
  Diffusing the impurities by heat treatment, and removing a natural oxide film formed on the contact holes and the second insulating film by wet etching;
  A step of sequentially laminating Ti and TiN on the entire surface including the contact hole and embedding W or Al in the contact hole.

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