JP3263657B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a BPSG film for planarization, and forming a Ti / TiN / W ( Or Al).

[0002]

2. Description of the Related Art A conventional semiconductor device and its manufacturing method will be described below with reference to the drawings. First, in FIG. 6, a contact hole 3 is formed in the insulating film 2 by anisotropic etching through a photoresist film in which a region corresponding to the contact hole 3 to be formed is opened in the insulating film 2 on the semiconductor substrate 1. Form. Note that the contact hole 3 exposes a diffusion region formed on the surface of the semiconductor substrate 1.

Here, four contact holes 3 are formed, and the corresponding drawing is shown in FIG. 9, and the diffusion region 4 of the transistor is shown by a two-dot chain line and a gate shown by a one-dot chain line. 6 contact holes 3 on both sides
・ Is formed. Then, as shown in FIG. 6 and FIG.
An impurity (for example, boron, phosphorus, arsenic, etc. ) for the purpose of reducing the contact resistance is ion-implanted into the diffusion region 4 through the mask 5.

Subsequently, as shown in FIG. 7, a barrier metal film is formed on the entire surface including the contact hole 3 by sequentially forming a Ti film 7 and a TiN film 8 by a sputtering method. Then, as shown in FIG. In order to form a tungsten plug, a W film (or aluminum film) 9 has been formed.
In recent years, the aspect ratio of a contact hole tends to increase with the progress of high integration and multilayer wiring of a semiconductor integrated circuit, and therefore, step coverage of a metal wiring film in the contact hole deteriorates, As a technique for solving the above-described problem, a contact plug made of a tungsten film or the like is buried in the contact hole via the barrier metal film, and a wiring is formed on the contact plug. .

[0005] That is, T
A W film 9 is formed by a CVD method via a barrier metal film formed by sequentially forming an i film 7 and a TiN film 8 by a sputtering method, and the tungsten film is etched back to form a tungsten plug in the contact hole 3. A wiring film made of an aluminum film or the like is formed on the buried tungsten plug.

[0006] These techniques are disclosed in, for example, JP-A-63-13.
No. 3648, and the like.

[0007]

In FIG. 8, a gate insulating film is formed in the lowermost layer of the insulating film 2, and several layers of a TEOS film, a glass film, and the like are stacked thereon, and finally, Has a BPSG film 10 formed to planarize the surface. When impurities are ion-implanted into the contact hole 3 in FIG. 6, a plurality of contacts are collectively surrounded by a mask 5 and ion-implanted at once as shown in FIG. For example, here, the contact of one transistor, that is, eight contact holes are surrounded by the mask 5 and ion-implanted at one time.

[0008] In FIG. 8, those indicated by crosses are the impurities implanted by ion implantation, and B in the region surrounded by the mask 5.
Naturally, ions are also implanted into the PSG film 10. However, after this ion implantation, for example, 70
This involves an annealing step of about 0 to 800 degrees. At this time, BP
The SG film has a portion in which the impurity is further concentrated (the region marked with x) and a BPSG film having a lower concentration (× region).
(A region without a mark), and there was a problem that the contact was distorted by the heat treatment.

[0009] In particular, in FIG. 8, the regions not marked with “x” tend to shrink during cooling, and the outer sides 11 and 12 of the left and right contact holes 3 tend to tilt outward.
Then, an eave is formed as shown by reference numeral 13, Ti is exposed from TiN 8, a radical reaction portion 14 with W called so-called volcano occurs, and there is a problem that a contact failure occurs.

Referring to FIG. 9, the opening of the mask 5 is horizontally long and has a vertical side (right side 15 and left side 16).
And the degree of distortion changes on the horizontal side (upper and lower sides),
In particular, contacts located near the right side 15 and the left side 16 tend to tilt outward. In addition, even in the case of Al, there is a problem that the step coverage is deteriorated at the eaves portion here, and the resistance value is increased, the wire is disconnected, and the like.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems. First, an insulating film surrounding a contact hole is formed of a BPSG film mainly for planarization. After the BPSG film has an etching rate higher than that of the BPSG film and is coated with an impurity implantation blocking film serving as a mask for ion implantation, and after opening the contact hole, when implanting ions into the contact hole, The problem is solved by trapping the impurities with the impurity injection blocking film except for the contact holes.

Particularly, in the BPSG film, a contact hole is distorted during annealing due to a difference in impurity concentration. Therefore, if an insulating film serving as an impurity injection blocking film is provided so that impurities are not directly injected, the entire area of the BPSG film is
Since impurities are not implanted, distortion imbalance during annealing can be achieved, and contact deformation can be prevented. Second,
In addition to the first means, the problem is solved by opening the contact hole after isotropically etching the impurity injection blocking film corresponding to the expected region of the contact hole.

Also in this case, the portion where the eaves are easily formed (the surface of the blocking film) is scraped off, which is effective for preventing the eaves from being formed. Third, the problem is solved by making the region to be ion-implanted a source region and / or a drain region of a transistor located around a nonvolatile semiconductor memory device group in which a floating gate and a control gate are stacked. .

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor device according to the present invention and a method for manufacturing the same will be described below with reference to the drawings. First, in FIG. 1, a diffusion region 22 such as a source region and a drain region of a transistor as shown in FIG.
On top of this, several layers of a gate insulating film, a TEOS film and a glass film are laminated as an insulating film 23 substantially composed of an oxide film of Si, and finally a BPSG film 24 and a TEOS film 25
(Which will be a later impurity injection blocking film). If necessary, an NSG film (non-doped glass film) is laminated below the BPSG film 24.

The BPSG film 24 has a P content of about 3 to 4 wt.
%, B is about 4 to 5 wt%, and is a Si glass film mixed with a main purpose of flattening the substrate surface.
About Å is formed. If necessary, BPSG
The film is etched back, and after the film formation , an N2 atmosphere, 8
Anneal for about 30 minutes at about 00 to 900 degrees. Also, the NSG film functions as a stopper for impurity diffusion, and
Approximately 000 ° is formed.

Subsequently, a contact hole 26 to be formed is formed.
The TEOS film 25 is isotropically etched by wet or dry through a photoresist PR having an opening corresponding to the above. Therefore, the eaves-forming portion shown in the conventional example, particularly the surface portion of the impurity implantation blocking film which is hardened due to the deterioration of the surface in the subsequent ion implantation is cut off, and a gentle step is formed.

Here, hydrofluoric acid + ammonium fluoride +
Although an acetic acid etchant is used, a hydrofluoric acid-based solution may be used. Subsequently, a contact hole 26 is formed via a photoresist PR. The etching here is realized by anisotropic plasma etching, and the gas is mainly CHF3 +
CF4 + Ar.

Further, as shown in FIG. 2, ions are implanted into the diffusion region 22 through a mask (see FIG. 9; photoresist here) surrounding a group of the contact holes 26. In this case, the impurity is BF ions, and the conditions are an acceleration voltage of about 40 KeV and a dose of 3.times.10@15 / cm @ 2. Subsequently, 750 is used for the purpose of diffusing the impurities.
Anneal for about 30 minutes in N2 atmosphere. NO in FIG.
As indicated, the Si exposed in absolutely the contact hole 26 to undergo the process of this annealing, such as a natural oxide film is formed.

For this reason, as shown in FIG. 3, in order to remove the natural oxide film NO, wet etching is performed using an aqueous solution containing hydrofluoric acid and ammonium fluoride. Here, the first feature of the present invention is the impurity injection blocking film 25 formed on the BPSG film. In particular, in the BPSG film, a strain is applied to the contact hole during the annealing due to a difference in impurity concentration. Therefore, if a film serving as a mask is provided so that impurities are not implanted, the entire region of the BPSG film is not implanted with impurities. Therefore, the unbalance of the distortion at the time of annealing can be taken over the entire area, and the deformation of the contact can be prevented.

Second, if an SiO2 film or a TEOS film having an etching rate higher than that of the BPSG film is used, the impurity implantation preventing film on the opening surface is etched first when the impurity implantation inhibiting film shown in FIG. 1 is etched. A slight taper R is formed to prevent the formation of the eaves. Further, since the mask 27 is provided, even if the mask into which the impurities are introduced has an unbalanced shape as shown in FIG. 9, the deformation of the contact hole is suppressed because the impurity injection blocking film 25 is provided. it can. Therefore, even if the size of the contact hole becomes smaller in the future and it becomes difficult to match the mask to each contact hole, ions can be implanted collectively in a certain group of contact holes.

Subsequently, as shown in FIG. 4, a barrier metal film is formed by sequentially forming a Ti film 28 and a TiN film 29 on the entire surface including the contact hole 26 by a sputtering method.
Subsequently, a wiring film made of a W film or an aluminum film is formed. Here, a contact plug made of a W film is buried in the contact hole via the barrier metal film,
When a wiring is formed on the contact plug, as shown in FIG. 5, a tungsten film is formed by a CVD method, and then the tungsten film is etched back so that a tungsten plug 31 is embedded in the contact hole 26 to form a tungsten film. A wiring film 32 made of an aluminum film or the like is formed on the plug 31.

As described above, if the impurity implantation preventing film 25 is provided on the BPSG film 24, impurities for ion implantation will not be introduced into the BPSG film by the impurity implantation inhibiting film. The entire film can suppress distortion due to heat treatment, and does not form an eave as described in the conventional problem. Therefore, the barrier metal film composed of two layers can be uniformly laminated, Ti is not exposed from TiN, and volcano can be eliminated when a W plug is formed.

As described above, the impurity implantation preventing film having a higher etching rate than the BPSG film, for example, SiO 2
If the film is a two film or TEOS film, the surface of the opening is etched first during the wet etching of the impurity injection blocking film in FIG. 1, so that a slight taper R is formed, and the formation of the eaves is prevented. Can be suppressed.

Next, an embodiment applied to a nonvolatile semiconductor memory device having a floating gate will be described with reference to FIGS. In FIG. 10, a source region 42 and a drain region 43 are formed on a surface layer of a P-type silicon semiconductor substrate 41 so as to be separated from each other. Also,
On both sides of the source region 42, a floating gate 45 made of a polysilicon film made conductive via an insulating film 44
Are formed. A control gate 47 made of a polysilicon film and a tungsten silicide (WSix) film is formed between the source region 42 and the drain region 43 with an insulating film 46 interposed therebetween. An end of the control gate 47 on the source region 42 side is disposed above the floating gate 45 with the insulating film 46 interposed therebetween.

The source region 42 and the control gate 47 both extend in one direction (perpendicular to the plane of the drawing), and a plurality of drain regions 43 and a plurality of control gates 47 are provided on both sides of the source region 42. They are arranged along the one direction. Then, the control gate 47 functions as a word line of the nonvolatile semiconductor memory device.

An interlayer insulating film 48 made of a TEOS film and a BPSG film is formed on the silicon substrate 41 so as to cover the floating gate 45 and the control gate 47. A wiring film which is in contact with the drain region 43 through a contact hole 49 formed as described above and functions as a bit line of the nonvolatile semiconductor memory device is formed.

Here, the contact hole 49 in which the above-described wiring film is formed is formed in a high step portion of the nonvolatile semiconductor memory device in which the floating gate 45 and the control gate 47 are stacked as shown in FIG. Therefore, it is inevitable that the contact hole 49 is deepened, and when a wiring film formed by stacking aluminum, W, or the like in such a contact hole 49 via a barrier metal film is formed, the step coverage is deteriorated. .

Further, step coverage is further deteriorated by the following points. The left side of FIG. 10 shows the cells of the nonvolatile semiconductor memory device as described above, and the right side shows one transistor 50 of a driving circuit for driving these memory cells. Impurities must be implanted into the source / drain regions of this transistor in order to reduce the contact resistance. Here, in order to suppress the cell leakage current,
Only the transistors around the group are ion-implanted.

By this ion implantation, the uppermost insulating film is conventionally a BPSG film. Therefore, in the cell region where the ion implantation is not performed and the driving circuit region around the ion implantation,
The characteristics of the BPSG film change slightly. Moreover, after that, annealing for diffusing impurities of ion implantation is performed, so that distortion is applied between the cell region and the peripheral driving circuit group, and an eave is formed.

That is, in the lamination of Ti, TiN, W plug, and Al, a volcano due to the eaves is generated as shown in FIG. 8, and in the lamination of Ti, TiN, Al, there is a problem such as disconnection of Al. However, in the present invention, the BPSG film 51
On top of this, there is provided a film 52 that does not allow impurities during ion implantation to reach the BPSG film 51 and is more easily etched than the BPSG film, here a TEOS film or a SiO 2 film by CVD.

Accordingly, in the present invention, first, as described in FIG. 1, the impurity implantation preventing film 52 is first wet etched to form a gentle step R. Second, since the impurity implantation blocking film 52 is provided to prevent impurity ion implantation, the BPSG film 51 itself has a uniform impurity distribution over the entire region, and suppresses eaves generated during annealing.

Therefore, the coverage of the barrier metal is further improved, and the stacking of Ti, TiN, W plug, and Al can prevent volcano and disconnection.
In the stacking of Al, disconnection or the like of Al can be prevented. continue,
As shown in FIG. 11, after the natural oxide film in the contact hole is removed, a Ti film 52 and a TiN film 53 are sequentially formed on the entire surface including the contact hole 49 by a sputtering method. CVD of film 54
And a tungsten plug is buried in the contact hole 49 by etching back the W film.
A wiring film 55 made of an aluminum film or the like is formed on the tungsten plug.

In this embodiment, an example is shown in which the present invention is applied to a so-called split gate nonvolatile semiconductor memory device. However, the present invention may be applied to a stacked gate nonvolatile memory device. Further, the present invention can be applied to a single-layer film or a multilayer film having three or more layers as an insulating film.

The present invention is applicable not only to contact holes but also to a case where wiring such as via holes is connected.

[0035]

According to the present invention, first, an insulating film surrounding a contact hole is formed of a BPSG film mainly for planarization, and thereafter, the BPSG film is formed on the BPSG film.
When an impurity implantation preventing film serving as a mask for ion implantation is covered with an etching rate faster than that of the film and the contact hole is opened, and when the impurity is ion-implanted into the contact hole, the impurity implantation except for the contact hole is performed. By trapping the impurities with a blocking film,
Deformation of the opening of the contact hole, that is, suppression of formation of an eave can be realized.

In particular, if an insulating film serving as an impurity injection blocking film is provided, the entire region of the BPSG film is not implanted with impurities, so that the distortion imbalance at the time of annealing can be taken and the contact can be prevented from being deformed. Secondly, in addition to the first means, the contact hole is opened after isotropically etching the impurity injection blocking film corresponding to the predetermined region of the contact hole, so that a more gentle taper shape is obtained, and the eaves are formed. Prevention can be realized.

Third, the regions to be ion-implanted are formed as source regions and / or drain regions of transistors located around a nonvolatile semiconductor memory device group in which a floating gate and a control gate are stacked. The formation of the eaves of the opening of the contact hole can be suppressed, and a good electrode formation can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 7 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 8 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 9 is a view of a portion having a contact hole.

FIG. 10 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 11 is a sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 29/792 (72) Inventor Katsuhiko Iizuka 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (56) References JP-A-7-254574 (JP, A) JP-A-9-171972 (JP, A) JP-A-6-37087 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name ) H01L 21/3205 H01L 21/3213 H01L 21/768

Claims (3)

(57) [Claims] 1. A contact hole is formed on an insulating film on a diffusion region formed in a semiconductor substrate. Ti and TiN are sequentially laminated on the surface of the insulating film including the inside of the contact hole, and W is formed thereon. Alternatively, in a method of manufacturing a semiconductor device in which Al is embedded, an insulating film surrounding the contact hole is formed of a BPSG film mainly for planarization, and thereafter, an etching rate on the BPSG film is lower than that of the BPSG film. Is fast, and covers the impurity implantation blocking film serving as a mask for ion implantation,
A method of manufacturing a semiconductor device, characterized in that when the impurity is ion-implanted into the contact hole after the opening of the contact hole, the impurity is trapped by the impurity injection blocking film except for the contact hole. 2. A contact hole is formed on an insulating film on a diffusion region formed in a semiconductor substrate made of Si, and Ti, T is formed on the surface of the insulating film including the inside of the contact hole.
In a method of manufacturing a semiconductor device in which iN is sequentially stacked and W or Al is buried thereon, an insulating film surrounding the contact hole is formed of a BPSG film mainly for planarization, and thereafter, the contact hole is formed. An impurity implantation blocking film, which has a higher etching rate than the Si oxide film exposed to the substrate and serves as a mask for ion implantation, is coated on the BPSG film, and thereafter, the impurity implantation blocking film corresponding to the predetermined region of the contact hole is formed. After isotropically etching, a contact hole was opened, and when impurities were ion-implanted into the contact hole, the impurities were trapped by the impurity injection blocking film except for the contact hole, and the Si oxide film was etched. rear,
A method of manufacturing a semiconductor device, comprising laminating Ti and TiN. 3. The ion implantation region according to claim 1, wherein a source region and / or a drain region of a transistor located around a nonvolatile semiconductor device storage device group in which a floating gate and a control gate are stacked. A method for manufacturing a semiconductor device according to claim 2.