JP3560003B2 - Digital processing equipment - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technology effective when applied to a digital processing device, and further to digital processing in which arithmetic processing in which data is rounded down in the same processing system is repeated a plurality of times, for example, a digital demodulation unit of a mobile phone The present invention relates to a technique which is effective for use in an error correction circuit in the above.
[0002]
[Prior art]
For example, a digital modulation type mobile phone demodulates digital data based on phase difference information detected from a received signal. At this time, the phase difference information contains some error due to various conditions such as radio wave propagation. Therefore, in order to accurately perform data demodulation, it is necessary to perform an error correction process by calculation.
[0003]
It is desirable that this correction process be performed with as high accuracy as possible. In particular, when the digitized phase difference information is corrected by a plurality of digital operations, it is necessary to pay attention to accumulation of errors due to truncation of lower bits. For example, in digital division processing, fractional rounding of lower bits is performed. When such division processing is repeated, errors of the fractions rounded down in each division processing are accumulated, and eventually a large error that cannot be ignored may occur.
[0004]
In order to avoid this kind of error, the inventors of the present invention have studied and found that the operation accuracy in each operation process is one rank or more higher than the final target accuracy, and then the individual operation results are On the other hand, it has been found that it is effective to perform the rounding processing for each.
[0005]
As for the mobile phone which is one application field of the present invention, for example, Nikkei BP, “Nikkei Electronics September 12, 1994 (No. 617)”, page 7196 (special feature: weight reduction and price reduction) The outline is introduced in (Competing mobile phone mounting technology).
[0006]
[Problems to be solved by the invention]
However, the present inventors have clarified that the above-described technique has the following problems.
[0007]
That is, the accumulation of errors in the case of repeating arithmetic processing that causes data to be rounded down, such as division, can be solved by rounding off in each arithmetic processing. Accuracy must be at least one rank higher than the final target accuracy. However, in order to realize this, there arises a problem that the arithmetic processing speed is reduced or the scale of the arithmetic processing circuit is significantly increased.
[0008]
SUMMARY OF THE INVENTION An object of the present invention is to effectively avoid accumulation of errors due to repeated arithmetic processing without lowering the arithmetic processing speed or significantly increasing the scale of the arithmetic processing circuit, and to reduce the accuracy of the processing scale. An object of the present invention is to provide a technology that enables high digital processing.
[0009]
The above and other objects and features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0010]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0011]
That is, in a digital processing device in which a plurality of digital arithmetic processes are executed by the same processing system, the lower-order bits are rounded down and rounded up at the same precision level with respect to the arithmetic result in each arithmetic process. That is.
[0012]
According to the above-described means, it is possible to obtain an operation result equivalent to that obtained by finally performing the rounding operation process by only a simple round-up operation without significantly increasing the operation accuracy in each operation process. .
[0013]
As a result, it is possible to effectively avoid accumulation of errors due to arithmetic processing and reduce the scale of the arithmetic processing circuit, thereby enabling digital processing with high accuracy for the processing scale. Is achieved.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
[0015]
In the drawings, the same reference numerals indicate the same or corresponding parts.
[0016]
FIG. 1 shows an embodiment of a digital processing device to which the technology of the present invention is applied.
[0017]
The digital processing apparatus of the embodiment shown in FIG. 1 constitutes an error correction circuit when demodulating digital data from phase difference information detected from a received signal in a digital modulation type mobile phone. Is a transmitting / receiving antenna, 102 is a duplexer, 200 is a wireless receiving unit, and 300 is a wireless transmitting unit.
[0018]
In the figure, reference numeral 201 denotes a detection circuit that detects phase difference information from a received signal, 202 denotes an AD converter that digitizes the output of the detection circuit 201, and 203 performs error correction of the digitized detection output, that is, phase difference information. An error correction circuit 204 is an encoder that demodulates digital data from the error-corrected phase difference information.
[0019]
Here, the error correction circuit 203 includes a first correction circuit unit 4 and a second correction circuit unit 5. The two correction circuit units 4 and 5 are cascade-connected, and execute a correction process with the same processing accuracy in the same processing system.
[0020]
The first correction circuit section 4 includes an error detection circuit 41, an average value calculation circuit 42 including an accumulation circuit 43 and a subtraction circuit 44, and a subtraction circuit 45, and includes clocks kφ (32 × 6 KHz = 192 KHz) and φ (6 KHz). , The 6-bit input data (digitized phase difference information) D1 is primarily corrected by digital arithmetic processing.
[0021]
The second correction circuit unit 5 includes an error detection circuit 51, an average value calculation circuit 52 including an accumulation circuit 53 and a subtraction circuit 54, and a subtraction circuit 55. The clocks kφ (32 × 6 KHz = 192 KHz) and φ (6 KHz) Under the synchronization, the 6-bit input data (digitized phase difference information) D2 primary corrected by the first correction circuit unit 4 is secondarily corrected by digital arithmetic processing.
[0022]
To describe each part in more detail, in the first correction circuit part 4, the error detection circuit 41 determines four reference values “001000” (8 in decimal) and “011000” (10) for the 6-bit input data D1. Differences with respect to 24), "101000" (40 in decimal), and "111000" (56 in decimal) are obtained and output as error data b1. The detection of the error data b1 is realized by extracting the lower 4-bit data a1 from the 6-bit input data D1, and logically inverting only the most significant bit of the lower 4-bit data. This error detection is performed in synchronization with a predetermined clock kφ (32 × 6 KHZ = 192 KHz).
[0023]
The average value calculation circuit 42 obtains the average error data d1 by integrating the error data b1 by the integration circuit 43 and dividing the integrated data c1 by the division circuit 44. In this case, the integrating circuit 43 outputs k (32) integrated data c1 of the error data b1 detected every 1 / kφ (1/192 KHz), and the dividing circuit 44 outputs the k integrated data. The average error data d1 obtained by dividing c1 by k is output. Thus, the average error data d1 for each 1 / φ (1/6 KHz) period is output.
[0024]
The subtraction circuit 45 subtracts the average error data d1 from the original input data D1. As a result, a correction is made to offset the error contained in the input data D1, that is, the deviation from the four reference values, with the average error data d1. Thus, the primary correction of the input data D1 is performed. This primary correction data D2 is sent to the second correction circuit unit 5.
[0025]
The second correction circuit unit 5 converts the 6-bit input data (digitized phase difference information) D2 primary corrected by the first correction circuit unit 4 into the same arithmetic processing as that of the first correction circuit unit 4. To perform secondary processing. That is, error data b2 is detected by extracting only lower-order 4 bits of data a2 from 6-bit data D2 subjected to primary correction. The error data b2 is integrated by k pieces, and the integrated data c2 is divided by k to obtain average error data d2 for each 1 / φ period. Then, by subtracting the average error data d2 from the primary corrected data D2, secondary corrected data D3 obtained by further correcting the primary corrected data D2 is obtained. This secondary correction data D3 is sent to the encoder 204 and used for data demodulation.
[0026]
Here, in the division circuit 44 in the first correction circuit unit 4 and the division circuit 54 in the second correction circuit unit 5, fractional truncation of the lower one bit occurs due to the division processing. If this rounding down is repeated twice, errors due to rounding down twice are accumulated in the final correction processing result, that is, the secondary correction data D3 as it is. May not be possible.
[0027]
Therefore, in the error correction circuit 204 of the embodiment, the lower one bit “1” is added by the subtraction circuit 55 in the second correction circuit unit 5. As a result, the first correction circuit unit 4 performs an arithmetic process in which lower bits are rounded down, while the second correction circuit unit 5 performs an arithmetic process in which lower bits are rounded up.
[0028]
As described above, in a digital processing device in which a plurality of digital arithmetic processes are executed by the same processing system, the lower-order bits are rounded down and rounded up at the same precision level with respect to the arithmetic result of each arithmetic process. By doing so, it is possible to finally obtain an operation result equivalent to that obtained by performing the rounded operation without significantly increasing the operation accuracy in each operation.
[0029]
As a result, accumulation of errors due to the arithmetic processing is effectively avoided without lowering the arithmetic processing speed or significantly increasing the scale of the arithmetic processing circuit, and digital processing with high accuracy is performed for the division of the processing scale. Become like
[0030]
FIG. 2 shows an embodiment in which each part of the error correction circuit 104 shown in FIG. 1 is shown in more detail. In the figure, error detection circuits 41 and 51 are constituted by inverters (phase inversion circuits) 411 and 511 for inverting the logic of only the most significant bit.
[0031]
The average value calculation circuits 42 and 52 include integration circuits 43 and 53 and division circuits 44 and 54. In this case, the integrating circuits 43 and 53 are constituted by adding circuits 431 and 531 and data latch circuits 432 and 532 for holding the added outputs of the adding circuits 431 and 531. The integration operation is performed by repeating returning to the input side of the addition circuits 431 and 531. The division circuits 44 and 54 are constituted only by circuits for extracting only the upper 4 bits of the integration result. That is, assuming that the integrated data c1 and c2 output from the integrating circuits 43 and 53 are 9 bits, and only the upper 4 bits are extracted, the extracted upper 4 bits of data are converted to the 9-bit integrated data c1. , C2 are equivalent to the data (d1, d2) obtained by performing division by rounding down to a divisor of 32. In this way, the division process involving the truncation of the lower bits is realized.
[0032]
The average error data d1 obtained by the average value calculation circuits 42 and 52 is transferred as a subtraction number to the subtraction circuits 45 and 55 every 1 / φ period via the data latch circuits 46 and 56.
[0033]
The subtraction circuits 45 and 55 are composed of complement circuits 451 and 551 and addition circuits 452 and 552. The average error data d1 and d2 from the average value calculation circuits 42 and 52 are logically converted into complements by the complement circuits 451 and 452 and then input to the addition circuits 452 and 552, where they are added to the input data D1 and D2. As a result, error correction for subtracting the average error data d1 and d2 from the input data D1 and D2 is performed. At this time, the addition circuit 452 in the first correction circuit unit 4 adds the complement of the average error data d1 as it is, but the addition circuit 552 in the second correction circuit unit 5 1 is added extra. The addition of 1 is realized by giving "1" to the lower carry (carry) CI of the adder circuit 552. The circuit for applying "1" only needs to pull-up the terminal of the lower carry CI to the power supply potential (logic level of "1").
[0034]
As a result, the lower bits of the correction data D2 of the first correction circuit unit 4 are rounded down, but the lower bits of the correction data D3 of the second correction circuit unit 5 are rounded up. The same effect as when the rounding operation is performed can be obtained.
[0035]
FIG. 3 shows another embodiment of the present invention.
[0036]
The difference from the above-described embodiment will be described. In the embodiment shown in FIG. 2, lower bits are rounded down and rounded up by the subtraction circuits 45 and 55, whereas in the embodiment shown in FIG. Bits are rounded down and rounded up by the average value calculation circuits 42 and 52.
[0037]
That is, in the average value calculation circuit 42 in the first correction circuit unit 4, when the data latch circuit 432 holding the addition output of the addition circuit 431 is initialized every 1 / φ period, its initial value is 0 ( Zero) is preset. On the other hand, in the average value calculation circuit 52 in the second correction circuit section 5, when the data latch circuit 532 holding the addition output of the addition circuit 531 is initialized every 1 / φ period, its average value is 32 ( (corresponding to the value of k) is preset. A preset circuit 533 has an initial value of 32.
[0038]
As a result, in the average value calculation circuit 42 in the first correction circuit unit 4, when the integrated data c1 is divided by the divisor 32, fraction bits are truncated. On the other hand, in the average value calculation circuit 52 in the second correction circuit unit 5, when the integrated data c2 is divided by the divisor 32, 32 equal to the divisor 32 is added to the integrated data c1 in advance. , 1 is added to the result of the division. That is, in the average value calculation circuit 52 in the second correction circuit section 5, the lower one bit is substantially rounded up.
[0039]
Therefore, also in this embodiment, the lower bits of the correction data D2 of the first correction circuit unit 4 are truncated, but the lower bits of the correction data D3 of the second correction circuit unit 5 are rounded up. As a result, the same effect as that of the rounding operation is finally obtained.
[0040]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and it can be said that various modifications can be made without departing from the gist of the invention. Not even. For example, a configuration may be employed in which arithmetic processing in which lower bits are truncated is performed three or more times. In this case, the lower bits are rounded off and rounded up in each operation. Further, a configuration may be adopted in which arithmetic processing such as division is performed by software using a microprocessor.
[0041]
In the above description, mainly the case where the invention made by the present inventor is applied to an error correction circuit in digital demodulation which is the field of application as the background has been described. However, the present invention is not limited to this. It can also be applied to digital signal processing.
[0042]
【The invention's effect】
The effects of typical inventions disclosed in the present application will be briefly described as follows.
[0043]
That is, it is possible to effectively avoid accumulation of errors due to arithmetic processing and to perform digital processing with high accuracy for the processing scale without lowering the arithmetic processing speed or significantly increasing the scale of the arithmetic processing circuit. Is obtained.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of a digital processing device to which the technology of the present invention is applied. FIG. 2 is a circuit diagram showing details of the digital processing device shown in FIG. 1 more specifically. Circuit diagram showing another embodiment of the present invention.
101 transmitting / receiving antenna 102 duplexer 200 wireless receiving unit 300 wireless transmitting unit.
201 detection circuit 202 AD converter 203 error correction circuit 204 encoder 4 first correction circuit section 5 second correction circuit section 41, 51 error detection circuit 42, 52 average value calculation circuit 43, 53 integration circuit 431, 531 addition circuit 432, 532 Latch circuits 44, 54 Division circuits 45, 55 Subtraction circuits 451, 551 Complement circuits 452, 552 Addition circuits 533 Preset circuits 46, 56 Latch circuits kφ Clock (192 KHz)
φ clock (kφ / k = 6 KHz)
D1 Input data D2 Primary correction data D3 Secondary correction data a1, a2 Lower 4-bit data b1, b2 Error data c1, c2 Integration data d1, d2 Average error data

Claims (2)

A first error detection circuit for extracting a difference between digital input data with respect to a digital reference value, a first average value calculation circuit for calculating an average of output data of the first error detection circuit, and an output data of the first calculation circuit; A first subtraction circuit that performs a subtraction process between input data, a first correction circuit that performs primary correction of the input data,
A second error detection circuit that extracts a difference between a primary correction data output from the first correction circuit and a reference value, a second average value calculation circuit that calculates an average value of output data of the second error detection circuit, A second subtraction circuit that performs a subtraction process between output data of a second average value calculation circuit and the primary correction data, and a second correction circuit that performs a secondary correction of the input data;
The first correction circuit performs one of a rounding up and a rounding down of a fraction of lower bits generated in the first average value calculation circuit,
The error correction circuit, wherein the second correction circuit performs one of a rounding up and a rounding down of a fraction of a lower bit generated in the second average value calculation circuit. 2. The error correction circuit according to claim 1, wherein one of the first and second correction circuits that performs round-up adds 1 in the corresponding first or second subtraction circuit. 3.

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