JP3551961B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a small-sized semiconductor device having the same size as a semiconductor chip and a method for manufacturing the same, and more particularly, to a method in which a metal wiring connected to an electrode of a semiconductor chip is two-dimensionally re-wired on a resin, A part of which functions as an external terminal and a method of manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, as electronic devices have become smaller and more sophisticated, CSPs (Chip Size Packages) have been developed as small, multi-terminal semiconductor devices.
[0003]
In particular, in a semiconductor device in which metal wiring connecting the electrodes on the surface of the semiconductor chip to the external terminals is formed, even if the electrode pitch on the semiconductor chip is narrow, the positions of the external terminals of the metal wiring can be arranged two-dimensionally. In addition, attention has been paid to a semiconductor device which has an improved degree of freedom in the position of an external terminal, and which realizes a reduction in size and an improvement in mountability of the semiconductor device.
[0004]
Hereinafter, a conventional semiconductor device will be described with reference to the drawings.
[0005]
11 is a perspective view showing a conventional semiconductor device, FIG. 12 is an enlarged perspective view of an end of the semiconductor device shown in FIG. 11, and FIG. 13 is a cross-sectional view taken along a line AA 'in FIG. FIG. 14 is a sectional view taken along the line BB ′ in FIG.
[0006]
First, as shown in FIGS. 11 and 12, an electrode 2 is formed on the upper surface of the semiconductor chip 1 and a passivation film 3 is formed around the electrode 2, and a first insulating resin 4 is further formed on the upper surface of the passivation film 3. Above each electrode 2 of the semiconductor chip 1, the first insulating resin 4 has a contact hole 5 opened in a circular shape. A metal wiring 6 plated with a metal such as Cu is formed from the inner wall of the contact hole 5 to the periphery of the upper portion. Since a conductive material is formed on the inner wall of the contact hole 5, the contact hole 5 is electrically connected to the electrode 2 of the semiconductor chip 1, and the contact hole 5 and the external electrode 7 are connected to the first electrode. Are electrically connected by a metal wiring 6 formed on the upper surface of the insulating resin 4. A ball electrode 8 made of solder or the like is mounted on the external electrode 7. Via the ball electrode 8, a wiring electrode of a mounting board (not shown) on which a semiconductor device is mounted and an external electrode 7 of a metal wiring 6 are formed. Are electrically connected. A second insulating resin 9 is formed on the upper surfaces of the metal wiring 6 and the first insulating resin 4 to cover the metal wiring 6.
[0007]
Next, the sectional structure of the contact hole and the metal wiring will be described in detail.
[0008]
Note that the description of the same contents as those described with reference to FIGS. 11 and 12 will be omitted.
[0009]
As shown in FIGS. 13 and 14, a seed layer 11 is formed on the upper surface of the metal barrier 10 formed on the upper surface of the electrode 2 of the semiconductor chip 1, and a metal wiring 6 is formed on the upper surface of the seed layer 11. I have.
[0010]
Here, the limit of the minimum distance between contact holes in a conventional semiconductor device will be described.
[0011]
As shown in FIG. 13, the diameter of the opening of the first insulating resin 4 formed above the electrode 2 of the semiconductor chip 1 is d, and the inner wall of the contact hole 5 and the end of the metal wiring 6 formed around it. The distance between them is S, the distance from the periphery of the contact hole 5 to the end of the metal wiring 6 is O, and the distance between the electrodes 2 of the semiconductor chip 1 is P.
[0012]
Here, the contact hole 5 formed in the first insulating resin 4 is formed by applying an insulating resin made of a photosensitive polyimide or the like, exposing and developing, and then thermosetting, but from the limit of the resolution of the insulating resin, The minimum value of the diameter d of the opening of the contact hole 5 is 40 [μm]. Further, the distance O needs to be 1 to 3 [μm] or more from the processing accuracy when the metal barrier 10 and the seed layer 11 are wet-etched, and is about 10 [μm] or more including the variation in the manufacturing process. In addition, the interval S between the metal wires 6 is about 20 [μm] as a minimum value when the thickness of the metal wire 6 is 10 [μm] due to the limit of processing accuracy when the metal barrier 10 and the seed layer 11 are wet-etched. .
[0013]
Therefore, the pitch P of the electrodes 2 of the semiconductor chip 1 is at least the sum of the distances d, O, and S, and is required to be 80 [μm] or more.
[0014]
[Problems to be solved by the invention]
However, in the conventional semiconductor device, when a large number of electrodes are arranged around the semiconductor chip, it is necessary to reduce the distance between the electrodes. However, the electrodes of the semiconductor chip and the metal wiring are electrically connected by the contact holes. Therefore, there is a restriction that the distance between adjacent contact holes cannot be smaller than the diameter of the contact holes.
[0015]
For example, when 400 semiconductor chip electrodes are arranged around a semiconductor chip having one side of 5 [mm], the interval between adjacent semiconductor chip electrodes must be at least 50 [μm] or less. However, in the conventional semiconductor device, the minimum pitch between the adjacent semiconductor chip electrodes 2 is required to be 80 [μm] or more, so that 400 electrodes cannot be arranged.
[0016]
As described above, even if an attempt is made to reduce the distance between the electrodes of the semiconductor chip, there is a problem that the distance between the metal wirings connected to the contact holes cannot be reduced due to the accuracy of forming the contact holes. A semiconductor device capable of coping with a narrow pitch between electrodes of a semiconductor chip without being affected by a size of a contact hole electrically connected to an electrode formed on the semiconductor chip, and a method of manufacturing the same. With the goal.
[0017]
[Means for Solving the Problems]
In order to solve the conventional problem, a semiconductor device of the present invention includes a semiconductor chip on which an electrode is formed, a first insulating resin formed on a surface of the semiconductor chip by opening a portion of the electrode, One end connected to the electrode, the other end extending to the surface of the first insulating resin, a metal wiring having a width smaller than the width of the electrode, and an external electrode terminal formed on the surface of the metal wiring. A second insulating resin formed on the surface of the first insulating resin and the surface of the metal wiring, the opening being provided at a portion of the external electrode terminal.
[0018]
In addition, a passivation film is formed between the surface of the semiconductor chip and the first insulating resin, and the electrodes of the semiconductor chip are formed in portions where the passivation film is opened.
[0019]
Also, a plurality of electrodes are arranged on the surface of the semiconductor chip at predetermined intervals.
[0020]
Further, the opening of the first insulating resin is larger than the opening of the passivation film, and the first insulating resin does not contact the electrodes of the semiconductor chip.
[0021]
Further, the first insulating resin is in contact with the electrode of the semiconductor chip.
[0022]
According to the semiconductor device of the present invention, since the width of the metal wiring is formed smaller than the width of the opening of the electrode of the semiconductor chip, an electrode pitch smaller than that of the conventional electrode structure having the contact hole can be realized. Can be.
[0023]
In the method of manufacturing a semiconductor device according to the present invention, a step of forming a first insulating resin on a surface of a semiconductor chip on which an electrode is formed, and a step of forming a portion of the first insulating resin on the surface of the electrode, Removing; forming a metal wiring having a width smaller than the width of the electrode on the surface of the first insulating resin and the surface of the electrode; forming a second insulating resin on the surface of the metal wiring A step of partially removing the second insulating resin to expose a part of the metal wiring, and a step of forming an external electrode terminal at an exposed portion of the metal wiring.
[0024]
Further, before the step of forming the first insulating resin, a step of forming a passivation film on a portion of the surface of the semiconductor chip other than the electrodes is provided, and after the step of forming the metal wiring, a resist is formed on the surface of the metal wiring. A step of forming a material and a step of selectively removing the resist material are provided, wherein a removed portion of the resist material is smaller than an opening of the passivation film.
[0025]
By forming a conventional electrode structure having no contact hole by the method of manufacturing a semiconductor device of the present invention, the width of a portion of a metal wiring formed on the surface of an electrode of a semiconductor chip can be reduced, It is possible to reduce the pitch between the metal wirings in response to the narrowing of the pitch between the electrodes.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of a semiconductor device and a method of manufacturing the same according to the present invention will be described with reference to the drawings.
[0027]
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
[0028]
1 is a perspective view showing the semiconductor device of the present embodiment, FIG. 2 is an enlarged view of FIG. 1, FIG. 3 is a cross-sectional view taken along the line AA ′ of FIG. 2, and FIG. It is sectional drawing of the BB 'part of FIG.
[0029]
As shown in FIG. 1, a plurality of electrodes 13 made of Al-Si or Al-Si-Cu are formed around a semiconductor chip 12, and a portion made of a low-elastic resin is formed in a portion other than a region where the electrodes 13 are formed. The first insulating resin 14 is formed, one end of the metal wiring 15 is electrically connected to the electrode 13 of the semiconductor chip 12, and the metal wiring 15 is connected to the first insulating resin 14 via the side surface of the first insulating resin 14. The other end of the metal wiring 15 is configured as, for example, a circular metal land 16. The second insulating resin 17 is formed on the surface of the semiconductor chip 12, the surface of the metal wiring 15, and the surface of the first insulating resin 14, but the metal land 16 is open. A ball electrode 18 made of solder is connected as an external electrode terminal to the metal land 16 exposed at the opening of the second insulating resin 17. Here, in the present embodiment, the opening of the first insulating resin 14 in the vicinity of the electrode 13 of the semiconductor chip 12 (the portion where the first insulating resin 14 is not formed) is the electrode of the semiconductor chip 12 of the passivation film 19. Since it is larger than the opening of the portion 13, the end surface of the first insulating resin 14 does not cover the opening of the passivation film 19.
[0030]
Next, the structure near the electrode of the metal wiring will be described in detail.
[0031]
As shown in FIG. 2, a passivation film 19 made of a polyimide resin is formed on the surface of the semiconductor chip 12 so as to open the electrode 13 of the semiconductor chip 12. As a feature of this embodiment, the width of one end of the metal wiring 15 connected to the electrode 13 of the semiconductor chip 12 is smaller than the width of the electrode 13 of the semiconductor chip 12. Therefore, the distance between the metal wirings 15 in the vicinity of the electrodes 13 of the semiconductor chip 12 can be reduced as compared with the conventional electrode structure having a contact hole, and the pitch of the electrodes 13 of the semiconductor chip 12 can be reduced.
[0032]
Next, as shown in FIG. 3, a metal barrier 20 is formed on the surface of the electrode of the semiconductor chip 12, a plating seed layer 21 is formed on the surface of the metal barrier 20, and a plating seed layer 21 is further formed on the surface of the plating seed layer 21. Has a metal wiring 15 formed thereon. The feature of this embodiment is that the width of the metal barrier 20, the width of the plating seed layer 21, and the width of the metal wiring 15 are smaller than the width of the opening of the passivation film 19 in the electrode 13 of the semiconductor chip 12. That is, the interval S between the metal wirings 15 and the width W of the metal wiring 15 are determined by the formation limit of the plating resist when plating the metal wiring 15 (the thickness of the resist with respect to the plane area of the portion where the plating resist is selectively removed). In general, when the thickness of the metal wiring 15 is 10 [μm], the minimum S = 20 [μm] and W = 20 [from the ratio: aspect ratio) and the etching limit when the metal barrier 20 and the plating seed layer 21 are wet-etched. μm]. Therefore, the minimum pitch between the electrodes 13 of the adjacent semiconductor chips 12 is the sum of S and W, and is generally about 40 [μm].
[0033]
As described above, since the semiconductor device of the present embodiment includes the metal wiring smaller than the width of the electrode of the semiconductor chip, the minimum distance P between the electrodes of the adjacent semiconductor chips is limited to the formation limit of the metal wiring width W and the metal wiring interval S. Dependent. For this reason, P can generally be formed to a minimum of about 40 [μm], and can be applied to a smaller, multi-pin semiconductor chip.
[0034]
Next, another embodiment of the semiconductor device will be described.
[0035]
FIG. 5 is a perspective view showing the semiconductor device of the present embodiment, and FIG. 6 is a cross-sectional view taken along the line CC ′ of FIG. The same contents as those in the first embodiment are omitted, and the same components are denoted by the same reference numerals.
[0036]
As shown in FIGS. 5 and 6, the end of the first insulating resin 14 formed on the surface of the passivation film 19 on the surface of the semiconductor chip 12 covers a part of the electrode 13 of the semiconductor chip 12, Is in contact with the electrode 13 of the semiconductor chip 12, but the metal wiring 15 re-wired on the surface of the first insulating resin 14 is formed by the first insulating resin 14 of the electrode 13 of the semiconductor chip 12. It is connected to an uncovered portion (opening) 22. In the present embodiment, the opening of the first insulating resin 14 in the electrode 13 of the semiconductor chip 12 is on the end side of the semiconductor chip 12, and the metal wiring 15 is connected to the opening 22 of the electrode 13 of the semiconductor chip 12. Is what it is.
[0037]
As described above, since a part of the first insulating resin is formed so as to cover the electrodes of the semiconductor chip, the volume of the first insulating resin is increased, and the volume of the first insulating resin and the metal wiring is increased. Since the contact area also increases, the amount of stress relaxation that can be absorbed by the first insulating resin increases, and the occurrence of problems such as disconnection of the metal wiring can be prevented.
[0038]
Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. FIG. 7 is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention, which is performed by different steps.
[0039]
First, as shown in FIG. 7A, a passivation film 19 is formed on the surface of the semiconductor chip 12 on which the electrodes 13 are formed so as to open the electrode 13 portions.
[0040]
Next, as shown in FIG. 7B, a low-elastic first insulating resin 14 made of a photosensitive epoxy resin is formed on the surfaces of the electrodes 13 of the semiconductor chip 12 and the passivation film 19.
[0041]
Next, as shown in FIG. 7C, the first insulating resin 14 is patterned by drying, exposing, and developing, so that the end of the semiconductor chip 12 and the electrode 13 of the semiconductor chip 12 are opened. An opening 23 is formed in the first insulating resin 14. The film thickness of the first insulating resin 14 is about 5 [μm] to 50 [μm], preferably about 10 [μm] from the viewpoint of maintaining flatness during coating and exposing and developing. As the first insulating resin 14, photosensitive polyimide, BCB, PBO, or the like may be used in addition to the photosensitive epoxy resin. When the first insulating resin 14 is a photosensitive insulating resin, a weak alkali or organic developer is used as a material that does not dissolve the electrodes 13 of the semiconductor chip 12 during development.
[0042]
Next, as shown in FIG. 8A, a metal barrier 20 and a plating seed layer 21 are sequentially formed on the surface of the electrode 13, the passivation film 19, and the first insulating resin 14 of the semiconductor chip 12 by a sputtering method. Prior to the sputtering of the metal barrier 20, the surface of the first insulating resin 14 is finely roughened by plasma treatment, so that the adhesion strength between the first insulating resin 14 and the metal barrier 20 can be improved, The development residue of the first insulating resin 14 remaining on the surface of the electrode 13 of the semiconductor chip 12 can be removed, and the connection resistance between the electrode 13 of the semiconductor chip 12 and the metal barrier 20 can be reduced. In the present embodiment, the roughening is performed by the plasma processing method using the reaction gas, but it is sufficient that the first insulating resin 14 can be selectively etched with respect to the etching amount of the electrode 13 and the passivation film 19 of the semiconductor chip 12. Specifically, the plasma processing method of the present embodiment uses an RIE (Reactive Ion Etching) processing method and a mixed gas selected from any of oxygen, nitrogen, and CF ₄ .
[0043]
In this embodiment, a Ti—W alloy is used as the metal barrier 20, has a strong adhesion strength to the first insulating resin 14, the electrode 13 of the semiconductor chip 12, and the passivation film 19, and has a plating seed layer 21. Has a barrier property to an etchant. Further, as the plating seed layer 21, low resistivity Cu is used so that the plating seed layer 21 can be formed by the electrolytic plating method. The thickness of the Ti-W alloy constituting the metal barrier 20 is preferably about 0.1 [μm] or more from the viewpoint of a barrier property of blocking an etchant when the plating seed layer 21 is etched. Taking into account the stress generated during the etching and the ease of etching, it is preferably about 0.5 [μm] or less, but in this embodiment it is 0.2 [μm]. Further, the thickness of Cu forming the plating seed layer 21 is preferably about 0.3 [μm] or more from the viewpoint of electric resistance, and is 1.0 [μm] or less from the viewpoint of deposition stress and ease of etching. Preferably, in this embodiment, it is about 0.5 [μm].
[0044]
Next, as shown in FIG. 8B, a photosensitive resist material 24 is applied to the surface of the plating seed layer 21.
[0045]
Next, as shown in FIG. 9A, the photosensitive resist material 24 is dried, exposed, and developed to leave the resist material 24 in a region excluding a portion where a metal wiring is to be formed. Here, in order to set the electrolytic Cu plating thickness to be 5 [μm] to 15 [μm] as the metal wiring, the thickness of the resist material 24 is formed to be about 20 [μm], and the resist material 24 is subjected to plasma treatment with oxygen. The development residue is removed.
[0046]
Next, as shown in FIG. 9B, the metal wiring 15 is formed by electrolytic Cu plating on the exposed portion of the plating seed layer 21 other than the portion where the resist material 24 is formed, using a thick metal film as a putter plating. Form. The thickness of the metal wiring 15 is formed to a thickness of about 5 [μm] to 15 [μm], preferably about 10 [μm] from the viewpoint of electric resistance and mechanical strength.
[0047]
Next, as shown in FIG. 9C, the resist material is peeled and removed, and a residue of the resist material 24 is removed by plasma treatment with oxygen. Then, when the entire surface of the plating seed layer 21 and the metal wiring 15 is Cu-etched with a Cu etchant, the upper layer (Cu) of the plating seed layer 21 having a smaller thickness than the metal wiring 15 is removed in advance. At this time, for example, a mixed solution of hydrogen peroxide and sulfuric acid or sodium persulfate is used as a solution that does not dissolve the metal barrier 20 and can selectively etch the plating seed layer 21.
[0048]
Next, as shown in FIG. 10A, the metal wiring 20 having a desired pattern is formed by etching the entire surface of the metal barrier 20 using a TiW etching solution made of, for example, a hydrogen peroxide solution.
[0049]
Next, as shown in FIG. 10B, a photosensitive second insulating resin 25 is applied to the surfaces of the metal wiring 15 and the semiconductor chip 12, and is dried, exposed, and developed to be patterned. An opening 26 is formed in the insulating resin 25. The second insulating resin 25 is formed to have a thickness of about 5 [m] to 50 [m], preferably about 30 [m], from the viewpoint of maintaining flatness during coating and exposing and developing. The material of the second insulating resin 25 may be a polymer such as an ester-bonded polyimide or an acrylate-based epoxy, for example, as long as it has an insulating property.
[0050]
Thereafter, solder paste is printed and melted on the metal lands 16 to form ball electrodes 18 as external electrode terminals. Here, instead of printing and melting the solder paste, a ball electrode 18 may be formed by mounting and melting a solder ball.
[0051]
As described above, according to the method of manufacturing a semiconductor device of the present invention, the plating seed layer and the metal barrier can be selectively etched using the metal wiring as a mask, so that an etching mask is unnecessary and an etching margin is widened. Thus, a high-performance, small-sized semiconductor device at a lower cost can be provided.
[0052]
【The invention's effect】
The semiconductor device and the method for manufacturing the same according to the present invention have a structure in which a metal wiring layer having a width smaller than the width of an opening formed in a passivation film of an electrode portion of a semiconductor chip is provided and a contact hole is not used. The distance between the electrodes of the chip can be reduced, and a semiconductor device applicable to a small, multi-pin semiconductor chip can be provided.
[Brief description of the drawings]
FIG. 1 is a perspective view showing a semiconductor device according to an embodiment of the present invention; FIG. 2 is a perspective view showing a semiconductor device according to an embodiment of the present invention; FIG. FIG. 4 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. FIG. 5 is a perspective view showing a semiconductor device according to an embodiment of the present invention. FIG. 6 shows a semiconductor device according to an embodiment of the present invention. FIG. 7 is a cross-sectional view illustrating each step of a method of manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 8 is a cross-sectional view illustrating each step of a method of manufacturing a semiconductor device according to one embodiment of the present invention. 9 is a cross-sectional view illustrating each step of a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating each step of a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 12 is a perspective view showing a semiconductor device. FIG. 12 is a perspective view showing a conventional semiconductor device. Sectional view showing a cross-sectional view [FIG. 14] Conventional semiconductor device showing the conductor arrangement EXPLANATION OF REFERENCE NUMERALS
REFERENCE SIGNS LIST 1 semiconductor chip 2 electrode 3 passivation film 4 first insulating resin 5 contact hole 6 metal wiring 7 external electrode 8 ball electrode 9 second insulating resin 10 metal barrier 11 seed layer 12 semiconductor chip 13 electrode 14 first insulating resin 15 Metal wiring 16 metal land 17 second insulating resin 18 ball electrode 19 passivation film 20 metal barrier 21 plating seed layer 22 opening 23 opening 24 resist material 25 second insulating resin 26 opening

Claims (7)

A semiconductor chip on which an electrode is formed, an opening at the electrode, a first insulating resin formed on the surface of the semiconductor chip, one end connected to the electrode, and another end connected to the first insulating resin A metal wiring extending on the surface of the metal wiring and having a width smaller than the width of the electrode; an external electrode terminal formed on the surface of the metal wiring; And a second insulating resin formed on the surface of the metal wiring. 2. The semiconductor according to claim 1, wherein a passivation film is formed between a surface of the semiconductor chip and the first insulating resin, and an electrode of the semiconductor chip is formed in a portion where the passivation film is opened. apparatus. 2. The semiconductor device according to claim 1, wherein a plurality of electrodes are arranged on the surface of the semiconductor chip at predetermined intervals. 2. The semiconductor device according to claim 1, wherein an opening of the first insulating resin is larger than an opening of the passivation film, and the first insulating resin does not contact an electrode of the semiconductor chip. 2. The semiconductor device according to claim 1, wherein the first insulating resin is in contact with an electrode of the semiconductor chip. Forming a first insulating resin on the surface of the semiconductor chip on which the electrode is formed; removing a portion of the first insulating resin formed on the surface of the electrode; Forming a metal wiring having a width smaller than the width of the electrode on the surface and the surface of the electrode; forming a second insulating resin on the surface of the metal wiring; Selectively removing the metal wiring to expose a part of the metal wiring, and forming an external electrode terminal at an exposed portion of the metal wiring. Prior to the step of forming the first insulating resin, a step of forming a passivation film on a portion of the surface of the semiconductor chip other than the electrodes is provided. After the step of forming the metal wiring, a resist material is coated on the surface of the metal wiring. 7. The semiconductor device according to claim 6, further comprising a step of forming and a step of selectively removing the resist material, wherein a removed portion of the resist material is smaller than an opening of the passivation film. Production method.

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