JP3544903B2 - Integrated circuit design method and integrated circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to layout design in LSI pattern design, and more particularly, to automatic layout using a layout tool.
[0002]
[Prior art]
The pattern design that builds the target electric circuit within the determined chip size requires a layout tool that uses a computer as the main part, such as allocating necessary circuit cells, laying out power supply wiring, and laying out signal lines. Has been done using. More specifically, when inputting the position information of input / output pads, the netlist representing the circuit cells and the input / output wiring of the circuit cells, etc. into a layout tool whose design rules are registered in advance, the layout is automatically output and the result is output. It is configured to
[0003]
[Problems to be solved by the invention]
In the layout tool, there is a system in which design rules are registered so that only one power supply is recognized for one circuit cell. FIG. 7 shows a specific example of the circuit cell 1 that can be realized by a single power supply VDD1.
Although no problem arises when an LSI is constituted by such a set of circuit cells, recently, for the purpose of reducing power consumption, even within a single circuit cell, as shown in FIG. Circuit designs that operate at a low voltage VDD2 as much as possible are mainly used for parts that operate at a low voltage.
[0004]
In such a case, since two power supplies are required for one circuit cell, when automatic layout is performed using a layout tool that recognizes only a single power supply, one of the power supplies VDD1 and VDD2 is automatically laid out. However, the wiring with the remaining power supply cannot be automatically wired by the layout tool, and the layout is currently manually processed.
[0005]
The present invention provides an integrated circuit design method capable of automatically laying out an LSI including a circuit cell requiring a plurality of power supply systems using a layout tool that recognizes only one power supply for one circuit cell. The purpose is to:
[0006]
[Means for Solving the Problems]
Therefore, the integrated circuit design method of the present invention provides a method for simulating a power supply in a chip having a plurality of power supply systems, even when an arbitrary circuit cell wants to fix an input signal at a voltage other than the power supply voltage of the cell. And perform automatic placement and automatic wiring.
[0007]
Specifically, when a plurality of power supply systems exist in the same chip, a very small resistance is individually connected to each of the power supply wirings, and the ends of the power supply wirings are output as terminals to the inside of the chip. This terminal is recognized as a signal output terminal, not a power supply, by a layout tool, and even if there is a cell within the chip to be fixed to an arbitrary voltage other than the power supply voltage, automatic wiring is performed based on this terminal signal. It becomes possible.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
According to a first aspect of the present invention, there is provided an integrated circuit design method for automatically laying out an LSI including a circuit cell requiring a plurality of power supply systems by using a layout tool which recognizes only one power supply for one circuit cell. In doing so, one main power supply system of the plurality of power supply systems is recognized by the layout tool as a power supply and is wired in a circuit cell in an automatic layout, and the auxiliary power supply system excluding the main power supply system is connected via a wiring cell. The layout tool recognizes the connection point as a signal instead of a power supply, and wires the circuit cell in an automatic layout.
[0009]
According to a second aspect of the present invention, there is provided an integrated circuit designing method for automatically laying out an LSI including a circuit cell requiring a plurality of power supply systems by using a layout tool which recognizes only one power supply for one circuit cell. In doing so, the layout tool recognizes an I / O pad provided on the integrated circuit chip and wire-bonded to the outside and a wiring cell having one end connected to the I / O pad. One main power supply system among the power supply systems is recognized by the layout tool as a power supply and is wired to a circuit cell in an automatic layout, and the auxiliary power supply system excluding the main power supply system is configured such that the other end of the wiring cell is not a power supply. In this case, the layout tool recognizes the signal as a signal and wires the circuit cell with automatic layout.
[0010]
According to a third aspect of the present invention, there is provided an integrated circuit design method according to the first or second aspect, wherein one of the resistance elements is connected to a power supply wiring, and the other of the resistance elements is a connection terminal to the circuit cell. It is characterized by the following.
According to a fourth aspect of the present invention, there is provided an integrated circuit designing method according to the first or second aspect, wherein the gate terminal of the P-type MOS transistor is fixed to the reference potential, and the source terminal is electrically connected to the power supply wiring. And the drain terminal is a connection terminal to the circuit cell.
[0011]
According to a fifth aspect of the present invention, there is provided an integrated circuit designing method according to the first or second aspect, wherein the source terminal of the N-type MOS transistor is connected to the power supply line, the gate terminal is fixed to the power supply, and the drain is The terminal is a connection terminal to a circuit cell.
The integrated circuit according to claim 6 of the present invention is an integrated circuit including a circuit cell requiring a plurality of power supply systems, wherein one main power supply system of the plurality of power supply systems is directly connected to the circuit cell. The auxiliary power supply system, excluding the main power supply system, is wired to the circuit cells via wiring cells for simulating a power supply as a signal .
[0012]
The integrated circuit according to claim 7 of the present invention is characterized in that, in claim 6, in the wiring cell, one of the resistance elements is connected to a power supply wiring, and the other of the resistance elements is a connection terminal to the circuit cell. I do.
In an integrated circuit according to an eighth aspect of the present invention, in the sixth aspect, in the wiring cell, the gate terminal of the P-type MOS transistor is fixed at a reference potential, the source terminal is electrically connected to the power supply line, and the drain terminal is connected to the power supply line. It is characterized in that it is a connection terminal to a circuit cell.
[0013]
In an integrated circuit according to a ninth aspect of the present invention, in the sixth aspect, in the wiring cell, the source terminal of the N-type MOS transistor is connected to the power supply line, the gate terminal is fixed to the power supply, and the drain terminal is connected to the circuit cell. A connection terminal is provided.
An integrated circuit according to a tenth aspect of the present invention is the integrated circuit according to the sixth aspect, wherein the wiring cell is arranged in an I / O cell having an I / O pad provided on the integrated circuit chip and wire-bonded to the outside. I do.
[0014]
Hereinafter, embodiments of the present invention will be described with reference to FIGS.
(Embodiment 1)
FIG. 1 shows (Embodiment 1).
When automatically laying out an LSI 3 including a circuit cell 1 requiring a plurality of power supply systems of VDD1 and VDD2 using a layout tool (not shown) that recognizes only a single power supply for one circuit cell, One end of the wiring cell 4 is connected to the power supply VDD2 so that the layout tool can recognize VDD1 as a power supply and can regard the power supply VDD2 as a signal when the power supply VDD2 is viewed from the circuit cell 1 side. A terminal name is given to one end, and when creating a netlist, the connection point is a signal at the point 5 where the power supply VDD2 is required in the circuit cell 1. Register your first name.
[0015]
Note that, specifically, the wiring cell 4 as a component can be made of polysilicon in a semiconductor manufacturing process. It is desirable that the resistance value is low, and ideally the resistance value is 0 ohm.
In this way, by creating a netlist and executing the netlist by a layout tool, even a circuit cell having two power supplies, VDD1 and VDD2, is provided by a layout tool that recognizes only a single power supply for one circuit cell. Power supply system can be automatically laid out and wired.
[0016]
(Embodiment 2)
FIG. 2 shows (Embodiment 2).
Although the wiring cell 4 of the first embodiment is made of polysilicon, in the second embodiment, the wiring cell 4 is composed of a P-type MOS transistor 6 that can be made in a semiconductor manufacturing process.
[0017]
In the netlist, the gate terminal of the P-type MOS transistor 6 is fixed to the reference potential GND, the source terminal is connected to the power supply VDD2, and the drain terminal is registered as a connection terminal to the circuit cell 1.
As a result, when the power supply VDD2 is viewed from the circuit cell 1 side, the resistance value between the source terminal and the drain terminal is interposed, and the layout tool recognizes VDD2 as a signal in a pseudo manner. Automatic layout wiring can be performed for all power supply systems even if the circuit cell has the same.
[0018]
(Embodiment 3)
3 and 4 show (Embodiment 3).
When the automatic layout wiring according to the first embodiment is performed, two types of special I / O pads shown in FIGS. 3A and 3B are provided on the integrated circuit chip and wire-bonded to the outside. Workability is improved by registering the I / O cells 7a and 7b as parts in advance.
[0019]
The I / O cell 7a in FIG. 3A has an I / O pad 8a, a wiring cell 4, a first power supply line 9a, and a second power supply line 9b. One end of 4 is connected to the second power supply line 9b.
The I / O cell 7b in FIG. 3B has an I / O pad 8b, a wiring cell 4, a first power supply line 10a, and a second power supply line 10b. Are connected to the power supply line 10a.
[0020]
By using these I / O cells 7a and 7b, it is assumed that VDD1 is externally supplied to the I / O pad 8b via the bonding wire, and VDD2 is externally supplied to the I / O pad 8a via the bonding wire. Further, the portion of the circuit cell 1 requiring VDD1 is connected to the first power supply line 10a of the I / O cell 7b as shown in FIG. 4, and the portion 5 of the circuit cell 1 requiring VDD2 is connected to the I / O cell 7b. A netlist is created so as to be connected to the other end of the wiring cell 4 of the O cell 7b, and the layout tool recognizes it.
[0021]
(Embodiment 4)
FIGS. 5A and 5B show (Embodiment 4).
The wiring cell in each of the above embodiments is a polysilicon resistor or a P-type MOS transistor 6, but these may be formed of an N-type MOS transistor 11 as shown in FIG.
[0022]
In the N-type MOS transistor 11, a source terminal is connected to VDD1, a gate terminal is fixed to a specific power supply VDD3, and a drain terminal is a connection terminal to the circuit cell 1.
VDD3 in this case is laid out as shown in FIG. When the wiring cell 4 is the N-type MOS transistor 11, it is preferable that the gate terminal is connected to the source terminal in the cell. If VDD3 is used, the voltage at the gate terminal and the voltage at the source terminal are the same as those of the transistor 1, so that the N-type MOS transistor 11 for this wiring cell has a gate and a source short-circuited to one wiring cell. I do.
[0023]
The circuit cell in each of the above embodiments is, for example, a bias circuit or a current source circuit. Specifically, when VDD2 is 1 volt or less with respect to 3 volts of VDD1 in the circuit layout shown in FIG. 6, the circuit cell constituted by the transistor 1 becomes a bias circuit and changes the resistance value of the resistor 21. Thus, the current value can be changed. The circuit 20 is an operational amplifier, a comparator, or the like. It goes without saying that the lower N-type MOS transistor in the circuit 20 is the same as the transistor 1 described above.
[0024]
【The invention's effect】
As described above, according to the integrated circuit design method of the present invention, even in the case of an LSI having a plurality of power supply systems, automatic placement and wiring of a multi-power supply LSI can be performed only by placing a wiring cell, and the number of steps can be significantly reduced. It can be planned.
[Brief description of the drawings]
1 is a layout diagram of an LSI according to a first embodiment of the present invention; FIG. 2 is a layout diagram of a second embodiment of the present invention; FIG. 3 is a layout diagram of an I / O cell according to a third embodiment of the present invention; FIG. 4 is a layout diagram when the I / O cell of the embodiment is used. FIG. 5 is a layout diagram of the embodiment 4 of the present invention. FIG. 6 is an explanatory diagram of a circuit cell. FIG. Layout diagram of power supply circuit cell [FIG. 8] Layout diagram of circuit cell requiring a plurality of power supplies [Description of reference numerals]
VDD1, VDD2 Power supply GND Reference potential 1 Circuit cell 3 LSI
4 Wiring cell 5 Location requiring power supply VDD2 6 P-type MOS transistors 7a, 7b I / O cell 8a I / O pad 9a First power supply line 9b Second power supply line 8b I / O pad 10a First power supply Line 10b Second power supply line 11 N-type MOS transistor

Claims (10)

When automatically laying out an LSI including a circuit cell requiring a plurality of power supply systems using a layout tool that recognizes only a single power supply for one circuit cell,
One main power supply system of the plurality of power supply systems is made to be recognized by the layout tool as a power supply and is wired in a circuit cell in an automatic layout,
An integrated circuit design method in which each of the auxiliary power supply systems except the main power supply system causes the layout tool to recognize a connection point via a wiring cell as a signal instead of a power supply as a signal and to wire the circuit cell with an automatic layout. When automatically laying out an LSI including a circuit cell requiring a plurality of power supply systems using a layout tool that recognizes only a single power supply for one circuit cell,
Causing the layout tool to recognize an I / O cell having an I / O pad provided on the integrated circuit chip and wire-bonded to the outside and a wiring cell having one end connected to the I / O pad;
One main power supply system of the plurality of power supply systems is made to be recognized by the layout tool as a power supply and is wired in a circuit cell in an automatic layout,
An integrated circuit design method in which an auxiliary power supply system other than the main power supply system causes the layout tool to recognize the other end of the wiring cell as a signal instead of a power supply, and to wire the circuit cell in an automatic layout. 3. The integrated circuit designing method according to claim 1, wherein the wiring cell has one of the resistance elements connected to the power supply wiring, and the other of the resistance elements serving as a connection terminal to the circuit cell. 3. The wiring cell according to claim 1, wherein a gate terminal of the P-type MOS transistor is fixed at a reference potential, a source terminal is electrically connected to a power supply wiring, and a drain terminal is a connection terminal to the circuit cell. Integrated circuit design method. 3. The integrated circuit designing method according to claim 1, wherein in the wiring cell, the source terminal of the N-type MOS transistor is connected to the power supply wiring, the gate terminal is fixed to the power supply, and the drain terminal is a connection terminal to the circuit cell. . An integrated circuit including a circuit cell requiring a plurality of power supply systems,
One main power supply system of the plurality of power supply systems is directly wired to a circuit cell, and the auxiliary power supply system other than the main power supply system is connected via a wiring cell for supposing a power supply as a pseudo signal. An integrated circuit wired to a circuit cell. 7. The integrated circuit according to claim 6, wherein in the wiring cell, one of the resistance elements is connected to a power supply wiring, and the other of the resistance elements is a connection terminal to a circuit cell. 7. The integrated circuit according to claim 6, wherein in the wiring cell, a gate terminal of the P-type MOS transistor is fixed at a reference potential, a source terminal is electrically connected to a power supply wiring, and a drain terminal is a connection terminal to the circuit cell. 7. The integrated circuit according to claim 6, wherein in the wiring cell, the source terminal of the N-type MOS transistor is connected to the power supply wiring, the gate terminal is fixed to the power supply, and the drain terminal is a connection terminal to the circuit cell. 7. The integrated circuit according to claim 6, wherein a wiring cell is arranged in an I / O cell having an I / O pad provided on the integrated circuit chip and wire-bonded to the outside.

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