JP3541566B2 - Serial data communication method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a serial data communication system in which data is transmitted by a time-division serial signal.
[0002]
[Problems to be solved by the invention]
In serial data communication, for example, when a variable pulse length method (PWM method) in which a data value is converted into a pulse length of a signal and transmitted is adopted, the type of data that can be transmitted by one transmission is one of the transmission data. The frame length is limited by the sampling rate of the receiving side, and, for example, in the case of start-stop synchronous communication of 8-bit data, data that can be transmitted by one transmission is limited to 256 types. Will be.
[0003]
In this case, in the variable pulse length method, it is conceivable to increase the length of one frame in order to increase the types of data that can be transmitted by one transmission, but this causes a new problem that a communication delay increases. Will do. It is also conceivable to increase the sampling rate on the receiving side to increase the types of data. However, on the receiving side, there is usually a basic interrupt processing routine in the program for controlling the receiving operation, so that there are naturally many restrictions on the reduction of the sampling rate as described above. However, it is not practical.
[0004]
When increasing the number of data types that can be transmitted in one transmission in the start-stop synchronous communication of 8-bit data, the number of data bits may be increased, but this complicates the data processing procedure on the receiving side. Is unavoidable and not practical.
[0005]
The present invention has been made in view of the above circumstances, and an object of the present invention is to determine the type of data that can be transmitted by one transmission by affecting the frame length of transmission data, or by sampling at the reception side. It is an object of the present invention to provide a serial data communication system which can be increased without changing a rate or complicating a procedure for data processing.
[0006]
[Means for Solving the Problems]
According to the first aspect of the present invention, the first voltage signal, the second voltage signal, and the third voltage signal, which are set to at least three levels, are transmitted from the transmitting device to the signal line through the output interface circuit. Can be selectively output. When the voltage signal is output to the signal line in this manner, the input interface circuit on the receiving device side discriminates the level of the voltage signal and converts it into a binary signal. Specifically, when the state in which the first voltage signal is output and the state in which the second voltage signal is output are repeated for the signal line, the first signal discriminating means outputs the signal in the repetition mode. When the state in which the first voltage signal is output and the state in which the third voltage signal is output are repeated with respect to the signal line, the second signal discrimination is performed. The means outputs a binary signal according to the repetition mode.
[0007]
That is, a state where the first voltage signal and the second voltage signal are alternately transmitted from the transmitting device to the signal line and a state where the first voltage signal and the third voltage signal are alternately transmitted are described. The difference can be recognized on the receiving device side, and as a result, the types of data that can be transmitted by one transmission increase. In this case, there is no need to increase the length of one frame or the number of bits of the data to be transmitted or to increase the sampling rate on the receiving side, so that there is no possibility of causing the problems as in the conventional configuration.
[0008]
In this case, a first switching element and a second switching element are provided in the output interface circuit, and when both of the switching elements are off, a first switching element for dividing the output voltage of the power supply terminal is provided . And the divided voltage of the voltage dividing circuit having the second resistor can be always applied to the signal line as the second voltage.
[0009]
Further, in a state where the first switching element in the output interface circuit is turned on from the state where the second voltage is applied to the signal line , the third resistor is connected to the first resistor in the voltage dividing circuit. is connected to the resistor in parallel, the first voltage signal and the second voltage signal and the levels are different is to be applied to the signal lines. Further, when the second switching element in the output interface circuit is turned on, both ends of the second resistor in the voltage dividing circuit are short-circuited, and the first voltage signal and the second voltage are applied to the signal line. A third voltage signal having a different level from the signal is applied.

[0010]
Therefore, on the transmission device side, the control required for data transmission as described above, that is, by selectively turning on and off the first switching element and the second switching element, the first voltage is applied to the signal line. Control can be easily performed to switch between a state in which the signal and the second voltage signal are transmitted alternately and a state in which the first and third voltage signals are transmitted alternately.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows an electrical configuration example of a data transmission system employing a serial data communication system according to the present invention. In the system shown in FIG. 1, digital data is transmitted via the signal line 3 from the ECU 100 constituting the transmitting device to the ECU 200 constituting the receiving device.
[0012]
The transmission-side ECU 100 is provided with an MPU 101 for processing an operation signal input from an operation unit (not shown), performing transmission control via the signal line 3, and the like. The MPU 201 for controlling reception via the signal line 3 and controlling a load (not shown) is provided in the ECU 200 on the reception side. In this case, the MPUs 101 and 201 are connected to each other via a ground potential line 4 for obtaining a reference potential level.
[0013]
The transmission-side ECU 100 is provided with an output interface circuit 102 for sending digital data to the signal line 3. The output interface circuit 102 includes a pnp transistor 103 (corresponding to a first switching element in the present invention) and an npn transistor 104 (corresponding to a second switching element in the present invention). The base of 103 is connected to the output port Q1 of the MPU 101 via a resistor 105, and the base of the transistor 104 is connected to the output port Q2 of the MPU 101 via a resistor 106. Note that base bias resistors 107 and 108 are connected between the base and emitter of the transistors 103 and 104, respectively.
[0014]
In the output interface circuit 102, a voltage dividing resistor 109 (corresponding to a third resistor in the present invention) is provided between the power supply terminal + Vcc and the ground potential line 4 between the emitter and the collector of the transistor 103. ) And 110 (corresponding to the second resistor in the present invention) are connected in series, and a common connection point of the voltage dividing resistors 109 and 110 is connected to the signal line 3. Further, the collector and the emitter of the transistor 104 are connected in parallel with the voltage dividing resistor 110 on the ground potential line 4 side.
[0015]
On the other hand, the reception-side ECU 200 is provided with an input interface circuit 202 for receiving the digital data sent to the signal line 3. The input interface circuit 202 includes comparators 203 and 204 (corresponding to first signal discriminating means and second signal discriminating means, respectively, according to the present invention) to which appropriate hysteresis is provided by feedback resistors 203a and 204a, respectively. Output terminals of the comparators 203 and 204 are connected to input ports P1 and P2 of the MPU 201, respectively.
[0016]
Further, the input interface circuit 202 is provided with a reference voltage generation circuit 205 for applying different levels of reference voltages to the non-inverting input terminals (+) of the comparators 203 and 204. The reference voltage generation circuit 205 has a configuration in which resistors 205a, 205b, and 205c are connected in series between a power supply terminal + Vcc and a ground power supply line. In the present embodiment, for example, a reference voltage Vref1 of 3.75 V is applied to the non-inverting input terminal (+) of the comparator 203, and a reference voltage of 1.25 V is applied to the non-inverting input terminal (+) of the comparator 204. Vref2 is set to be given.
[0017]
Further, in the input interface circuit 202, a pull-up resistor 206 (corresponding to the first resistor in the present invention) is connected between the power supply terminal + Vcc and the signal line 3, and the signal line 3 is connected to the input line. It is connected to each inverting input terminal (-) of the comparators 203 and 204 via the resistor 207. The pull-up resistor 206 and the voltage dividing resistor 110 constitute a voltage dividing circuit 500 according to the present invention.
[0018]
As a result of the provision of the output interface circuit 102 having the above configuration, and the provision of the pull-up resistor 206 constituting the voltage dividing circuit 500 by the voltage dividing resistor 110 in the output interface circuit 102 on the input interface circuit 202 side. The output interface circuit 102 can selectively output three-stage voltage signals as shown in the following (1) to (3) to the signal line 3 according to the on / off state of the internal transistors 103 and 104. is there. However, the collector-emitter saturation voltages of the transistors 103 and 104 are ignored.
[0019]
{Circle around (1)} When the transistor 104 is turned on, the transistor 104 short-circuits both ends of the voltage-dividing resistor 110 in the voltage-dividing circuit 500. Therefore, the third voltage signal δv3 at the ground potential level is supplied to the signal line 3. The signal is output (irrespective of the on / off state of the transistor 103).
[0020]
{Circle around (2)} In a state where the transistor 104 is turned off and the transistor 103 is turned on, the transistor 103 connects the voltage dividing resistor 109 in parallel with the voltage dividing resistor 206 in the voltage dividing circuit 500, so that the signal line 3 On the other hand, a first voltage signal δv1 of a comparatively high level divided by the parallel circuit of the resistors 109 and 206 and the resistor 110 is output. In the present embodiment, the level of the first voltage signal δv1 is set to be 5V.
[0021]
{Circle around (3)} In a state where both the transistors 103 and 104 are turned off, a second voltage signal δv2 of a comparatively low level divided by the pull-up resistor 206 and the voltage dividing resistor 110 is output to the signal line 3. Is done. In the present embodiment, the level of the second voltage signal δv2 is set to be 2.5V.
[0022]
In this case, as apparent from the above description, the comparators 203 and 204 in the input interface circuit 202 connect the voltage signal of the signal line 3 supplied to the inverting input terminal (−) and the non-inverting input terminal (+) to the non-inverting input terminal (+), respectively. Are compared with reference voltages Vref1 (= 3.75 V) and Vref2 (= 1.25 V).
[0023]
Therefore, in a state where the third voltage signal δv3 (ground potential level) is output to the signal line 3 (state (1)), both the comparators 203 and 204 output an “H” level signal. In a state where the first voltage signal δv1 (5 V) is output to the signal line 3 (state of (2)), both the comparators 203 and 204 output an “L” level signal. Further, in a state where the second voltage signal δv2 (2.5 V) is output to the signal line 3 (state of (3)), the “H” level signal is output from the comparator 203 and the “L” level is output from the comparator 204. "Level signal is output.
[0024]
Thus, the comparator 203 can generate a binary signal having a different logic level between the state where the first voltage signal δv1 is input through the signal line 3 and the state where the second voltage signal δv2 is input. ing. The comparator 204 is configured to generate a binary signal having a different logic level between a state where the first voltage signal δv1 is input through the signal line 3 and a state where the third voltage signal δv3 is input. I have.
[0025]
The outputs of the comparators 203 and 204 as described above are input to the input ports P1 and P2 of the MPU 201, respectively. In the MPU 201, based on the input signals as described above, the signal lines 3 The level of the transmitted voltage signal is determined in three stages, and based on the determination result, the above-described binary signal (where the first voltage signal δv1 is “mark” and the second voltage signal δv2 is “space” And the first voltage signal δv1 is a “mark”, and the third voltage signal δv3 is a “space”.
[0026]
Here, an example will be described in which data communication is performed between the ECUs 100 and 200 by a variable pulse length method (PWM method) in which a data value is converted into a signal pulse length and transmitted.
[0027]
In other words, for example, when transmitting a pulse length variable signal of 40 ms per frame, as shown in FIG. 2A, the pulse width ΔT falling from the mark state (for example, any of 10 ms, 20 ms, or 30 ms) is set. Each pulse signal having a data value is transmitted through the signal line 3 as data A, B, and C, each of which is a binary signal.
[0028]
In this case, to increase the number of types of data that can be transmitted, for example, to double, the entire frame length may be doubled, but this is not practical because the communication delay increases. Further, it is also possible to cope with this by reducing the minimum pulse width of the transmission data to 1/2 by increasing the sampling rate of the input signal in the receiving ECU 200. However, since the MPU 201 of the receiving ECU 200 usually has many basic interrupt processing routines in its control program, the reduction of the sampling rate as described above is naturally limited. There is a problem that it is not practical as a result.
[0029]
On the other hand, in the present embodiment, as shown in FIGS. 2B and 2C, the ECU 100 identifies each of the transistors 103 and 104 in the output interface circuit 102 according to the selective on / off state of the transistor. Two types of data A 'and A ", B' and B", C 'and C "each composed of possible different binary signals can be transmitted, and the logic level of the data transmitted in the ECU 200 is inputted. The identification can be performed through the interface circuit 202.
[0030]
However, in FIGS. 2B and 2C, ON and OFF states of the transistors 103 and 104 are indicated by ON and OFF, respectively, and the level of the binary signal given to the input terminals P1 and P2 of the MPU 201 is “H”. It is represented by “1” corresponding to the level signal and “0” corresponding to the “L” level signal.
[0031]
Therefore, according to the present embodiment, it is possible to increase the types of data that can be transmitted without increasing the frame length of the transmission data or increasing the sampling rate of the input signal in the receiving ECU 200. It will be very useful.
[0032]
Further, when data communication is performed between the ECUs 100 and 200 by, for example, the start-stop synchronization method, in the conventional configuration, only 256 types of data can be transmitted when the transmission data is 8 bits. Can be transmitted in a state switched to two stages, and consequently 512 types of data can be transmitted, and the receiving side only needs to perform 8-bit processing.
[0033]
Note that the present invention is not limited to the above-described embodiment, and the following modifications or extensions are possible.
On the transmission side, the level of the voltage signal to be output to the signal line is switched in three stages (0 V, 2.5 V, 5 V), but may be switched in more stages. However, in this case, it is necessary to add signal discriminating means for discriminating the levels of the voltage signals to the receiving side. The first and second signal discriminating means may be configured using an AD converter IC.
[0034]
In the example of FIG. 1, the output interface circuit 102 is configured by combining the transistors 103 and 104 and the resistors 105 to 110. However, the output interface circuit having the same function is configured by combining the resistor and another circuit element such as an FET. You can also. The pull-up resistor 206 included in the voltage dividing circuit 500 may be provided on the output interface circuit 102 side.
[Brief description of the drawings]
FIG. 1 is an electrical configuration diagram showing one embodiment of the present invention. FIG. 2 is a waveform diagram for explaining an operation.
In the figure, 3 is a signal line, 100 is an ECU (transmitting device), 101 is an MPU, 102 is an output interface circuit, 103 is a transistor (first switching element), 104 is a transistor (second switching element), and 109 is Voltage dividing resistor (third resistor), 110 is voltage dividing resistor (second resistor), 200 is ECU (receiving device), 201 is MPU, 202 is input interface circuit, 203 is comparator (first signal discriminating means) , 204 are comparators (second signal discriminating means), 205 is a reference voltage generating circuit, 206 is a pull-up resistor (first resistor), and 500 is a voltage dividing circuit.

Claims (1)

In a serial data communication system for transmitting a serial signal from a transmitting device to a receiving device via a signal line,
Provided in the transmitting apparatus side, a first voltage signal set at a level of at least three stages to the signal line, and a second voltage signal and the third selectively capable of outputting an output interface circuit voltage signals ,
A first signal that is provided on the receiving device side and that generates a binary signal having a different logic level between a state where the first voltage signal is input and a state where the second voltage signal is input via the signal line; Signal discriminating means;
A second signal which is provided on the receiving device side and generates a binary signal having a different logic level between a state where the first voltage signal is input and a state where the third voltage signal is input via the signal line; Signal discriminating means ;
A voltage divider having a first resistor and a second resistor for dividing the output voltage of the power supply terminal, the divider being provided so that the divided voltage can be applied to the signal line;
A first switching element that applies the first voltage signal to the signal line by connecting a third resistor in parallel with a first resistor in the voltage dividing circuit in an on state; A second switching element that applies the third voltage signal to the signal line by short-circuiting both ends of a second resistor in the voltage dividing circuit in an on state, and the first and second switching elements are provided. A serial data communication system , wherein a divided voltage by the voltage dividing circuit is applied to the signal line as the second voltage signal in a state where both switching elements are off .

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