JPH118545A - Drive circuit and drive method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To deal with the fluctuations of bias voltage, when performing communication conforming with the Institute of Electrical and Electronic Engineers(IEEE) 1394. SOLUTION: A capacitor Cref is charged by a bias voltage in the high impedance state of cable, through which a differential signal is transmitted. Then, at the time of differential signal output, at a comparator 45, that differential signal is compared with the bias voltage corresponding to the charge of capacitor Cref. In an up-down counter 32, corresponding to the compared result, the on/off of plural parallel-connected transistors p11-p14, p21-p24, p31-p34 and p41-p44 is controlled for turning on/off the current of the differential signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a drive circuit and a drive method, and more particularly to, for example, an IEEE (Inst.
itute of Electrical and Electronic Engineers) 13
The present invention relates to a drive circuit and a drive method suitable for driving a cable for a physical layer when performing communication conforming to a standard such as 94.

[0002]

2. Description of the Related Art For example, communication conforming to the IEEE 1394 standard uses a twisted pair cab.
This is done by biasing the cable and exchanging differential signals between the devices connected in le).

FIG. 5 shows a conventional communication system (a system is a system in which a plurality of devices are logically aggregated and performs such a communication. Is not limited).

In this communication system, device D
EVICE 1 and DEVICE 2 are connected by a cable (twisted pair cable) 1.

In the device DEVICE1, a cable bias (Cable Bias) circuit 11 biases a pair wire 1A constituting the cable 1. That is, pair wire 1
One end of the device A connected to the device DEVICE1 is terminated by a series connection of two resistors RT as terminating resistors, and the cable bias circuit 1
Numeral 1 biases a connection point between two resistors RT as a terminating resistor to a predetermined bias voltage.

A drive circuit 112 is connected to one end of the pair wire 1A, which is biased by the cable bias circuit 11, on the device DEVICE1 side. The other end of the pair wire 1A is connected to a drive circuit 125 of the device DEVICE2, so that the drive circuit 112 of the device DEVICE1,
The drive circuit 125 of the device DEVICE2 operates by sharing the bias voltage from the cable bias circuit 11.

The drive circuit 112 generates a differential signal (a signal of 2) corresponding to information to be transmitted, and one of the signals is
(The other signal is inverted), and the differential signal is transmitted to the device DEVICE2 via the pair line 1A. One end of the pair line 1A on the device DEVICE2 side is connected to a bias circuit 125, a terminating resistor in which two resistors RT are connected in series and a receiver circuit 26, and from the drive circuit 112 via the pair line 1A. The supplied differential signal is received by the receiving circuit 26.

In the device DEVICE2,
The other end of a resistor R whose one end is grounded is connected to a connection point between two resistors RT as a terminating resistor of the pair line 1A.

The drive circuit 125 of the device DEVICE2 also outputs a differential signal corresponding to information to be transmitted, and the differential signal is transmitted to the device DEVICE1 via the pair line 1A. You. A receiving circuit 13 is also connected to one end of the pair line 1A on the device DEVICE1 side, and a differential signal supplied from the drive circuit 112 via the pair line 1A is received by the receiving circuit 13.

By the way, the device DEVI of the pair line 1A
At one end on the CE1 side, two resistors RT as a terminating resistor are provided.
In addition, a resistor in which two resistors RC as resistors for detecting a common mode voltage are connected in series is connected in parallel with the two resistors RT. The connection point between the two resistors RT is connected to a common mode signal detection circuit (Common Mode
pareator) 14 is connected to the non-inverting input terminal (+) of the comparator, and the inverting input terminal (−)
It is connected to a connection point between two resistors RT as a terminating resistor.

In IEEE1394, the average value of differential signals (the average value of the potentials of the two lead wires of a pair wire 1A (1B) composed of two lead wires when a differential signal is output (hereinafter referred to as the average value) , A common mode voltage) is set to a predetermined voltage, for example, a speed signal (IEEE1) as information on a data transmission rate.
394-1995)
The common mode signal detection circuit 1 is capable of transmitting a so-called common mode signal such as
At 3, the common mode signal is detected. For example,
In the receiving circuit 13, the common mode voltage detecting circuit 13
The differential signal from the device DEVICE2 is received as a data transmitted at a transmission rate corresponding to, for example, a speed signal as the common mode signal detected at the step S1.

The drive circuit 115 and the receive circuit 16 of the device DEVICE1 connected to the pair line 1B correspond to the drive circuit 125 and the receive circuit 26 of the device DEVICE2 described above. The part of the cable bias circuit 21, the drive circuit 122, the receive circuit 23, and the common mode signal detection circuit 24 of the device DEVICE2 connected to the line 1B is the same as the device DEVIC2 described above.
E1 cable bias circuit 11, drive circuit 11
2, since it corresponds to the receiving circuit 13 and the common mode signal detecting circuit 14, the description thereof is omitted.

The device DEVICE1 has two drive circuits 112 and 115, and the device DEVICE2 has a drive circuit 122.
And 125 are provided, for example, in order to transmit information about the clock in one drive circuit and transmit normal data in the other drive circuit. For the same reason, each device is also provided with two receive circuits.

[0014]

In the above communication system, as described above, two devices DEVIC are used.
Since the bias voltage is shared between E1 and DEVICE2, if there is a variation in the ground level between them, the bias voltage will also fluctuate.

That is, for example, the difference in ground level between the devices DEVICE1 and DEVICE2 is-
When the voltage is allowed in the range of 0.5 V to +0.5 V, for example, the bias voltage supplied by the cable bias circuit 11 in the device DEVICE1 is 1.8.
Assuming 5V, device DEVIC via pair line 1A
The bias voltage supplied to E2 ranges from 1.35V to 2.35V.
It changes in the range of 35V. In consideration of the variation in the characteristics of the cable bias circuit 11 itself, the bias voltage supplied to the device DEVICE2 further varies.

As described above, when the bias voltage fluctuates, the output current flowing through the drive circuit fluctuates, and the voltages of the two signals constituting the differential signal become unbalanced. That is, for example, in the above case, the device DEVI
The differential signal of the drive circuit 125 in CE2 becomes unbalanced. If the differential signals become unbalanced, the common mode voltage (the voltage of the common mode signal) changes, making it difficult to accurately transmit and receive the signals.

Therefore, for example, US Pat.
0 discloses a drive circuit for performing feedback for correcting an output current according to a received bias voltage, as shown in FIG.

In this drive circuit, a transistor (N-channel MOS (Metal Oxide Semiconductor))
FETs (Field Effect Transistors) 201 and 202 constitute a current mirror circuit for passing a current corresponding to one of the differential signals, and a transistor (N-channel MOS FET) 2
In 01 and 203, a current mirror circuit for flowing a current corresponding to the other signal constituting the differential signal is formed, and a predetermined output current is caused to flow by these current mirror circuits.

Then, two resistors RT as a terminating resistor
, That is, the bias voltage supplied from the communication partner is monitored by the operational amplifier 204, and the operational amplifier 205 controls the drain voltages of the transistors 202 and 203 constituting the current mirror circuit to be equal to the bias voltage. (P channel MO
By controlling the gate voltages of the SFETs 206 to 209, the imbalance of the differential signal does not occur even if the bias voltage fluctuates. The transistors 206 and 207 adjust (compensate) the current of the differential signal.
The transistors 208 and 209 are for adjusting the current of the common mode signal.

In this drive circuit, a current mirror circuit is provided to allow a predetermined current to flow as a differential signal, and the transistors 202 and 203 constituting this current mirror circuit need to operate in a saturation region. is there. Therefore, for example, when the drain voltage of the transistors 206 and 207 increases due to a change in the bias voltage, the voltage between the drain and the source of the transistors 206 to 209 decreases, so that the transistors 202 and 203 operate in the saturation region. for,
It is necessary to reduce the voltage between the gate and the source of the transistors 206 to 209. And the transistor 20
It is necessary to use channels 6 to 209 having a large channel width so that a predetermined current can flow even under such conditions.

Furthermore, since the characteristics of the transistors 202 and 203 constituting the current mirror circuit usually have variations, the channel length of the transistors 206 and 207 needs to be increased in order to absorb the variations.

Therefore, it is necessary to use large transistors as the transistors 206 to 209.
This hinders a reduction in the power supply voltage and a reduction in the circuit area of the circuit, which is expected to proceed in the future.

The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a small-sized drive circuit capable of coping with fluctuations in bias voltage.

[0024]

According to a first aspect of the present invention, there is provided a drive circuit comprising: a plurality of switching means connected in parallel for turning on / off a current; a comparing means for comparing a differential signal with a bias voltage; Control means for controlling ON / OFF of the switching means in accordance with the comparison result of the means.

According to a fifth aspect of the present invention, in the case where the drive circuit includes a plurality of switching means connected in parallel for turning on / off the current, the differential signal is compared with the bias voltage, and the comparison result is obtained. Correspondingly, the on / off of the switching means is controlled.

In the drive circuit according to the first aspect, the plurality of switching means are connected in parallel,
The current is turned on / off. The comparing means compares the differential signal with the bias voltage, and the control means
On / off of the switching means is controlled according to the comparison result of the comparing means.

According to a fifth aspect of the present invention, in the case where the drive circuit includes a plurality of switching means connected in parallel for turning on / off a current, the differential signal is compared with a bias voltage, and the comparison result is provided. In response to the above, on / off of the switching means is controlled.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below, but before that, the correspondence between each means of the invention described in the claims and the following embodiments will be clarified. For this reason, the features of the present invention are described as follows by adding the corresponding embodiment (however, an example) in parentheses after each means.

That is, the drive circuit according to claim 1 is
A drive circuit for passing a current corresponding to a differential signal to be transmitted to a communication partner connected via a cable biased to a predetermined bias voltage, wherein a plurality of switching circuits connected in parallel for turning on / off the current Means (for example,
The transistor (P-channel MOSFE) shown in FIGS.
T) Comparison means for comparing a differential signal and a bias voltage with p11 to p14, p21 to p24, p31 to p34, and p41 to p44 (for example, FIG. 2)
And a control means (eg, an up / down counter shown in FIGS. 2 and 4) for controlling on / off of the switching means in accordance with the comparison result of the comparing means. 32)).

The drive circuit according to a third aspect of the present invention provides a storage means for storing a bias voltage when the cable is in a high impedance state (for example, a capacitor Cre shown in FIG. 2).
f), wherein the comparing means compares the differential signal with the bias voltage stored in the storage means.

According to a fifth aspect of the present invention, there is provided a drive method in a drive circuit for passing a current corresponding to a differential signal transmitted to a communication partner connected via a cable biased to a predetermined bias voltage. The drive circuit includes a plurality of parallel-connected switching means (for example, transistors p11 to p14, p21 to p24, p31 to p34, and p41 to p44 shown in FIGS. 2 and 4) for turning on / off the current. In this case, the differential signal is compared with a bias voltage, and ON / OFF of the switching means is controlled in accordance with the comparison result.

Of course, this description does not mean that each means is limited to those described above.

FIG. 1 shows a configuration example of an embodiment of a communication system to which the present invention is applied. In FIG. 5, FIG.
The same reference numerals are given to the portions corresponding to the case in. That is, this communication system is basically the same as the communication system of FIG. 6 except that drive circuits 12, 15, 22, or 25 are provided instead of drive circuits 112, 115, 122, or 125, respectively. It is configured similarly.

Here, the drive circuits 12, 15, 22,
And 25 have the same configuration, for example, and only the drive circuit 12 will be described below.

FIG. 2 shows a configuration example of the drive circuit 12 of FIG. The drive circuit 12 is, for example, a CMOS and is configured as a one-chip IC. Further, in FIG. 2 (the same applies to FIG. 4 described later), among the transistors (FETs) illustrated in FIG.
The channel MOS FETs and those not attached are N-channel MOS FETs.

The up / down counter 32 is, for example, 4
A bit counter increments or decrements the count value at the timing of an input signal to the clock terminal (CK). In addition,
Whether to increment or decrement the count value is determined by an input signal to its up / down terminal (U / D).

The count value of the up / down counter 32 is determined by the NAND gates 34 _{1 to} 34 ₄ and 35 _{1 to} 3
5 ₄ is adapted to be supplied to. That is, the LSB of the 4-bit count value of the up / down counter 32
(0th bit), the first bit, second bit, MSB (third bit) is adapted to be supplied to the respective NAND gates 34 ₁ through 34 ₄ and 35 ₁ to 35 ₄ one input terminal of each I have.

[0038] NAND gate 34 ₁ to 34 ₄ of the other input terminal, to both, when communicating, for example, be in the H level, other signals are at the L level when the TpE
n is supplied. Here, the signal Tp
When En is at the H level, data (hereinafter, appropriately referred to as differential data) TpD or TpDX serving as a differential signal to be transmitted to a communication partner is supplied to each of the inverters 36 and 37 described below. I have. The differential data TpD and TpDX are, for example, such that when one of them is 1, the other is 0.

The output terminal of the NAND gate 34 ₁ to 34 _4, a plurality of transistors p connected in parallel to the power supply
11 to p14 and transistors p21 to p21
It is connected to 24 sets of gates.

The transistors p11 to p14 are for pull-up, and their sources are all connected to the power supply, and their drains are all connected to the drain of the transistor 38. The differential data TpD is supplied to the gate of the transistor 38 via the inverter 36. Therefore, the transistor 38 is turned on / off in accordance with the differential data TpD.
It has been made to turn off.

The source of the transistor 38 is the transistor N1 which forms a current mirror circuit with the transistor N1.
2 and the source of the transistor N2 is grounded. The gate of the transistor N2 is connected to the gate of the transistor N1 whose source is grounded, and the gate of the transistor N1 is also connected to its drain. The connection point between the gate and the drain of the transistor N1 is connected to the drain of the transistor 40 whose source is connected to the current source Iref. The drive circuit 12 is connected to the gate of the transistor 40.
Is enabled or disabled (di
sable) signal is supplied. Here, the signal Active is
For example, when the drive circuit 12 is at the L or H level,
Is enabled or disabled
Each is made to be in a state.

Here, when the transistor 40 is turned on, the transistors N1 and N2 constituting the current mirror circuit operate, whereby a current corresponding to the differential data TpD flows through the transistor 38. Then, a signal at a connection point between the drain of the transistor 38 and the drains of the transistors p11 to p14 connected in parallel is output as one signal Tp of the differential signal.

Similarly to the transistors p11 to p14, the transistors p21 to p24 are for pull-up, and their sources are all connected to the power supply, and the drains are all the drains of the transistor 39. Is connected to The differential data TpDX is supplied to the gate of the transistor 39 via the inverter 37. Therefore, the transistor 39 is turned on / off in accordance with the differential data TpDX. .

The source of the transistor 39 is the transistor N1 which forms a current mirror circuit with the transistor N1.
3 and the source of the transistor N3 is grounded. Further, the gate of the transistor N3 is connected to the gate of the transistor N1, like the gate of the transistor N2. Therefore, when the transistor 40 is turned on, the transistors N1 and N3 constituting the current mirror circuit operate, thereby
The current corresponding to the differential data TpDX is the transistor 3
Flow to 9. And the drain of the transistor 39,
The signal at the connection point with the drains of the transistors p21 to p24 connected in parallel is the other signal T of the differential signal.
Output as pX.

The output terminal of the signal Tp and the signal TpX
Is connected in series with two resistors Rc for detecting a common mode voltage and a bias voltage from a communication partner.

Here, transistors N2 and N3 are
For example, in each case, a current of 8 mA flows. The transistors p11 to p1 connected in parallel
The set of 4 and the set of transistors p21 to p24 are:
For example, in each case, a current of 4 mA flows.

Further, for the set of transistors p11 to p14, when the width of the channel of the transistor p11 is W, the width of the channel of the transistor p12 through p14 are respectively in ^{2 1 W, 2 2 W,} 2 3 W . Thus, the transistor p12 to p14, by each turning on by itself, as compared with the case where only the transistor p11 is turned on, 2 ^1, 2 ^2, 2 ³ times have been current to flow. That is, when the signal TpEn is at the H level, the transistors p11 to p14 connected in parallel
Only the bit corresponding to the bit whose count value of the up / down counter 32 is 1 is turned on, and a current corresponding to the count value flows. That is, the transistors p11 to p14 basically function as switches, but since the channel width is set as described above, a current corresponding to the count value flows.

The transistors p21 to p24 have the same configuration as the transistors p11 to p14. Therefore, when the signal TpEn is at the H level, a current corresponding to the count value of the up / down counter 32 flows. I have.

The transistors p11 to p14 or p2
Since the currents flowing from 1 to p24 flow through the transistors 38 and N2 or 39 and N3, the currents of the signals Tp and TpX change according to the count value of the up / down counter 32.

[0050] In the other NAND gate 35 ₁ to 35 ₄ input terminal, to both, are adapted as one of the common mode signal, for example, the speed signal SpdSig supplied. Speed signal SpdSig
Sets the transmission rate to, for example, 100 Mbps or 20 Mbps.
When it is set to 0 Mbps, it is set to the L or H level, respectively.

The output terminals of the NAND gates 35 _{1 to} 35 ₄ are connected to a plurality of transistors p connected in parallel to the power supply.
31 to p34 and transistors p41 to p41
It is connected to 44 sets of gates.

The transistors p31 to p34 are used to change the voltage of the common mode signal. All of the sources are connected to the power supply, and all of the drains are connected to the drain of the transistor 38. Have been.

Similarly to the transistors p31 to p34, the transistors p41 to p44 are used to change the voltage of the common mode signal. All the sources are connected to the power supply, and the drains are all connected to the power supply. , And the drain of the transistor 39.

Here, transistors p31 to p34
Is similar to the transistors p11 to p14 from the viewpoint of a switch for adjusting the current flowing through the transistor 38, but is based on the bias fluctuation in that the change in the voltage of the common mode signal due to the bias fluctuation is compensated. This is different from transistors p11 to p14 which compensate for a change in voltage of the differential signal Tp. Therefore, the transistor p
The ratio of the channel widths of 31 to p34 is
11 to p14, but the current flowing when outputting a differential signal and the current flowing when outputting a common mode signal are generally different.
The width of each channel from p to
The width is different from the width of each of the channels 11 to p14. That is, when the transistors p11 to p14 need to supply a pull-up current of, for example, 4 mA at the time of outputting a differential signal, the transistors p31 to p34 supply a pull-up current of, for example, 0.5 mA at the time of outputting a common-mode signal. When it is necessary to flow, the width of each channel of the transistors p31 to p34 and the transistor p1
The ratio of the channel width of each of 1 to p14 is 1: 8 which is the ratio of the current.

Therefore, in this case, if the channel width of the transistor p11 is represented by W as described above, the channel width of each of the transistors p31 to p34 is 2 ⁰
W / 8,2 and has a ^{1 W / 8,2 2 W / 8,2} 3 W / 8.

It should be noted that the above is the same as the transistor p41.
The same applies to p44 to p44.

The connection point of the two resistors Rc for detecting the common mode voltage and the bias voltage is connected to transmission gates 41 and 42. Transmission gates 41 and 42 each include an N-channel MOSFET and a P-channel MOSFET whose sources and drains are connected to each other, and an inverter that connects the gates of the two FETs. Signal Idle
Alternatively, the output of the NOR gate 44 is supplied. The transmission gate 41 or 42 is connected to the signal Idle or the NOR gate 4 respectively.
4 is, for example, H level or L level,
The conductive state or the insulated state is set.

Here, the signal Idle is set to the H level only when the cable 1 is in the high impedance state, and is set to the L level otherwise.

Transmission gate 41 or 42
Are turned on, the respective outputs are supplied to one end of a capacitor Cref whose other end is grounded or to the inverting input terminal (-) of the comparator 45. And the capacitor Cref
The connection point between the transmission gate 41 and the non-inverting input terminal (+) of the comparator 45 is connected.
The comparator 45 compares the voltage of the non-inverting input terminal with the voltage of the inverting input terminal. If the voltage of the non-inverting input terminal is higher than the voltage of the inverting input terminal, the comparator 45 sets the H level. The L level is output as a signal UD. The signal UD is supplied to an up / down terminal (U / D) of the up / down counter 32.

One input terminal of the NOR gate 44 has
The speed signal SpdSig and the signal TpEn are supplied to the other input terminal via the inverter 43, respectively. Therefore, the NOR gate 44 goes high only when the signal TpEn is high and the speed signal SpdSig is low, so that the transmission gate 42 is turned on.

The speed signal SpdSig is also supplied to one input terminal of a three-input NAND gate 47 via an inverter 48.
7, a clock CK and a signal TpEn are supplied to the remaining two input terminals. And NAND gate 4
The output of 7 is supplied to the clock terminal (CK) of the up / down counter 32 via the inverter 49.

Next, a method for generating the signal Idle will be described with reference to FIG.

FIG. 3A shows a configuration example of a generation circuit for generating the signal Idle.

Each of the comparators 61 and 62 is a three-level detection comparator (offset comparator), and the differential signal Tp or TpX is input to each non-inverting input terminal or inverting input terminal. FIG.
(B) shows the differential signal T to the comparators 61 and 62.
It shows the output VO1 or VO2 of the comparator 61 or 62, respectively, corresponding to the input of p and TpX, as shown, when the differential signal Tp is a voltage sufficiently higher than TpX, VO1 or VO2 respectively H
Or it becomes L level. When the differential signal TpX has a voltage sufficiently higher than Tp, VO1 or VO2 goes to L or H level, respectively, and the differential signal Tp and TpX
When and are almost the same voltage (when the voltage difference is small),
Both VO1 and VO2 go to the H level.

When the cable 1 is in the high impedance state, there is almost no difference between the differential signals Tp and TpX. Therefore, the signal goes high only when both VO1 and VO2 are high, and otherwise goes low. If a signal having a level is generated (for example, VO1 and V
If the logical product with O2 is obtained, the signal becomes the signal Idle.

Next, the operation of drive circuit 12 shown in FIG. 2 will be described.

The drive circuit 12 is enabled.
The signal Active to be in the state changes from H level to L
At that level, transistor 40 is turned on, thereby allowing transistors N1 and N2 and N3 to allow a pull-down current to flow through transistors 38 and 39.

When the cable 1 is in the high impedance state, the signal Idle of the H level is supplied to the transmission gate 41 as described above, whereby the transmission gate 41
Becomes conductive. The transmission gate 41
As described above, since the transmission gate 41 is connected to the connection point of the two resistors Rc and becomes conductive, the voltage at the connection point, that is, in this case, the cable 1 is set to the high impedance state. Therefore, the bias voltage output from the cable bias circuit 11 is applied to the capacitor Cref. As a result, the capacitor Cref is charged with a charge corresponding to the bias voltage.

When the signal Idel is at the H level, the differential signal is not transmitted and received, so that the signal TpEn is at the L level. Therefore, the signal TpE
Since n is supplied to one input terminal via the inverter 43 and the output of the NOR gate 44 is at L level, the transmission gate 42 is in an insulated state. Further, in the NAND gate 47 in which the signal TpEn is supplied to one of the three input terminals, the clock CK is masked by the signal TpEn, so that the output level does not change from the H level. , The up / down counter 32 does not operate.

[0070] The output of the NAND gate 34 ₁ to 34 ₄ which signal TpEn is supplied to one input terminal H
Level, and thus the transistors p11 to p14
And p21 to p24 are all turned off.

Further, when the signal Idel is at the H level, the speed signal SpdSig is at the L level, and therefore, the speed signal SpdSig is supplied to one of the input terminals.
The outputs of the ND gates 35 _{1 to} 35 ₄ are at the H level, whereby the transistors p31 to p34 and p41
To p44 are all turned off.

When the differential signal is output, the signal Id
le or TpEn is set to L or H level, respectively, and the speed signal SpdSig is kept at L level. When the signal Idle goes to L level, the transmission gate 41 is insulated and the capacitor Cr
A voltage corresponding to the electric charge charged to ef, that is, a bias voltage of the cable is applied to the non-inverting input terminal of the comparator 45.

When the signal TpEn goes high,
One input terminal of the NOR gate 44 has an inverter 4
The L level is supplied via 3. Further, since the L-level speed signal SpdSig is supplied to the other input terminal of the NOR gate 44, the output of the NOR gate 44 becomes H-level. As a result, the transmission gate 42 becomes conductive.

[0074] On the other hand, when the signal TpEn becomes H level, among the NAND gates 34 ₁ through 34 _4, of the count value of the up-down counter 32, the output of which corresponds to a bit that is a 1 and the L level Become. In this case, among the set of transistors p11 to p14, the one whose L level is supplied to the gate is turned on, and the set of transistors p21 to p24 whose L level is supplied to the gate is also turned on. Accordingly, a state in which a pull-up current can flow through the transistor 38 or 39 is established.

Then, the differential data TpD and TpDX
Of the differential data TpD or Td
The pDX is supplied to the gate of the transistor 38 or 39 via the inverter 36 or 37, respectively, whereby the transistor 38 or 39 turns on / off in response to the differential data TpD or TpDX.

As described above, the transistor 38 or 39
Signal Tp or T corresponding to the current flowing through
pX is output to cable 1.

In this case, the voltage at the connection point of the two resistors Rc is the average value of the differential signals Tp and TpX, that is, the common mode voltage, which is in the conductive state as described above. The signal is applied to the inverting input terminal of the comparator 45 via the transmission gate 42.

The comparator 45 includes a capacitor Cref
A bias voltage, which is a voltage corresponding to the electric charge stored in the memory, is compared with a common mode voltage supplied via the transmission gate 42. If the bias voltage is higher than the common mode voltage, the H level is set. Output the L level. The output of the comparator 45 is supplied to an up / down terminal (U / D) of the up / down counter 32 as a UD signal (signal UD).

Here, when the UD signal supplied to the up / down terminal (U / D) is at the H level or the L level, the up / down counter 32 outputs its clock terminal (CK).
The count value is incremented or decremented by 1 at the timing of the rising edge or the falling edge of the input to. In this case, since the signal TpEn is at the H level and the speed signal SpdSig is at the L level, the output of the NAND gate 47 is an inverted version of the clock CK. However, if the bias voltage is higher than the common mode voltage, it is incremented according to the clock, otherwise, it is decremented according to the clock.

As described above, the set of transistors p11 to p14 and the set of transistors p21 to p24 are turned on / off according to the count value, and the ratio of their channel widths is 2 as described above. Since the power is raised to a power, the pull-up current corresponding to the count value flows according to the set of transistors p11 to p14 or the set of transistors p21 to p24.
That is, thereby, the current corresponding to the differential signal Tp or TpX changes, and the common mode voltage which is the voltage at the connection point of the two resistors Rc changes.

As described above, this common mode voltage is supplied to the comparator 45 via the transmission gate 42. Hereinafter, this common mode voltage corresponds to the charge charged in the capacitor Cref. The same processing is repeated until the voltage becomes equal to (approximately equal to) the bias voltage in the high impedance state.

Thereafter, when a speed signal SpdSig, for example, is output as a common mode signal, the speed signal SpdSig is set to the H level. When the speed signal SpdSig becomes H level, the speed signal SpdSig becomes N level supplied through the inverter 48.
In the AND gate 47, the speed signal Spd
The clock CK is masked by Sig, and its output level remains at H level and does not change, so that the up / down counter 32 stops operating. That is, in this case, the up / down counter 32 outputs the speed signal S
The operation is stopped while the count value immediately before the pdSig becomes H level is held. Here, it is assumed that the speed signal SpdSig has already been set to the H level after the bias voltage and the common mode voltage have become substantially equal.

When the speed signal SpdSig is H
Level, the NAND gates 35 ₁ through 35 3
5 out of _4, of the count value of the up-down counter 32, the output of which corresponds to a bit that is a 1 L
Level. In this case, the transistors p31 to p3
Of the four sets, those whose L level is supplied to the gate are turned on, and the transistors p41 to p44 are turned on.
Similarly, the pair whose L level is supplied to the gate is turned on.

As described above, since the width of the channel of each of the transistors p31 to p34 and p41 to p44 corresponds to the pull-up current flowing to output the common mode signal, it is held by the up-down counter 32. The transistors p31 to p34 and p41 to p44 are turned on in accordance with the count value (as described above, the count value that makes the bias voltage and the common mode voltage substantially equal), so that the common mode voltage fluctuates by the specified value. Of the pull-up current flows.

Next, FIG. 4 shows another example of the configuration of the drive circuit 12 of FIG. Note that, in the figure, parts corresponding to those in FIG. 2 are denoted by the same reference numerals. That is, the drive circuit 12 does not include the transmission gates 41 and 42, the inverter 43, the NOR gate 44, and the capacitor Cref, and supplies a predetermined reference voltage Vref to the non-inverting input terminal of the comparator 45. The configuration is otherwise the same as in FIG.

As described above, the predetermined reference voltage Vref is supplied to the non-inverting input terminal of the comparator 45. Therefore, in the embodiment of FIG. 4, the common mode voltage is changed to the reference voltage Vref. Transistors p11 to p1 so that
4, ON / OFF of p21 to p24, p31 to p34, p41 to p44 is controlled.

As the reference voltage Vref, for example, a bias voltage output from the cable bias circuit 11 is supplied. In this case, the transistors p11 to p14 are set so that the common mode voltage becomes equal to the bias voltage. , P21 to p24, p31 to p34, and p41 to p44 are controlled.

The embodiment of FIG. 4 is applicable to a drive circuit 12 or 22 having a cable bias circuit 11 or 21.
It is necessary to adopt a configuration as shown in FIG.

As described above, the transistors p11 to p11
Since 14, p21 to p24, p31 to p34, and p41 to p44 function as switches, the length of the channel (corresponding to the length of the gate) can be set to a minimum necessary value. Therefore, the size of these transistors can be reduced, and as a result, the layout area can be significantly reduced when a CMOS or the like is used.

Further, when a differential signal is output, the common mode voltage is controlled by feedback so that an unnecessary current as a common mode signal does not flow, so that power consumption can be reduced. Becomes

Further, a common mode voltage when a differential signal is output and a common mode voltage (bias voltage) when the cable 1 is in a high impedance state are compared, and feedback is applied so that the two become equal. By controlling the pull-up current, it is possible to cope with a wide range variation of the common mode voltage and to cope with a low voltage power supply.

In this embodiment, in order to turn on / off the current (pull-up current) as differential signal Tp or TpX, four transistors p11 to p11
Although 14 or p21 to p24 are used in parallel connection, the number of transistors connected in parallel is not limited to four. That is, the number of transistors connected in parallel for turning on / off the current is, for example, the power supply voltage, the fluctuation range of the common mode voltage at the time of differential signal output, and the change of the common mode voltage due to turning on / off the speed signal SpdSig. It is preferable to set an appropriate value corresponding to the above. This means that the transistors p31 to p31 operating at the time of outputting the common mode signal
The same applies to the set of 34 and the sets of p41 to p44.

In this embodiment, the transistors p11 to p14, p21 to p24, and p21 to p14 as switches connected in parallel for controlling the current are provided on the pull-up side.
Although p31 to p34 and p41 to p44 are provided, such a transistor as a switch can be provided on the pull-down side, and further, can be provided on both the pull-up side and the pull-down side. is there. However, for example, in a circuit that drives a differential signal such as the drive circuit 12 shown in FIG. 2 or FIG. 4, the H level voltage of the differential signal Tp or TpX is increased by increasing the common mode voltage. Since the reduction is a particular problem, it is desirable to provide a switch connected in parallel for controlling the current on the pull-up side.

Further, in this embodiment, transistors are used as switches connected in parallel for controlling current, but other devices can be used.

In the present embodiment, the transistor is turned on in accordance with the count value. However, the transistor can be turned off.

Further, in this embodiment, the current as a differential signal is controlled by using transistors having different channel widths. However, in controlling this current, a plurality of transistors having the same channel width are used. It is also possible to connect transistors in parallel. However, in this case, assuming that the number of bits of the up / down counter 32 is n, 2 ⁿ transistors are required, and the count value output by the up / down counter 32 is only 2 bits corresponding to the number represented by the count value. It needs to be converted to a decimal number.

[0097]

According to the drive circuit of the first aspect and the drive method of the fifth aspect, the differential signal and the bias voltage are compared, and the current is turned on / off in accordance with the comparison result. On / off of a plurality of switching means connected in parallel to be turned off is controlled. Therefore, it is possible to cope with the fluctuation of the bias voltage.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration example of an embodiment of a communication system to which the present invention has been applied.

FIG. 2 is a circuit diagram showing a configuration example of drive circuits 12, 15, 22, and 25 in FIG.

FIG. 3 is a diagram for explaining a method of generating a signal Idle of FIG. 2;

FIG. 4 is a circuit diagram showing another configuration example of the drive circuits 12 and 15 of FIG.

FIG. 5 is a circuit diagram showing a configuration of an example of a conventional communication system.

FIG. 6 is a circuit diagram showing a configuration of an example of a conventional drive circuit.

[Explanation of symbols]

1 cable, 11 cable bias circuit, 12
Drive circuit, 13 receive circuit, 14 common mode signal detection circuit, 15 drive circuit, 16
Receive circuit, 21 Cable bias circuit, 2
2 drive circuit, 23 receive circuit, 24 common mode signal detection circuit, 25 drive circuit, 2
6 receive circuit, 32 up / down counter,
34 _{1 to} 34 ₄ , 35 _{1 to} 35 ₄ NAND gates,
36, 37 inverter, 38 to 40 transistor, 41, 42 transmission gate, 43
Inverter, 44 NOR gate, 45 comparator, 47 NAND gate, 48, 49 inverter, 61, 62 comparator

Claims (5)

[Claims] 1. A drive circuit for flowing a current corresponding to a differential signal to be transmitted to a communication partner connected via a cable biased to a predetermined bias voltage, wherein the drive circuit turns on / off the current. Switching means connected in parallel with each other, comparison means for comparing the differential signal with the bias voltage, and control means for controlling on / off of the switching means in accordance with the comparison result of the comparison means. A drive circuit, comprising: 2. The drive circuit according to claim 1, wherein the cable is biased by a communication partner connected to the cable. 3. A storage device for storing the bias voltage when the cable is in a high impedance state, wherein the comparing device compares the differential signal with the bias voltage stored in the storage device. 3. The drive circuit according to claim 2, wherein: 4. When information is transmitted by setting the average value of the differential signal to a predetermined voltage, supply of the comparison result by the comparing means to the control means is stopped. Item 2. The drive circuit according to item 1. 5. A driving method in a drive circuit for flowing a current corresponding to a differential signal to be transmitted to a communication partner connected via a cable biased to a predetermined bias voltage, wherein the drive circuit comprises: In the case where a plurality of switching means connected in parallel for turning on / off a current is provided, the differential signal is compared with the bias voltage, and on / off of the switching means is controlled in accordance with the comparison result. A drive method characterized by performing.