JPH09321810A - Serial data communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a kind of data transmittable by the transmission of one time without inviting the complication of procedures by making a transmitter side able to selectively output at least three kinds of voltage signals and constituting a receiver side so as to identify them. SOLUTION: In the output interface circuit 102 of a transmitter 100, when a transistor(TR) 104 is turned ON, the third voltage signals δv3 of a ground potential level are outputted to a signal line 3. When the TR 104 is turned OFF and the TR 103 is turned ON, the first voltage signals δv1 of a relatively high level are outputted. When the TRs 103 and 104 are turned OFF, the voltage signals δv2 of a relatively low level are outputted. Comparators 203 and 204 inside an input interface circuit 202 compare the voltage signals of the signal line 3 supplied to an input terminal-with reference voltages Vref1 and Vref2 supplied to noninverted input terminal +.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data communication system in which data is transmitted by a time-division serial signal.

[0002]

In serial data communication, for example, when a pulse length variable system (PWM system) for converting a data value into a pulse length of a signal and transmitting the signal is adopted, data that can be transmitted by one transmission is transmitted. Types are limited by the frame length of the transmitted data and the sampling rate of the receiving side. For example, when performing asynchronous communication of 8-bit data, it can be transmitted by one transmission. This data will be limited to 256 types.

In this case, in the pulse length variable system, 1
In order to increase the number of types of data that can be transmitted by one transmission, it is conceivable to increase the length of one frame, but this causes a new problem that the communication delay increases. It is also possible to increase the data types by increasing the sampling rate on the receiving side. However, on the receiving side, since a basic interrupt processing routine usually exists in the program for controlling the receiving operation, the above-mentioned shortening of the sampling rate naturally has many restrictions. However, there is a problem that it is not practical.

In the asynchronous communication of 8-bit data, if the number of types of data that can be transmitted by one transmission is increased, the number of bits of data may be increased, but this makes the procedure of data processing on the receiving side troublesome. It is unavoidable that it becomes impractical.

The present invention has been made in view of the above circumstances, and an object of the present invention is to influence the type of data that can be transmitted by one transmission to affect the frame length of transmission data or to the receiving side. (EN) Provided is a serial data communication system which can be increased without changing the sampling rate and complicating the procedure for data processing.

[0006]

According to a first aspect of the invention, at least 3 signal lines are provided from the transmitter side to the signal line.
The first voltage signal, the second voltage signal, and the third voltage signal that are set to the stepped level can be selectively output through the output interface circuit. When the voltage signal is output to the signal line in this way, the input interface circuit on the receiving device side discriminates the level of the voltage signal and converts it into a binary signal. Specifically, when the state in which the first voltage signal is output and the state in which the second voltage signal is output are repeated with respect to the signal line, the repeating mode is set by the first signal discriminating means. When the binary signal corresponding to the signal is output and the state in which the first voltage signal is output and the state in which the third voltage signal is output are repeated for the signal line, the second signal discrimination is performed. The means outputs a binary signal corresponding to the repetition mode.

That is, a state in which the first voltage signal and the second voltage signal are alternately transmitted and a state in which the first voltage signal and the third voltage signal are alternately transmitted from the transmitter side to the signal line The difference from the state can be recognized on the receiving device side, and as a result, the number of types of data that can be transmitted by one transmission increases. In this case, there is no need to increase the length of one frame or the number of bits of the data to be transmitted or to increase the sampling rate on the receiving side, so that there is no risk of causing the problems of the conventional configuration.

According to the second aspect of the present invention, the divided voltage by the voltage dividing circuit having the first resistance and the second resistance for dividing the output voltage of the power supply terminal is constantly applied to the signal line by the second voltage. Can be applied as the voltage of.

In a state in which the first switching element in the output interface circuit is turned on, the third resistor is connected in parallel with the first resistor in the voltage dividing circuit, and the first resistor is connected to the signal line. The first voltage signal having a level different from that of the voltage signal is applied. Further, when the second switching element in the output interface circuit is turned on, both ends of the second resistor in the voltage dividing circuit are short-circuited, and the first voltage signal and the second voltage are supplied to the signal line. The third voltage signal having a level different from that of the signal is applied.

Therefore, on the side of the transmitter, the control necessary for the above-mentioned data transmission, that is, by selectively turning on and off the first switching element and the second switching element, The control of switching between the state in which the first voltage signal and the second voltage signal are alternately transmitted and the state in which the first voltage signal and the third voltage signal are alternately transmitted can be easily performed.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an electrical configuration example of a data transmission system adopting a serial data communication system according to the present invention. The system shown in FIG. 1 is configured to transmit digital data from the ECU 100, which constitutes the transmitter, to the ECU 200, which constitutes the receiver, through the signal line 3.

The transmission side ECU 100 is provided with an MPU 101 for processing an operation signal input from an operation section (not shown) and controlling transmission through the signal line 3. Further, the receiving ECU 200 is provided with an MPU 201 for performing reception control through the signal line 3 and control of a load (not shown). In this case, the MP
U101 and 201 are connected to each other via the ground potential line 4 for obtaining the reference potential level.

The signal line 3 is connected to the ECU 100 on the transmission side.
An output interface circuit 102 for transmitting digital data to the digital camera is provided. The output interface circuit 102 includes a pnp-type transistor 103 (corresponding to the first switching element in the present invention) and an npn-type transistor 104 (corresponding to the second switching element in the present invention). The base of 103 is connected to the output port Q1 of the MPU 101 via the resistor 105, and the base of the transistor 104 is MPU.
The output port Q2 of 101 is connected via a resistor 106. The base bias resistors 107 and 1 are provided between the base and emitter of the transistors 103 and 104.
08 are respectively connected.

The output interface circuit 102 is also provided.
In this case, between the power supply terminal + Vcc and the ground potential line 4, between the emitter and collector of the transistor 103, the voltage dividing resistor 109 (corresponding to the third resistor in the present invention) and 110 (in the present invention). The so-called second resistor) is connected in series, and the common connection point of the voltage dividing resistors 109 and 110 is connected to the signal line 3. Further, the collector-emitter of the transistor 104 is connected in parallel with the voltage dividing resistor 110 on the ground potential line 4 side.

On the other hand, the receiving ECU 200 is provided with an input interface circuit 202 for receiving the digital data sent to the signal line 3. The input interface circuit 202 includes feedback resistors 2
The comparators 203 and 204 (corresponding to the first signal discriminating means and the second signal discriminating means in the present invention, respectively) to which appropriate hysteresis is given by 03a and 204a are provided, and the output terminals of these comparators 203 and 204 are They are connected to the input ports P1 and P2 of the MPU 201, respectively.

The input interface circuit 202 is also provided.
Is provided with a reference voltage generation circuit 205 for applying reference voltages of different levels to the respective non-inverting input terminals (+) of the comparators 203 and 204. This reference voltage generating circuit 205 includes resistors 205a, 205b and 20 between a power supply terminal + Vcc and a ground power supply line.
5c is connected in series. In this embodiment, a reference voltage Vref1 of, for example, 3.75V is applied to the non-inverting input terminal (+) of the comparator 203, and a reference voltage of, for example, 1.25V is applied to the non-inverting input terminal (+) of the comparator 204. It is set so that Vref2 is given.

Further, in the input interface circuit 202, a pull-up resistor 206 (corresponding to the first resistor in the present invention) is connected between the power supply terminal + Vcc and the signal line 3 and the signal line thereof is connected. 3 is the input resistance 207
Is connected to each inverting input terminal (−) of the comparators 203 and 204 via. The pull-up resistor 2
The voltage dividing circuit 500 according to the present invention is configured by 06 and the voltage dividing resistor 110.

The output interface circuit 102 having the above configuration is provided, and the input interface circuit 20 is provided.
The pull-up resistor 2 that forms the voltage dividing circuit 500 with the voltage dividing resistor 110 in the output interface circuit 102 on the second side.
As a result of the provision of 06, the output interface circuit 102
From the signal line 3 to the internal transistor 103
According to the ON / OFF state of the switch 104 and the switch 104, it is possible to selectively output the following three-stage voltage signals. However, the collectors of the transistors 103 and 104
Ignore the emitter saturation voltage.

When the transistor 104 is turned on, the transistor 104 short-circuits both ends of the voltage dividing resistor 110 in the voltage dividing circuit 500, so that the signal line 3
A third voltage signal δv3 at the ground potential level is output to (independent of the on / off state of the transistor 103).

When the transistor 104 is turned off and the transistor 103 is turned on, the transistor 103 connects the voltage dividing resistor 109 in parallel with the voltage dividing resistor 206 in the voltage dividing circuit 500, so that the signal line 3 In contrast, the parallel circuit of the resistors 109 and 206 and the resistor 11
A relatively high level first voltage signal δv1 divided by 0 is output. In this embodiment, the level of the first voltage signal δv1 is set to 5V.

When both the transistors 103 and 104 are turned off, the second low-level second voltage signal δv2, which is divided by the pull-up resistor 206 and the voltage dividing resistor 110, is output to the signal line 3. To be done. In this embodiment, the level of this second voltage signal δv2 is 2.5.
It is set to V.

In this case, as is apparent from the above description, the comparators 203 and 204 in the input interface circuit 202 have the voltage signal of the signal line 3 applied to the inverting input terminal (-) and the non-inverting input terminal (+). ) Is compared with the reference voltages Vref1 (= 3.75V) and Vref2 (= 1.25V) given to each of the above.

Therefore, the third voltage signal δ is applied to the signal line 3.
In the state (the state) in which v3 (ground potential level) is output, both the comparators 203 and 204 output the “H” level signal. Further, in the state (the state) in which the first voltage signal δv1 (5V) is output to the signal line 3, both the comparators 203 and 204 output the “L” level signal. In addition, signal line 3
In the state (the state) in which the second voltage signal δv2 (2.5V) is output to, the comparator 203 outputs the “H” level signal and the comparator 204 outputs the “L” level signal.

As a result, the comparator 203 can generate a binary signal having a different logic level depending on whether the first voltage signal δv1 is input through the signal line 3 or the second voltage signal δv2 is input. It is composed.
In addition, the comparator 204 receives the state in which the first voltage signal δv1 is input through the signal line 3 and the third voltage signal δ
It is configured to generate a binary signal that has a different logic level when v3 is input.

Comparators 203 and 20 as described above
4 are input to the input ports P1 and P2 of the MPU 201, respectively.
In No. 1, the level of the voltage signal transmitted through the signal line 3 is determined in three stages based on the input signal as described above, and based on the determination result, the above-mentioned binary signal (first The voltage signal δv1 is “mark”, the second voltage signal δv2 is “space”, and the first voltage signal δ
v1 is a “mark”, and the third voltage signal δv3 is a “space”).

Here, an example will be described in which data communication is performed between the ECUs 100 and 200 by a pulse length variable system (PWM system) in which a data value is converted into a pulse length of a signal and transmitted.

That is, for example, when transmitting a signal of a variable pulse length system of 40 ms per frame, as shown in FIG. 2A, the pulse width ΔT (for example, 10 ms, 20 ms, or 30 ms) which falls from the mark state. Each pulse signal whose data value is (?) Is transmitted through the signal line 3 as data A, B, and C each of which is a binary signal.

In this case, the total frame length may be doubled in order to double the number of types of data that can be transmitted, but this is not practical because the communication delay increases. Further, by increasing the sampling rate of the input signal in the receiving ECU 200, the minimum pulse width of the transmission data can be reduced to ½. However, M of the receiving ECU 200
Since the PU 201 usually has a large number of basic interrupt processing routines in its control program, the above-mentioned reduction of the sampling rate is naturally constrained, resulting in practical application. There is a problem that it is not appropriate.

On the other hand, in this embodiment, as shown in FIG.
As shown in (b) and (c), from the ECU 100 side, the transistor 103 in the output interface circuit 102,
Two types of data A ′ composed of different binary signals that can be respectively identified according to the selective on / off state of 104.
And A ″, B ′ and B ″, C ′ and C ″ can be transmitted, and the logic level of the data thus transmitted can be identified on the ECU 200 side through the input interface circuit 202.

However, in FIGS. 2B and 2C, the ON and OFF states of the transistors 103 and 104 are respectively set to O.
Shown by N and OFF, input terminals P1 and P of MPU201
The level of the binary signal given to 2 is represented by "1" corresponding to the "H" level signal and "0" corresponding to the "L" level signal.

Therefore, according to the present embodiment, it is possible to increase the frame length of the transmission data or increase the types of data that can be transmitted without increasing the sampling rate of the input signal in the receiving ECU 200. It is extremely useful in practical use.

Further, when data communication is performed between the ECUs 100 and 200 by a start-stop synchronization method, in the conventional configuration, only 256 kinds of data can be transmitted when the transmission data is 8 bits. Since the data can be transmitted in a state in which the logical level of is switched in two steps, 512 types of data can be transmitted as a result, and the receiving side only needs to perform 8-bit processing.

The present invention is not limited to the above-described embodiment, but the following modifications or expansions are possible. On the transmitting side, the level of the voltage signal output to the signal line is switched to three levels (0V, 2.5V, 5V), but it may be switched to multiple levels. However, in this case, it is necessary to add signal discriminating means capable of discriminating the levels of the voltage signals to the receiving side. The first and second signal discriminating means are connected to the AD converter I.
It may be configured by using C.

In the example of FIG. 1, transistors 103 and 1
Although the output interface circuit 102 is configured by combining 04 and the resistors 105 to 110, the output interface circuit having the same function can be configured by combining the resistor and another circuit element such as an FET. The pull-up resistor 206 included in the voltage dividing circuit 500 may be provided on the output interface circuit 102 side.

[Brief description of drawings]

FIG. 1 is an electrical configuration diagram showing one embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation.

[Explanation of symbols]

In the figure, 3 is a signal line, 100 is an ECU (transmission device),
101 is an MPU, 102 is an output interface circuit, 1
03 is a transistor (first switching element), 10
4 is a transistor (second switching element), 109
Is a resistance for voltage division (third resistance), 110 is a resistance for voltage division (second resistance), 200 is an ECU (reception device), and 201 is M.
PU, 202 is an input interface circuit, 203 is a comparator (first signal discriminating means), 204 is a comparator (second signal discriminating means), 205 is a reference voltage generating circuit, 2
Reference numeral 06 represents a pull-up resistor (first resistor), and 500 represents a voltage dividing circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H04L 5/04 H04L 5/04

Claims (2)

[Claims] 1. A serial data communication system for transmitting a serial signal from a transmitting device to a receiving device via a signal line, wherein the transmitting device has at least 3 lines for the signal line.
An output interface circuit capable of selectively outputting the first voltage signal, the second voltage signal, and the third voltage signal set to the stepped level is provided, and the first interface is provided on the receiving device side through the signal line. First signal discriminating means for generating a binary signal having different logical levels depending on the state in which the voltage signal is input and the state in which the second voltage signal is input, and the first voltage signal through the signal line. And a second signal discriminating means for generating a binary signal having a different logic level depending on the input of the signal and the input of the third voltage signal. 2. A first resistor and a second resistor for dividing the output voltage of the power supply terminal, the divided voltage being provided so as to be applied to the signal line as the second voltage signal. The output interface circuit applies the first voltage signal to the signal line by connecting a third resistor in parallel with a first resistor in the voltage divider circuit in an ON state. And a second switching element for applying the third voltage signal to the signal line by short-circuiting both ends of the second resistor in the voltage dividing circuit in the ON state. The serial data communication system according to claim 1, wherein the serial data communication system is configured.