JP3537153B2 - Signal processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing system .

[0002]

2. Description of the Related Art In general, considering the transition of the structural technology of the electric system of a camera, first, in a first stage, a sequence control circuit composed of a CMOS and a bibola (hereinafter referred to as Bi) are used.
An auto-exposure (hereinafter, referred to as AE) circuit comprising an automatic focus adjustment (hereinafter, referred to as AF) circuit and the like are connected. And in the second stage, the CMO
A microcomputer (hereinafter, referred to as a microcomputer) made of S and an AE and AF circuit made of Bip are connected.

As a technology that has further advanced this, for example, as shown in "Photo Industry, May 1988, p. 88", a microcomputer composed of CMOS and an AE circuit composed of Bip are integrated into one chip by a Bi-COS process. The thing that has been turned up has appeared. Here, the circuit composed of Bip is A
E and AF circuits are used because the past flow is dragged, the analog circuit is easier to design for the Bip, and the Bip is easier to flow a large current.

Further, A using a CMOS microcomputer
As the F circuit, a reflected light amount integration type is generally used. In addition, in the camera technology, in recent years,
The display is frequently used by the LCD, and in the case of the LCD, in consideration of the adverse effect of the ambient temperature, LC
A technique of changing the voltage of a D / A converter as a D drive source according to temperature has also been proposed.

[0005]

However, when these CMOS microcomputers and Bip circuits are to be integrated into one chip, a Bip-CMOS process is required in the manufacturing process, leading to an increase in lead time and an increase in cost. . Further, since the analog section is set to Bip, the current consumption increases.

Since the reflected light amount integration type device used as the AF circuit using the CMOS microcomputer cannot perform logarithmic compression and has no division function, a high-precision distance measuring device can be obtained. Then, there is a disadvantage that the circuit scale becomes large.

Further, the AF circuit, AE circuit, remote control circuit, and the like of a camera have a drawback that they are susceptible to noise because they handle weak signals. Conventionally, the only way to prevent this is to improve the arrangement of parts and patterns. Did not.

Further, in the camera technology, digital timers are used in various places. The digital timer requires a clock, and the noise of the clock adversely affects various measuring circuits required for the photographing operation of the camera. Will be given.

[0009] When disposing the sensor in the chip containing the drive circuit of the power system for the temperature measurement as described above, it causes a temperature measuring erroneous, suitable electrostatic resulting LCP
Cannot provide pressure.

[0010] The present invention has been made in view of the above problems, and an object thereof is to provide a clock timer.
An object of the present invention is to provide a signal processing system provided with an analog timer circuit .

[0011]

According to one embodiment of the present invention, a digital signal processing system, an oscillation circuit for generating a clock pulse signal to be supplied to the digital signal processing system, and a weak signal are provided. in the signal processing system formed by forming the processing for the analog circuitry on a common semiconductor substrate, and a reference current source, a charging unit charges the capacitor by the reference current source, to reset the capacitor, D
/ A conversion means and temperature detection means, depending on the detected temperature
An analog timer circuit including a reference voltage setting unit that corrects the D / A conversion output and a comparison unit that compares the charging voltage of the capacitor to be charged with the reference voltage. A signal processing system that activates the analog timer circuit and inhibits the operation of the oscillation circuit in accordance with the output of the analog timer circuit.

[0012]

[0013]

[0014]

[0015]

[0016]

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

In other words, according to one aspect of the present invention, the charging unit includes the reference
The capacitor is charged by the current source and the capacitor is reset.
Set, detected by the temperature detection means in the reference voltage setting section
D / A conversion by D / A conversion means according to the detected temperature
The converted output is corrected, and the comparison unit of the analog timer circuit compares the charged voltage of the capacitor with the reference voltage. When the weak signal processing analog circuit is operated, the analog timer circuit is operated, and the operation of the oscillation circuit is inhibited in accordance with the output thereof.

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

[0033]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a CM according to the first embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration of a camera controller using an OS analog circuit. In the first embodiment, the analog circuit is
It is composed of an OS and a CMOS analog circuit and microcomputer are integrated into one chip.

More specifically, as shown in FIG.
com core) 1, booster circuit block 2, remote control circuit block 3, distance measuring circuit block 4, NPN motor pre-driver circuit block 5, motor constant voltage circuit block 6, T
Stable T proportional DAC circuit block 7, comparator 8,
B. C circuit block 9, temperature measurement circuit block 10, reset circuit block 11, reference voltage circuit block 12, photometry circuit block 13, strobe charge detection circuit block 1
4, a PI / PR detection circuit block 15, a PLED driver circuit block 16, and a PNP pre-driver circuit block 17 are integrally formed, and an EEPROM
18, an LCD 21, a switch 20, and a strobe circuit block 19 are provided.

Hereinafter, the operation of the camera controller using the CMOS analog circuit according to the first embodiment will be described in detail with reference to the flowcharts of FIGS.

First, the main sequence of the camera controller using the CMOS analog circuit according to the first embodiment will be described with reference to the flowchart of FIG.

When the battery is turned on, the reset is performed by the reset circuit block 11, and the program of the CPU 1 is started. Then, initialization of the flag of the CPU 1, the RAM, the port, and the analog circuit section is performed (step S101). Furthermore, B. The battery check is performed by the C circuit block 9, and if the result is OK, the process proceeds to the next step S103 (step S1).
02). Then, the voltage of the entire system is guaranteed by turning on the booster circuit block 2 (step S1).
03).

Subsequently, in the interrupt permission in step S104, a relay (not shown) in the block of the switch 20 is set.
Switch, power switch, rear cover open / close switch, film rewind switch, etc. (S10
4). If the power switch is "ON", the process proceeds to step S111. If the power switch is "OFF", the process proceeds to step S1.
The process moves to 06 (S105).

In step S106, the AF circuit is turned off, the booster circuit is turned off,
Set the power-off mode, such as turning off 1 or turning off the port. If the power drive flag is "ON", the power drive flag is turned "OFF" after a certain time has elapsed (steps S108 and S1).
09), the CPU 1 stops the original vibration and enters the stop state (step S110). The switches that can be accepted in the stop state include a power switch (when turned on, shift to a circle 1), a rear cover open / close switch, and a forced film rewind switch (shift to a circle 1 after processing).

On the other hand, if the power switch is turned on in step S105, the following processing is repeated. That is, first, the LCD 21 is displayed (step S111), and power is supplied to the distance measuring circuit block 4 so that the distance measuring circuit can operate at any time (step S112). In the case of the Bip circuit, since the current is large, it cannot be turned on at all times, and a time lag of several tens of milliseconds is required until the measurement can be performed since the switch is turned on after being pressed.

Then, in the flash charging, energy for flash emission is charged in the main capacitor in the flash circuit block 19 (step S113). This charging level is detected by the flash charging voltage detection circuit block 14, and if this charging is completed, the process proceeds to the next step S114 without doing anything.

Subsequently, the brightness of the subject is measured by the photometric circuit block 13 (step S114). At this time, it is determined whether or not the mode is the remote control mode (step S11).
5).

In the remote control mode,
The CPU 1 is used to set the remote control circuit block 3 to the operating state by the remote control setting process and to remove the influence of the original vibration noise.
To the standby state (steps S121, S12
2).

In the standby state, unlike the stop state, although the original vibration is moving, the clock is supplied to only the minimum necessary parts such as the display of the LCD 21, and the influence of noise on the analog circuit part is not affected. Almost gone. In this standby state, if a remote control signal is input, a subroutine "remote control reception interrupt" to be described later is performed.
(See FIG. 20), but if the release switch is pressed, a subroutine "release interrupt processing" described later will be performed.
(See FIG. 3) is executed. This subroutine "Relie
The "interrupt processing" is accepted at any time while the power switch is "ON" other than in the standby mode, and when the other operation switch is turned "ON", the process proceeds to a circle 2 in the figure.

On the other hand, if the mode is not the remote control mode, a timer is started and then a standby state is entered (step S).
116, 117). The standby state is released when the operation switch is pressed or the timer overflows, and the timer determines the repetition interval of the main routine. Further, when the standby state is released, a subroutine "switch processing" is executed (step S118), and a mode switching when a mode switch (not shown) is pressed or a zoom when the zoom switch is pressed. -Instruction to drive the motor is performed.

If the power drive flag is "ON", it is checked whether a predetermined time has elapsed since the power drive flag was turned "ON" (step S119). Is turned off (step S
120). The power drive flag is a flag for determining whether the temperature measurement circuit can be used. Further, the above-mentioned fixed time is a time for the chip to return to the ambient temperature. The above operation is repeated until the power switch is turned off.

In the present invention, since the chip is constituted by a CMOS analog circuit, the current consumption is basically small in each circuit, and therefore, the heat generation of the chip itself is small. And
Unlike the bipolar, the chip temperature does not rise, so that the temperature is the same as the ambient temperature no matter when the temperature is measured. However, when a power system such as a motor pre-driver is driven, the temperature of the chip rises because the current is required without any difference from the bipolar. Therefore, when the power system is driven, the power drive flag is turned on. The temperature is not measured while the power drive flag is "ON".

Next, referring to the flowchart of FIG.
The sequence of a subroutine "release interrupt" executed when the release switch is pressed or a remote control signal is received will be described in detail.

In this routine, first, the power drive flag is checked. If the flag is "off", the temperature is measured. If the flag is "on", the temperature of the IC itself is still high, and the temperature is not measured. Use temperature values. This temperature is used for correcting the temperature coefficient of the lens (steps S201 to S201).
203).

Subsequently, it is confirmed whether or not the photometry is being performed. If the photometry is being performed, a release time lag occurs, so the photometry is interrupted and the previous photometry value is used. And the main flow
Since the photometry is always performed, the value is used when the photometry is completed. That is, the photometry time is virtually zero (steps S204 and S205).

Then, it is determined whether or not a strobe is necessary (step S206). If a strobe is not required, charging is stopped, and the process proceeds to the next step S210. If the strobe is necessary, it is determined whether or not the charging is completed (step S208). If the charging is completed, the process proceeds to the next step S210. If the charging is not completed, an uncharged warning is issued. , And exits the interrupt (step S209).

Further, the distance to the subject is measured by the distance measuring circuit block 4 (step S210), and the remote control reception flag is confirmed (step S211). After the remote control mode is turned off, the sequence shifts to the shooting sequence (steps S212 to S217).

If no remote control is received,
Check whether the second release is on / off (step S21).
5) Wait until the second release is turned on.
At this time, the 2nd release does not turn on and the release
When the power switch is turned off, the CPU exits the interrupt (step S216).

Further, in the photographing sequence in step S217, first, the focus lens is driven to the focus position. Subsequently, the shutter is driven, the film is wound up, and the motor is moved, so that the power drive flag is turned "ON", the interruption is exited (steps S217 to S221), and the process returns to the main routine.

Next, referring to FIG.
The sequence of “CD ON” will be described in detail.

In this routine, first, the power drive flag is checked (step S301), and the flag is turned off.
Then, after measuring the temperature, the drive voltage of the LCD 21 is set (steps S302, S303). In the present embodiment, the drive voltage of the LCD 21 is set in the range shown in FIG. 5 so that the display density does not change even if the temperature changes. Subsequently, when the power drive flag is “ON”,
The previously set voltage is maintained without setting the drive voltage of the LCD 21. After displaying the number of film frames and the mode of the camera (step S304), the process returns to the main routine. Hereinafter, each circuit block of the camera controller using the CMOS analog circuit according to the first embodiment will be described in detail.

CMOS using only CMOS process
In an analog circuit, as one of the technologies enabling a large dynamic range and a division function as in a conventional analog circuit, there is a technology using a bipolar transistor which already exists in a CMOS process.

For example, FIG. 6 shows an NPN bipolar transistor and an NPN bipolar transistor existing in a CMOS process.
The configuration of the transistor is shown and described.

As shown in FIG. 7A, if the P ^- well is regarded as a base region, the N ⁺ inside the well is regarded as an emitter, and the N ^- substraight is regarded as a collector, the parasitic NPN
A bipolar transistor is created. However, the collector of this transistor is connected to the power supply line.

As shown in FIG. 3B, the N ^- well is a base region, the P ⁺ inside this well is an emitter,
Furthermore, P ^- Sabusutore - is regarded the door as the collector, the parasitic NPN Baipo - can La transistor. However, the collector of this transistor is connected to the GND line.

Therefore, by utilizing such a parasitic transistor in the CMOS process, even in a CMOS analog circuit only in the CMOS process,
As in the case of the conventional bipolar analog circuit, a large dynamic range and a division function can be realized.

FIG. 7 is a diagram showing a specific configuration of the distance measuring circuit block 4 using a parasitic NPN transistor in a CMOS process.

In the figure, the light emitting element is turned on by turning on the PMOS transistor 32 of the light emitting circuit section and turning on the external power transistor 33 by the light emitting signal P0 from the μ-com core 31. The pulse light emitted at 34 is condensed by the light projecting lens 35 and is irradiated toward the subject 36 located at the subject distance a.

The light reflected by the subject 36 passes through a light receiving lens 37 arranged at a base line distance S from the light projecting lens 35, and a semiconductor position detecting element arranged at the focal length fj. (Hereinafter abbreviated as PSD) 38.

Further, the signal light currents I1 and I2 output from both terminals of the PSD 38 are detected by signal light current detection circuits 39 and 39a described later.

As described above, the ranging circuit block 4 projects the light pulse on the object to be measured, and receives the reflected light from the object to detect the signal pulse light current component. It comprises signal light current detection circuits 39 and 39a for amplification, an operation circuit 40 for obtaining distance information of a subject from the detected photocurrent, and a count circuit 41 for A / D converting the output of the operation circuit 40. I have. Since the same components are used for the signal light current detection circuits 39 and 39a and have the same configuration, only the signal light current detection circuit 39 will be described, and the same numbers are assigned to the same components 39a. a "is attached and the description is omitted.

The IRED 34 of the light emitting circuit is driven by a transistor 33. The on / off of the external power transistor 33 is determined by the μ-com core 3
PMOS transistor 3 configured in the same chip as 1
2.

It should be noted here that the PMOS transistor 32 needs to supply a drive current of several tens of mA, so that Vcc1 is used as the source power source and the μ-co
That is, it is configured to be a power system power supply of a different system from the power supply Vcc2 of the other circuit blocks including the m core 31.
As described above, the power supply system is connected to the power system power supply Vcc in the chip.
1 and the stabilized power supply Vcc2 By using at least two power supplies, it is possible to prevent power supply fluctuations during large current drive from adversely affecting the measurement / control circuit block. Further, on / off of the PMOS transistor 32 is controlled by a control terminal P0 of the μ-com core 31, and on / off of the infrared light projected from the IRED 34 in a pulse waveform is controlled by this terminal output signal.

On the other hand, the photocurrent detection circuit section 9 has a CMO
Based on S operational amplifier 42 and P well, N in P well
C with ⁺ as emitter and N ^- substrate as collector
A preamplifier circuit composed of a parasitic NPN transistor 43 existing in a MOS, and a CMOS operational amplifier 44
And a background light removing circuit composed of an NMOS transistor 45 and its peripheral circuit.

The signal pulse current I2 obtained from one channel of the PSD 38 is supplied to an operational amplifier 42 constituting a preamplifier circuit. This operational amplifier 42
The output terminal is connected to the emitter of the transistor 43, the inverting input terminal is used as a base, and the non-inverting input terminal is connected to a reference power supply Vre (not shown) so that feedback is applied by the transistor 13.
f1, respectively, whereby the base input resistance of the transistor 43 is equivalently reduced to about several KΩ.

Further, the output of the operational amplifier 44 constituting the background removing circuit is connected to the CMOS transmission gate 4.
6, the capacitor is connected to a capacitor formed inside the chip and the gate of the NMOS transistor 45 for extracting the background. When the transmission gate 46 is supplied with a high-level "H" signal at the terminal P1 of the .mu.
Feedback buckle of transistor 43, operational amplifier 44, transmission gate 46, transistor 45
The inverting terminal of the operational amplifier 44 is imaginary
As a result of the short-circuit operation of the operational amplifier 44 so that the reference voltage source output becomes Vref2 (not shown), a charge corresponding to the background light at this time is accumulated in the capacitor 47, and only the background light current component is the transistor 45. Is pulled out to the ground line.

By the feedback loop, VBE of the transistor 43 is given by the following equation. Vref1 and Vref2 are set so that VBE = 0.55V or so.

VBE = Vref1−Vref2 (1) In such a state, the emitter current is set sufficiently smaller than βN times the minimum value of the obtained signal light current I1, so that the error in the distance measurement is small. You need to keep it down to the level.
However, care must be taken if the size is too small, since a responsiveness problem occurs. A contrivance for this will be described later.

At the time of light emission, the transmission gate 46 is turned off, so that the above-described feedback loop is broken. However, the electric charge accumulated in the capacitor 47 causes the transistor 45 to generate the photocurrent due to the background light. GN
D, only the pulse light component of the photocurrent obtained from one channel of the PSD 38 excluding the photocurrent due to the background light is multiplied by βN by the transistor 413 and flows as βN × I2 as the emitter current. The emitter potential at that time is given by the following equation.

[0076]

(Equation 1) Similarly, at the time of light emission, the output of the operational amplifier 12A, that is, the emitter potential of the transistor 13A is expressed by the following equation.

[0077]

(Equation 2) The operation output circuit 40 includes resistors 49, 50, 51,
52 and a CMOS operational amplifier 53 constitute a subtraction circuit. By this subtraction circuit, the above (2), (3)
The voltage subtraction represented by the equation is performed, and the following voltage value is obtained as the output.

[0078]

[Equation 3] Since this output voltage value is a voltage proportional to the reciprocal 1 / a of the object distance a, the distance to the object can be obtained by obtaining the value. FIG. 8 shows the relationship between the output voltage and the reciprocal of the subject distance a.

Hereinafter, referring to the flowchart of FIG.
The sequence of distance measurement by the distance measurement circuit block 4 will be described. Here, the output voltage is set to S, and the average of outputs when 36 measurements are made to improve the S / N ratio is taken. Further, the P1 ON time was set to 400 μs, and the P0 ON time was set to 200 μs (steps S401 to S412).
Note that the set values “36 times” and “400
μs ”and“ 200 μs ”are merely examples, and the present invention is not limited thereto.

Next, FIG. 10 shows a photometric circuit block 1 using a parasitic NPN transistor in a CMOS process.
FIG. 3 is a diagram showing a specific configuration of No. 3;

As shown in the figure, a spot metering light receiving element Sp for measuring a subject luminance in a narrow area in the center of the photographing screen as a photometric element, and a measuring means for measuring a subject luminance in a wide area of the photographing screen. The average photometric element Av is used, and the photocurrents IAv and ISP are detected by a photometric circuit block 13 described later.

The photometric circuit is a parasitic NPN transistor 6 in a CMOS process in which IAv flows as an emitter current.
1, a parasitic NPN transistor 62 in a CMOS process in which ISp flows as an emitter current, a constant current source 63, a CMOS operational amplifier 64, a parasitic NPN transistor 65 in a CMOS process, and a reference voltage source Vref3 (not shown) proportional to temperature. Is composed of
(Saturation Current of Transistor) A T-proportional AD composed of a canceling reference voltage circuit, comparators 66 and 67 and a T-proportional DAC 68 for outputting a voltage output proportional to temperature.
And a converter 69. In such a configuration, the output potential a of the operational amplifier 64, that is, the reference voltage for Is cancellation is expressed by the following equation.

[0083]

(Equation 4) Therefore, the potential at point b is expressed by the following equation.

[0084]

(Equation 5) Similarly, the potential at the point c is expressed by the following equation.

[0085]

(Equation 6) Here, assuming that IAv = 2 ^m · Iref and Isp = 2 ^l · Iref, the potentials at points b and c are expressed by the following equations. VT ln (2) is a voltage of about 18 mV at 30 ° C., which is proportional to the temperature.

Vref3−VTln (2) · l (8) Vref3−VTln (2) · m + VTln (n) (9) Next, how the input range of the T-proportional AD converter is determined Or a specific design example. Here, for example, it is assumed that the photocurrent Isp by the spot photometric element changes in the range of 100 pA to 1 μA depending on the luminance of the subject.

Further, Iref = 10 μA, Vref3 = 180
mV (30 ° C.), b when Isp is 100 pA
The potential at the point is 480 mV (30 ° C.), and the potential at the point b when the Isp is 1 μA is 240 mV (30 ° C.).
° C).

On the other hand, in order to simplify the subsequent arithmetic processing, to reduce the photometric error due to the quantization error, and to increase the accuracy as much as possible, a configuration is adopted in which a sharp numerical value 8 count corresponds to one luminance step. It is assumed that the / D converter has 8 bits. Since the amount of change in the output of the photometric circuit per stage is 18 mV (30 ° C.), the voltage value per count is 18 mV / 8 = 2.2.
When a full bit set at 5 mV (30 ° C.) is set, the value becomes 255 × 2.25 mV = 573.75 mV (30 ° C.).

On the other hand, the area of the photometric range of the average photometric element is about 16 times the area of the photometric range of the spot photometric element, and the photocurrent IAv is 1600 pA to 16 μA depending on the luminance of the object.
Range. Therefore, the number n of NPN Tr becomes “n−
If it is 1 ", the potential at point a is 408 mV (30 ° C.) when IAv is 1600 pA, and the potential at point a is 168 mV (30 ° C.) when IAv is 16 μA.

As described above, the photocurrents Isp and IAv have different photoelectric flow rates with respect to the same luminance. Therefore, if the photometric circuits are the same, the output voltages thereof differ, and the input voltage of the subsequent A / D converter is increased. It is necessary to increase the range. Therefore, in this embodiment, n is set to “16” so that the average and the output voltage of the photometric circuit of the spot have the same voltage value at the same luminance.

As described above, the photometric output voltage values at the same luminance can be made equal by setting the emitter size ratio of the NPN transistor equal to the light current ratio between the average and the spot at the same luminance. Then, even if they are not exactly the same, they are set to substantially similar values, so that A
Since the design can be performed without unnecessarily increasing the input voltage range of the D conversion circuit, an increase in circuit scale can be suppressed.

Here, in order to make photometric output voltages from photometric elements having different photocurrent ratios at the same luminance substantially equal,
With the circuit shown in FIG. 11, the output Is of the reference voltage circuit can be made different between the average and the spot in advance.

For example, if IAv / Isp = 16, Vref3A = Vref3 + 18 mA (30.degree. C.). Times.ln (16) / ln (2) (10) or IrefA = Iref.times.16 (11) Just do it. In addition, adjustment may be made by adding a level shift circuit as shown in FIG.
(30 ° C.) × ln (IAv / Isp) / ln (2).

The obtained potentials at the photometric voltage values b and c are A / D-converted by the T-proportional ADC 69, converted into digital values, taken into the μ-com core, and arithmetically converted into subject brightness information. Stored in memory.

The T-proportional ADC 69 comprises a D / A converter composed of a dividing resistor and a tap decoder and comparators 66 and 67. When a command is sent from the μ-com core to the tap decoder, One of the potentials of the taps of the dividing resistor is input to one terminal of the comparators 66 and 67. The μ-com core can A / D convert the photometric output voltage value by repeatedly comparing each set voltage of the D / A converter with the photometric output voltage.

Further, a current proportional to the temperature T of VT In (N / R0) (N is a positive integer, R0 is a resistance inside the circuit) is passed through the divided resistor by the constant current source 70, It is configured to generate a voltage proportional to T. still,
In addition to the constant current source 70A stable against the temperature T above T proportional constant current source 70 of this is configured to be switched together by switching from mu-com core, further A / D converter 69 is T proportional, T stable A / D
It is configured to be used as a converter. The T-stable A / D converter is used for A / D conversion of another information amount (for example, temperature, strobe charge voltage, etc.) of the camera.

[0097] In the above manner, as a whole of the circuit scale of
It is configured to improve the reduction .

Further, the photometric value is subjected to A / D conversion to obtain μ-co.
Although it can be taken into the m core, when a CMOS operational amplifier is used, the offset voltage becomes a problem unlike the conventional bipolar operational amplifier. That is, while the voltage is only 2-3 mV in the conventional operational amplifier, it is about 20 mV in the CMOS operational amplifier. 18 brightness per step
Since it is mV (30 ° C.), the offset voltage of the CMOS operational amplifier is not negligible.

In order to solve this problem, in the embodiment shown in FIG. 10, the CMOS operational amplifier 64 and the CMOS comparator 66 have substantially the same configuration as shown in FIG. 13, and are arranged as close as possible in the same chip. by doing,
An offset voltage in the same direction is generated so as to cancel each other. FIG. 14 is a diagram showing a specific configuration of a circuit for generating a T-stable and T-proportional reference current for a D / A converter, and is used as a bias current source for a camera measurement circuit in addition to the above.

Hereinafter, the photometry sequence by the photometry circuit block 13 will be described in detail with reference to the flowchart of FIG.

In this sequence, the spot average is measured by measuring the potentials at the points b and c, respectively. What is necessary is to perform A / D conversion on this potential. Here, a comparator and tap deco
A description will be given as an A / D system using an A / D converter using a digital converter, and only one of the processes will be described since the spot averaging process is the same.

First, VH is set to Vcc2, and VL is set to a value corresponding to GND, and the output of the comparator is checked.
If the value of the comparator is at the high level "H", the value of the tap decoder is lower, so that the value of VL is (VH + VL) /
Substitute 2. Furthermore, if the output of the comparator is low level “L”, the value of the tap decoder is higher, so VH
Is substituted for (VH + VL) / 2. Hereinafter, when this is repeated eight times, A / D conversion of 8 bits is performed, and the output of photometry is A / D converted (steps S501 to S50).
8).

Next, FIG. 16 is a diagram showing a configuration of the temperature measuring circuit block 10 in a CMOS process. The temperature measuring object to be measured by the temperature measuring circuit block 10 is a CMOS.
This is the temperature of the microcomputer chip itself. Since this CMOS can reduce the power consumption of the microcomputer section and the various measurement circuits for the camera such as photometry, distance measurement, temperature measurement, etc., all at very low power, IC
The power consumption of the chip itself is much smaller than that of a bipolar integrated circuit.

Normally, in the case of a bipolar integrated circuit, the temperature of the IC chip itself is 3 ° C. due to its power consumption.
The temperature rises with respect to the ambient temperature. Further, since the degree of the rise differs depending on the timing from when power is supplied to the IC to when the temperature is measured, a variation of about 3 ° C. always occurs due to the temperature measurement timing, so that accurate camera temperature correction cannot be performed. On the other hand, CMOS has a small difference between the temperature of the chip itself and the environmental temperature due to inherent low power consumption.

Further, conventionally, in the above-described bipolar, taking into account heat generation due to the power consumption of the chip itself, for example, a single function of a measuring circuit of a camera such as a photometric circuit chip, a distance measuring circuit chip, a remote control receiving circuit chip, etc. Alternatively, a temperature measurement circuit is incorporated in an IC chip having only a few functions to measure such an IC chip temperature.

On the other hand, by using CMOS, various measuring circuits for cameras are integrated on a large scale.
A temperature measuring circuit can be provided in the C chip, and an all-in-one IC suitable for a camera can be designed.
Such a microcomputer contributes to further downsizing and cost reduction of the camera.

Then, as shown in FIG. 16, the temperature measuring circuit block 10 of the present embodiment comprises MOS transistors Q1 to Q
8, a temperature-proportional reference current circuit including a resistor R1, a resistor R2, and a circuit starting constant current source I1, a parasitic NPN Tr Q9, a resistor R3, a CMOS operational amplifier OP1, a CMOS transistor Q10, and a resistor R4 which exist in a CMOS process. It comprises a temperature stable reference current circuit and a resistor R5.

Here, in the temperature proportional type reference current circuit, the area ratio between Q5 and Q4 is set to 1:16.
According to this relationship, Iref1 becomes a current value represented by the following equation.

Iref1 = (VT In16) / R2 (12) This VT is a thermal voltage and is proportional to the temperature.
26 mV (30 ° C.). The resistance value of R3 is selected so that Iref1 flows through Q9 and R3 so that the + terminal potential of the operational amplifier becomes 1.26 V with respect to Vcc2. Further, this 1.26V is called a bandgap reference voltage and shows very good temperature stability.

Then, based on this voltage, the temperature stable reference current Iref2 output from the source of Q10 is expressed by the following equation.

Iref2 = 1.26V / R4 (13) Accordingly, the voltage VTEMP generated at the resistor R5 is expressed by the following equation.

[0112]

(Equation 7) Here, R2 = 1KΩ, R4 = 15KΩ, R5 = 28K
Ω,

[0113]

(Equation 8) VTEMP is 269 mV at 40 ° C. and 605 mV at −10 ° C.

The amount of voltage change per 1 ° C. was 6.72 m.
V.

On the other hand, when the input voltage range of the A / D conversion circuit section 9 is set to 0 to 856.8 mV and set to 3.36 mV per count, measurement is performed with a temperature measuring accuracy of 0.5 ° C. per count. A / D conversion of the warm voltage value is possible. A at this time
The / D conversion circuit is, of course, stable with respect to temperature.
Further, the relationship between the obtained A / D conversion digital value and the temperature corresponds to the difference between the theoretical value and the actual value of the A / D conversion value obtained in advance at the reference temperature by the μ-com core. After correcting the digital amount stored as the amount, the digital amount is compared with a reference value for temperature to obtain the value.

Next, FIG. 17 shows not only various measuring circuits for a camera which can basically reduce power consumption by using CMOS but also an external drive which cannot basically reduce power consumption. Circuit block, eg motor
FIG. 3 is a diagram illustrating a specific example of a configuration in which a drive circuit, a booster circuit, a plunger drive circuit, and the like are incorporated.

In the case where a power control circuit is incorporated as shown in the figure, when a motor is driven at the time of film winding or rewinding in terms of a camera, several tens to several hundreds of meters are required.
The current A flows for 1 to 30 seconds, and the temperature of the IC chip rises to about 60 to 70 ° C. at the peak, and it takes several minutes for it to drop to a temperature close to the ambient temperature. . For this reason, if the temperature of the operation of the camera is corrected again using the temperature of the IC chip itself, there occurs a problem that the temperature correction is not completely accurate.

Here, in order to solve the above-mentioned problem, a time measuring circuit 81 is provided together with the temperature measuring circuit 80, and after a power system control circuit such as a motor drive circuit 83 or a step-up circuit 86 is operated. The configuration is such that the temperature data of the temperature measuring circuit 80 until the temperature rise of the IC chip disappears is not used as the temperature correction data of the camera. This has already described the method using the power drive flag in the main flow or the like. The power drive flag MT
FLG is MTFLG1, MFLG depending on the load condition and drive condition.
Two or more types such as TFLG2 may be provided.

FIG. 18 is a circuit diagram showing the configuration of a remote control receiving circuit block of the camera. FIG. 19 shows the operation waveform of each unit when the receiving unit receives a remote control signal by infrared light. FIG.

The photodiode 90 is a light receiving element for receiving the remote control signals A1, A2 and A3 shown in FIG. Preamplifier 93
Amplifies the input small signal voltage to the preamplifier output 100 shown in FIG.
(BPF; Band Pass Filter) 94.

The BPF 94 has a filter characteristic set so that the carrier frequency fc of the remote control signal is at the center of the pass band, and has a ripple frequency (100 Hz and 120 Hz) twice the commercial frequency of a fluorescent lamp or the like. FIG. 19 which consists of only the remote control signal by removing the noise component of FIG.
The BPF output 101 shown in (c) is output to the detection circuit 95 at the next stage. Further, the integration circuit 96 detects the detection output 10
An integral output 103 shown in FIG. 19E is output after integrating 2 to remove the carrier component. The waveform shaping circuit 97
Has hysteresis of threshold levels VTH1 and VTH2, performs waveform shaping, and outputs signal pulses P1, P2, P2.
3 as the light receiving circuit output shown in FIG.
U (μ-com core) 91 is output.

Each circuit block of the receiving means in the remote control device is constituted by CMOS, and 200 to 300 mA for the conventional bipolar power consumption of 2 to 3 mA.
It is reduced to 1/10 or less of μA. For this reason, the continuation time of the remote control mode is conventionally limited to about 20 minutes by measures against battery consumption, but can be extended to about 200 minutes (= 3 hours 20 minutes) which is ten times as long. This is practically sufficient time, and it is not necessary to provide a time limiter dedicated to a remote controller as in the related art. Therefore, in the main flow described above, no time limit is set in the remote control mode.

Hereinafter, the processing operation of the remote control reception signal output by the remote control circuit block 9 by the μ-com core and the control of the remote control circuit block 9 will be described in detail. The μ-com core detects “ON” of a remote control mode setting switch provided on the camera body, displays “mode display” indicating that the remote control mode is active on an LCD (not shown), and a remote control interrupt terminal. After prohibiting RNINT, the remote control enable terminal RMEN is set to low level “L” to supply power to the remote control receiving circuit block. After this power supply, the remote control interrupt terminal R is given a predetermined time after the remote control receiving circuit block is stabilized.
Enables NINT interrupt. Further, the μ-co
When the output of the light receiving circuit is input, the m-core reads the input signal according to a program stored in a ROM therein and determines whether or not the signal is a remote control signal.

First, referring to the flowchart of FIG.
A sequence until the μ-com core receives the remote control signal and determines the signal will be described.

When a remote control reception interrupt is applied to the μ-com core by the input signal pulse P1, the internal timer 1
And the timer 1 is stopped by the input of the next signal pulse P2. As a result, the signal pulses P1 and P1
The pulse interval of the signal pulse P2 and P3 is measured by a timer, and if it coincides, the pulse interval of the signal pulses P2 and P3 is similarly measured by a timer.
By determining whether or not the time is equal to the predetermined time T1 (steps S602 to S607), the remote control signal is determined. If they match, the remote control reception flag is turned "ON" (step S608), and after interrupting the remote control interrupt, the process exits the interrupt process.

If the pulse interval does not coincide with the predetermined time T1, it is determined that the noise is noise, the noise is ignored, and the process exits from the interrupt processing (step S609). The predetermined pulse interval T1 is 10 msec between the periodic noise pulses of the fluorescent lamp.
The time interval is not synchronized with c or an integral multiple of 8.3 msec.

When the μ-com core determines that the received signal is a remote control reception signal as described above, the process shifts to release interrupt processing, and distance measurement, photometry, temperature measurement, focus lens drive, and shutter drive film winding are performed. Continue the camera sequence.

Next, points to be noted when incorporating the operation processing of the remote control receiving circuit into the operation sequence of the camera will be described.

The remote control receiving circuit has a very weak number 10
Since the detection circuit detects a μV signal, it is easily affected by noise. Therefore, when the boosting circuit is operating, that is, when the boosting circuit is formed on the same chip as the remote control receiving circuit or when strobe charging is operating, the remote control receiving There is a fear that interrupts will occur regularly and normal camera operation will not be performed.

In order to solve this problem, in this embodiment,
As shown in the flowchart of FIG. 21, Rimokonmo - de
In the signal reception standby state , the booster circuit operation is prohibited. During the strobe charge, the remote control receiving circuit is disabled or the remote control receiving interrupt is prohibited. In the present invention, the remote control mode is devised after the flash charging is completed as shown in the main flow. This prevents an erroneous signal output from the remote control receiving circuit from hindering the normal operation of the camera (steps S701 to S707).

Next, FIG. 22 shows a specific configuration of the NPN motor pre-driver circuit block 5 when a motor driver pre-driver circuit is formed on the same chip as the CPU and various measurement circuits of the camera. FIG.

Normally, a power supply Vcc2 stabilized by a diode filter (D1, C1) composed of a Shottky barrier diode and a tantalum capacitor of about 33 μF is used as a power supply for various measurement circuits of the CPU and the camera. Is used.

This is because the battery voltage causes a sharp and large voltage drop due to a heavy load drive such as a motor drive, a plunger drive, a boost coil drive or a strobe charge.
The size (dv / dt) of which the dv / dt cannot guarantee the normal sequence of the CPU or the accurate measurement of various measurement circuits (dv)
/ Dt) 0 or more.

Therefore, the normal backup capacitor C1
Is set to a value represented by the following equation, assuming the consumption current Idi of the IC inside Vcc2.

[0135]

(Equation 9) Further, as a major problem, since the camera is a portable device, the battery is separated from the battery contact piece due to the vibration, and the ground fault is temporarily interrupted. In particular, if the above-mentioned problem occurs during the operation of the camera and the Vcc2 voltage drops below the operable level of the CPU, normal camera control by the CPU is not performed, and in the worst case, the camera is destroyed.
The chattering of this battery is considered to be about 10 msec depending on the shape and pressure of the battery contact piece. Therefore, the capacitor C
The value is set to a value such that the time Vcc2 does not drop below the normal operable voltage of the CPU.

Normally, the dominant parameter for determining the capacity of the capacitor C1 is Vcc during the battery chattering.
2 Voltage holding. For this capacitor C1, a tantalum capacitor is used because it has good frequency characteristics and it is easy to obtain a relatively large capacity. However, this is expensive and also has a large volume for a small camera mounting space. , Vcc2, the current consumption Idi of the IC must be designed to be small.

For this purpose, it is necessary to design the various measuring circuits of the camera so that they consume as little current as possible. On the other hand, a circuit for driving an external power transistor such as a motor pre-drive circuit needs to supply a current of several tens mA as its base current. When such a circuit is formed on the same chip as the CPU chip in the same manner as the camera measurement circuit, if the power supply of the circuit block is made common to the same Vcc2 as the CPU and the measurement circuit, Vcc2 is used for the above-described reason. The capacity of the holding capacitor must be very large. Actually, the above configuration is impossible in terms of cost and space.

Therefore, in this embodiment, the source current source is Vcc2
Instead, a large current supply terminal and a line are provided on the IC so that a large current is not emitted from the power stabilizing capacitor C1 to the outside of the IC as Vcc1. IC including microcomputer
48, as shown in FIG.
An IC lead 201 connecting the C205 to the battery protrudes from the package 204, and the IC lead 201 is connected to a pad 203 on the IC 205 by a gold wire 206.

Here, when a large current flows through the GND line 202 of the IC 205,
2 is 0.2 to 3Ω and the pad 203 and I
The contact resistance with the C-lead 201 has a value of 0.2 to 3Ω, and a potential difference of about 50 to 100 mV is generated along the path through which the large current flows. When the line 202 is shared with the above circuit block and the CPU and the camera measurement circuit block, a normal
Kens, accurate measurement becomes impossible.

In this embodiment, an MTGND line for discharging a large current to GND and a dedicated G for the camera measurement circuit block are used.
In order to provide at least two GND lines of the ND line and to prevent the influence of the contact resistance of the pads, terminals consisting of at least two GND pads MTGND terminal, ANGN
A D terminal is provided.

As described above, by providing at least two lines of GND lines and GND terminals, it is possible to configure the large current drive circuit block on one chip. Ideally, it is better to separately provide the digital GND for the CPU and the analog GND for the measuring circuit. However, since this actually leads to an unnecessary increase in the number of terminals, the present embodiment dares to combine them. . However, in this case, one point ground
It is necessary to devise the wiring such that

Next, a specific configuration of the pre-drive circuit will be described.

First, an N terminal constant current drive circuit for driving an external NPN power transistor will be described.

This N terminal constant current drive circuit is a CMO
Resistance S operational amplifier OP1 R1, R2, R3 and the reference voltage Vref3 and P MOS composed of transistors Q1 P MOS transistor constant current drive voltage generating circuit, the voltage PMOS transistors Q2, Q3, Q4, Q5 of the gate -
Transfer gate switches SW1 and SW2
, SW3, SW4 and Vcc1 as sources, external NP
PMOS transistors Q2, Q3, Q4, Q5 having the drain of the base of the N transistor, and shunt resistors R4, R5, R6, shunting between their gate sources.
NMOS transistors Q6 and Q6 which shunt between R7 and the base-emitter of the external NPN power transistor
7, Q8 and Q9.

When a power supply signal is input from the port N0 of the μ-com core to the operational amplifier OP1, the operational amplifier operates and a current IN0 of 100 μA flows through the resistor R3. This IN0 is expressed by the following equation.

IN0 = Vref3 / R3 (17) Then, the following relationship is established between VGS of transistor Q1 and IN0.

IN0 = A · (VGS−Vth) ² (18) A: proportional constant, Vth: threshold voltage. Based on Vcc1, potential Va at point a is expressed by the following equation.

[0148]

(Equation 10) Further, when the output port N1 of the .mu.-com core becomes high level "H" and the transfer gate switch SW1 is turned "on", the GS voltage of Q2 is 0V and Q2 is off. , Q6 are on, but Va voltage is applied and Q2 is on, and Q6 is off. At this time, the output current IN1 is expressed by the following equation.

IN1 = A · (VGS1−Vth) ² (20) Then, the above (R1 + R2) / R2 is set by the following equation so that VGS1 becomes such that IN1 = 20 mA.

[0150]

(Equation 11) With the above circuit configuration, each output port N
A constant current of 20 mA can be output from 1, N2, N3 and N4, and there is no need to use a base limiting resistor as in the prior art.
A pre-drive circuit with a small mounting area can be obtained.

Further, since the fluctuation of Vcc1 is fed back, no matter how the Vcc1 voltage fluctuates, it is always 20 m.
A drive can be performed, and stable actuator control can be performed without being affected by the power supply voltage.

Next, a description will be given of a P terminal constant current drive circuit for driving an external PNP power transistor. This is the same operation principle as that of the N-terminal constant current drive circuit described above, and there is only a difference between a source and a sink.

The P terminal constant current drive circuit includes a CMOS operational amplifier OP1A, resistors R1A, R2A, R3A and a reference voltage Vre.
N MO consists of f3A and N MOS transistor Q1A
And S transistor constant current drive voltage generating circuit, the voltage N MOS transistors Q2A, Q3A, Q4A, Q5A
And shunt resistors R4A, R5A, R6A, R7A for shunting between their gate and source, and PMOS transistors Q6A, Q7A, Q8A, Q9A for shunting between the base and emitter of the external PNP transistor. And an output unit.

Then, when a power supply signal is input from the port P0 of the μ-com core to the operational amplifier OP1A, the operational amplifier is operated and a current Ip0 of 100 μA flows through the resistor R3A.

The current Ip0 is expressed by the following equation.

Ip0 = (Vref3A-Vcc1) / R3A (22) Further, the following equation holds between VGS of the transistor Q1 and Ip0.

Ip0 = B · (VGS−Vth) ² (23) B: proportional constant, Vth: threshold voltage, the potential VaA at point a on the basis of GND is represented by the following equation.

[0158]

(Equation 12) Further, the output port P1 of the μ-com core becomes high level "H" and the transfer gate switch SW1A
Is turned on, the GS voltage of the transistor Q2A is 0 V, the transistor Q2A is off, the transistor Q6A is on, the VaA voltage is applied, the transistor Q2A is on, and the transistor Q6A is on. Is turned off.

At this time, the output current IP1 is expressed by the following equation.

IP1 = B ・ (VGS1−Vth) ² (25) Then, the above (R1A + R2A) / R2A is set by the following equation so that VGS1 becomes IP1 = 20 mA.

[0161]

(Equation 13) With the above circuit configuration, P1, P2
, P3 and P4 can sink a constant current of 20 mA.

FIG. 23 is a diagram showing a specific configuration of an analog timer circuit that does not use a clock. As shown in the figure, a timer 118a includes MOS transistors 111 and 112 constituting a current mirror circuit and a constant current source 1
14, a MOS transistor 113 for switching the current of the constant current source, a capacitor 115 for integrating the current of the constant current source, a MOS transistor 116 for discharging the charge stored in the integration capacitor, and a DAC for storing the amount of charge stored in the capacitor. It comprises a comparator 117 for comparing the output and a timer 118a.

The timer 118b operates as a timer 118a.
By changing the value of the tap decoder, two timer values can be set, and furthermore, they can be used continuously. By changing the value of the constant current source, a long timer or a short timer can be made.

Hereinafter, the operation of the analog timer circuit will be described with reference to the flowchart of FIG. The timer value is set based on the graph of FIG. When the capacitor in the integrated circuit is used, the temperature characteristic is small, but when there is a temperature characteristic, the graph may be selected according to the temperature. Further, here, a description will be given assuming that there is a temperature characteristic.

First, the temperature is measured (step S801), and the output (D / A value) of the tap decoder is set from FIG. 27 so as to become the timer value T or TA set before calling the analog timer (step S802). ). Then, TM1 or T
M1A is turned on, and the charge of the capacitor 115 or 115A is discharged. At the same time, turn on TM2 or TM2A
Then, the capacitor can be charged, and TM1 or T
After turning off the M1A and starting the timer, the original vibration is stopped (steps S803 and S804).

Thereafter, when the level of the capacitor 115 or 115A exceeds the output of the tap decoder, TM3
Alternatively, TM3A rises, and this signal causes μ-co
m wakes up and the original vibration starts (returns from the clock pause state to the oscillation state). Immediately after the original vibration starts, TM2 or TM2A is turned off, the charge is stopped, and the process returns to the main routine (steps S805 to S805).
8).

The timing chart in this state is as shown in FIG. 25. In addition to the method shown in FIG. 25, various methods such as the method shown in FIG. 26 can be considered, but the timing shown in FIG. Let's continue with the explanation.

As is clear from the above description, the original oscillation of μ-com can be stopped during the operation of the analog timer, so that it can be applied to the measurement of a minute current or a minute voltage or the time measurement of a signal susceptible to noise. can do.

Next, FIG. 28 is a diagram showing a specific configuration of a photometric circuit using an analog timer. Here, the difference from the photometric circuit shown in FIG. 10 is that a flip-flop is provided after the comparator. The flip-flop latches the level of the comparator in response to the analog timer stop signal.

FIG. 29 is a flowchart showing the operation of the photometric circuit.

The difference from the operation shown in FIG.
That is, steps S904 and S905 are newly provided to use the analog timer. In other words, if the photometric voltage is very small, the noise of the original vibration is superimposed on it, and accurate A / D conversion cannot be performed. Therefore, when checking the output of the comparator, the original oscillation is stopped and the measurement is performed without noise. Is taking the method. Since the output of the comparator is latched by the analog timer end signal, when the original oscillation oscillates, the level without noise is already latched. Other operations are the same as those described above with reference to FIG.

FIG. 30 is a diagram showing a specific configuration of a distance measuring circuit using an analog timer. This distance measuring circuit is an improvement of the A / D unit 41 shown in FIG.

That is, as in the case of the photometry in FIG. 7, when the stationary light is latched by the capacitor 47,
When calculating the output of the SD 38, an analog timer is used to remove original vibration noise. Then, the calculation result is held in the capacitor by the end signal TM3 of the analog timer. After that, A / D conversion is performed, so that a signal without noise of the original vibration can be A / D converted.

FIG. 31 is a flowchart showing the operation of the distance measuring circuit. The only difference from the operation shown in FIG. 9 is that an analog timer is used (steps S1003 to S1011). The other operations are the same as those described above with reference to FIG.

FIG. 32 is a diagram showing a specific configuration of a circuit in which an analog timer is applied to evaluation of a remote control received signal. The purpose of this circuit is also to remove noise due to the original vibration. In this case, two timers are used.

FIG. 34 is a flowchart showing the operation of such a circuit. The normal remote control signal is shown in FIG.
Assume that there are three pulses at T1 intervals as shown in FIG. This T1 is OK up to an error of T1 ± α. Then, this circuit determines whether the analog timer reaches the set timer value or the remote control reception signal falls.
The T2 signal is generated to stop the timer.

That is, FIG. 33A shows the output of the remote control light receiving circuit when the remote control signal is advanced. In this case, the timer value is set to T1 + α. That is, if T3 becomes high level "H" before a remote control signal is input, T≥T1
+ Α and NG.

On the other hand, FIG. 33B shows the output of the remote control light-receiving circuit when the set time comes earlier. In this case, since the analog timer is stopped, the time can be known by performing A / D conversion. Therefore, it is determined whether or not the signal is normal based on whether it is greater than T1 -α. This determination is made immediately after the end of the timer 1 to start the timer 2 and after the end of the timer 2, and if OK, sets the remote control reception flag and exits the interrupt.

Next, the CMO according to the second embodiment of the present invention will be described.
A camera controller using an S analog circuit will be described. 35 and 36 are diagrams showing the configuration.

First, the reference current circuit block 201 in FIG. 36 will be described.

This reference current circuit block 201
OS transistors Q1, Q2, Q3, Q7, Q8, NM
OS transistors Q4, Q5, Q6 and resistors R1, R2
, R3. When PT0 is set to "L" by the CPU, a current of several .mu.A limited by the resistor R1 flows through the transistor Q1, and the transistors Q1 and Q2 constitute a current mirror circuit. The current is transistor Q
4 flows into the DG short circuit. Since the transistors Q4, Q5 and Q6 each constitute a current mirror circuit, the same drain current flows through the transistors Q5 and Q6.

Incidentally, the transistors Q8 and Q7 are the same as the 10: 1 current mirror circuit in the minute current region (because the voltage drop due to the resistor R3 is small), and the drain current of the transistor Q7 is equal to the drain current of the transistor Q6. Therefore, the potential at the point A becomes low level "L", the PMOS transistor Q3 is turned "on" and the drain current flows, the drain current of the transistor Q4 increases, and the transistors Q5 and Q6 are turned on by the current mirror. Drain current increases.

When this current increases, transistors Q7,
The drain current ratio of Q8 approaches "1" from 1/10 because the voltage drop of the resistor R3 is effective.

In the above cycle, as a result, the drain currents of the transistors Q5 and Q7 converge at a point where they coincide with each other. As a result, the voltage drop of the resistor R3 is expressed by the following equation.
In the following equation, VT indicates a thermal voltage.

[0185]

[Equation 14] However, MOS is a weak inversion region, ID
Used at about 200 nA.

Next, the bandgap reference voltage circuit block 203 will be described.

The circuit block 203 is a 1.26 V constant voltage circuit that is stable with respect to temperature. Then, a band gap reference voltage based on the Vcc2 potential is obtained by the NPN parasitic transistor Q13, NMOS transistor Q12 and resistor R5 based on the P well in the CMOS process.
Further, the transistor Q13 has a diode characteristic of -2 mV / ° C., and the voltage across the resistor RS generates a voltage which changes by + with respect to the temperature change of the following equation.

VT ln (10) × (R5 / R3) × 10 (28) Then, the equation (28) is changed so that the amounts of change of plus (+) and minus (−) are almost equal to cancel each other. RS /
If R3) is designed, the voltage between VCC2-B becomes stable with respect to temperature. As a guide, the voltage value is 1.26V.
Conversely, although an NPN transistor is used, when a parasitic PNP transistor based on an N well is used, GND is used.
A reference voltage of 1.26V can be made by reference.

Next, the temperature stable reference current circuit block 20
4 will be described.

This circuit block 204 comprises an operational amplifier OP
1 and PMOS transistors Q14 and Q15 and resistors R6 and R7
It is constituted by. Then, the transistors Q14 and Q15 are turned on by the operational amplifier OP1, and the resistance R6
And a source current flows through R7, and the potential at point C becomes equal to the potential at point B due to an imaginary short. Therefore, a current of 1.26 / (R6 + R7) flows through the resistors R6 and R7, and half of the drain current flows through the transistors Q15 and Q14.

Next, the temperature measurement circuit block 202 will be described.

The temperature measuring circuit block 202 comprises a PMOS transistor Q10, a resistor R4, and an NMOS transistor Q11.
It is composed of

Then, the drain current of the transistor Q10 is expressed by the following equation.

[0194]         VT ln (10) / R3 × 40 (29) Therefore, the voltage VT is expressed by the following equation.

[0195]         VT = ((273 + T) / 300) × 26 mV (30) Here, T indicates a temperature (° C.).

Transistor Q11 is connected to transistors Q16 and Q16.
17 and a current mirror circuit, and the current mirror circuit includes the temperature stable reference current circuit block 20.
4, the current shown by the following equation is injected.

1.26V / (R6 + R7) / 2 (31) The drain current of the transistor Q11 has the above current value.
The remainder obtained by subtracting the T stable current from the T proportional current value flows into the resistor R4.

Therefore, the E current is expressed by the following equation.

[0199]

(Equation 15) Therefore, at -10 ° C, VE = 281mV, + 40 ° C
In this case, VE = 456 mV.

Next, the capacitor charge / discharge circuit block 20
5 will be described.

This circuit block 205 is for A / D conversion of the voltage of the strobe main capacitor, the battery voltage, the voltage related to the temperature, and the like. The NMOS transistors Q16 and Q1
7, Q18, Q22, PMOS transistors Q19, Q20, and a capacitor C1. When the CPU port PT2 = "H", the transistor Q18 is turned "on".
Since the transistors Q16, Q17, Q19 and Q20 each constitute a current mirror circuit, the drain current of the transistor Q20 is expressed by the following equation.

1.26V / (R6 + R7) / 20 (34) When the CPU port PT4 is “H”, the transistor Q22 is turned “ON”, the capacitor C1 is discharged, and the potential at the point F becomes 0V. .

Further, CPU port PT4 = "L", P
When T2 = "H", the capacitor C1 is charged by the drain current of the transistor Q20, and the potential of F rises with time. PT4 = "L", PT2
= "L", the potential at the F point is fixed to the potential at that time.

Next, the operation of A / D converting the battery voltage will be described in detail with reference to the flowchart of FIG.

First, it is assumed that the reference current circuit is operated with PT0 = “L” and PT1 = “L”. A / D
The memory ADM storing the converted value is set to “0” (step S1201). I is set to "0" (step S1202). The CPU ports PT4 and PT2 are both set to the high level "H", and the switching NMOS transistors of the transistors Q18 and Q22 are turned "on" (step S1203).

Then, after waiting for 1 msec (step S12)
04), when the CPU port PT4 is set to low level "L" to turn off the transistor Q22, charging of the capacitor C1 is started (step S1205).

Subsequently, timer counting is started. This timer may be a software soft timer,
A hardware counter incorporated in the CPU may be used.
For a soft timer, about 16 to 32 KHz is appropriate depending on the resolution required for A / D conversion of the camera and the limitation of the measurement time. The faster the hardware, the better (step S1206).

Subsequently, it is detected whether or not the input port PT6 of the CPU is at the high level "H". When the high level is set to "H", the flow advances to step S1208 to add the current timer value to the contents of the memory ADM (step S1207). Then, it is checked whether or not I = 3. If “3”, the content of the ADM is reduced to １ ／ in step S1211 and the process returns in step S1212 (step S1209). Then, step S1209
If I is not 3 in step S1210, I is incremented in step S1210, and the process returns to step S1203.

As described above, the average of the four A / D conversion values is stored in the memory ADM. Step S12
If it does not change for 100 msec or more in the judgment of 07, an interrupt is separately issued by an interrupt timer and the CPU
Displays a camera failure and stops all camera operations.

FIG. 39 shows that the strobe charging voltage is A /
5 is a flowchart illustrating an operation for performing D conversion. This sequence is the same as the above-described sequence of FIG. 37 except that PT7 is set to the high level “H” in step S1307, and thus redundant description is omitted here.

FIG. 41 is a flowchart showing the operation of A / D converting the measured voltage value. This sequence is the same as the above-described sequence of FIG. 37 except that PT5 is set to the high level “H” in step S1407, and thus the repeated description is omitted here.

Next, the operation of A / D converting the photometric value will be described in detail with reference to the flowchart in FIG.

The ADM is set to “0” (step S15)
01), I is set to “0” (step S1502). Then, the CPU port PT3 is set to low level “L”,
When the transistor Q21 is turned on, the capacitor C2
Is discharged, and the H potential becomes the same potential as VCC2 (step S1503).

Thereafter, waiting for 1 msec (step S15)
04), CPU port PT3 is set to high level “H”,
When the transistor Q21 is turned off, the capacitor C2 is charged by the photocurrent corresponding to the brightness by the SPD1 (step S1505).

Subsequently, timer counting is started (step S1506), and it is checked whether or not the CPU port PT8 is at the high level "H" (step S150).
7) If the high level is "H", the timer value is added to the contents of the ADM memory (step S1508). And I
= 3, and if it is not I = 3, I is incremented and the process returns to step S1503. If "3", the content of the ADM is reduced to 1/4 in step S1511 and the process returns in step S1512 (step S15).
09). Thus, the photometric value is A / D converted.

According to the sequence described above, the camera information necessary for operating the camera is A / D converted. Here, the A / D conversion method using the VT conversion generally has a problem that it takes too much time as compared with other A / D conversion methods.
This usually means that the time from when the release button is pressed to when the film is exposed must be about 0.3 seconds. If you are too slow, you miss a photo opportunity. From the above viewpoint, at least the photometric A / D, the strobe charging voltage A / D, and the battery voltage A / D are required for each release.
3 seconds / 3 = 0.1 seconds, that is, the time required for one AD should be at least 100 msec or less. In this embodiment, the value of C1 and the value of the charge current to C1 are appropriately set so that one A / D is designed to be about 10 msec.

For this, the following ideas can be further considered. That is, first, A / D conversion of at least two or more pieces of camera information is performed simultaneously. For example, as shown in the flowchart of FIG. 45, three A values of photometry, temperature measurement, and battery voltage are used.
/ D conversion is performed at the same time. Secondly, the memory area for storing the A / D conversion value corresponding to each camera information is checked in a predetermined memory area, and the contents of the memory area are operated or deleted by keys other than the release switch. Respond every predetermined time,
A / D conversion and updating are performed, and a camera operation is performed according to the A / D conversion value before the release switch is turned on.

Next, the constant voltage motor drive circuit block 206 will be described.

This constant voltage motor drive circuit block 2
Reference numeral 06 includes an operational amplifier OP2, resistors R13 and R14, and an external PNP power transistor.

This is a non-inverting type amplifier, and the following relationship is established between the potential at the high level "H" point and the potential VI at the I point.

[0221]

(Equation 16) Here, VI can produce and hold an arbitrary voltage value by charging the capacitor C1 from the GND level for a predetermined time by time control of the switching transistors Q18 and Q22. Thus, the CPU:
For example, it is possible to perform fine control such as driving at a low voltage at the start of winding or at a high voltage if the speed is increased to some extent.

In a CMOS process, as a method of utilizing the logarithmic compression characteristic, in addition to using a parasitic transistor, a MOS transistor may be replaced by a weak inversion region.
There is a method used in. That is, as shown in FIG. 46, in a region where the drain current is several hundred nA or less, the following relationship is established between the drain current ID and the gate-source voltage VGS.

[0223]

[Equation 17] Next, FIG. 49 is a diagram showing a specific circuit configuration when the region where the drain current is several hundred nA or less is applied to a distance measuring circuit.

In the figure, a pulse photocurrent detection circuit block comprises a CMOS operational amplifier OP1, a preamplifier comprising NMOS transistors Q1, Q2 and Q3 and constant current sources I1 and I2, a CMOS operational amplifier OP2, a transfer gate G1 and a capacitor C1. And a background light extraction circuit comprising an NMOS transistor Q4. Vref2 is set to VCC2-100 mv, and the operational amplifier OP2 is connected to the transfer gate G
When 1 is "ON", a feedback loop is formed by the preamplifier section, and the constant current of I1 and the background light component Ip1 of PSD are all discharged to GND through the transistor Q4, and the potential at that time is stored in the capacitor C1. You. In this state, the voltage between the drain and the source of the transistor Q3 becomes 100 mV, and almost no current flows through the transistor Q3. Transfer gate G1 is "off"
Therefore, even if the feedback loop is cut off, the capacitor C1 continues to hold the previous potential, so that the transistor Q4 still discharges the constant current of I1 and the background light component of PSD. At this time, the port P1 of the CPU
To turn on Q5, project an infrared light pulse from the IRED to the object, and when the photocurrent component .DELTA.Ip1 due to the reflected light is input to the PSD1 terminal, all of the current flows into the transistor Q3.

In this case, the transistor Q3 is made 20 times larger.
3 operates in the weak inversion region,
The potential at point A is determined by the following equation.

[0226]

(Equation 18) Similarly, the potential at point B is obtained from the following equation.

[0227]

[Equation 19] Then, the transistors Q6 and Q7 are also multiplied by 20 and I3
It is designed to operate in the weak inversion region compared to the constant current source. Further, the transistor Q
Assuming that the drain current of No. 6 is ID1, the following equation is established.

[0228]

(Equation 20) When the drain current of the transistor Q7 is ID2, the following equation is established.

[0229]

(Equation 21) Since the above two equations are equal, the following equation is established.

[0230]

(Equation 22) Therefore,

[0231]

(Equation 23) It becomes. Here, since ID1 + ID2 = 1 μA, the following equation holds.

[0232]

(Equation 24) From the above, the potential at the point C of R1 is expressed by the following equation.

[0233]

(Equation 25) Accordingly, since ΔIp2 / (ΔIp1 + ΔIp2) indicates the position of the center of gravity of the spot light image incident on the PSD, the object distance can be obtained by measuring the potential at the C point.

Further, the CPU performs A / D conversion of the C point in synchronization with the light emission pulse, and takes in the digital value. Then, light projection is performed a plurality of times, and the distance to the subject is calculated from the average value.

Next, FIG. 50 is a diagram showing a specific configuration when applied to a photometric circuit.

In the figure, the potential at point A is expressed by the following equation.

[0237]

(Equation 26) In this equation, Vref1 is the voltage of one of the taps of the tap decoder.

The current I1 flowing through the tap resistor R is expressed by the following equation.

[0239]

[Equation 27] Therefore, by performing successive approximation AD between the CPU and the tap decoder, the CPU can obtain an A / D value corresponding to the brightness.

As described in detail above, in the camera controller using the CMOS analog circuit of the present invention, the CMO
Since the analog circuit can be formed by the S process, the lead time and cost are comparable to those of the microcomputer, and the AF and AE circuits and the microcomputer can be integrated into one chip, so that the size of the camera can be reduced.

Furthermore, it is also possible to reduce the time lag and eliminate the restriction on the receivable time of the remote controller. In addition, by using a timer without a clock, there is no influence of clock noise. Then, even if the chip generates heat, the temperature of the LCD drive voltage can be corrected without erroneous determination.

[0242]

According to the present invention, a clock timer is required.
And a signal processing system including an analog timer circuit .

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a camera controller using a CMOS analog circuit according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a main sequence of a camera controller using a CMOS analog circuit according to the first embodiment.

FIG. 3 is a flowchart showing a sequence of a subroutine "release interrupt" executed when a release switch is pressed or a remote control signal is received.

FIG. 4 is a flowchart showing a sequence of a subroutine “LCD ON”.

FIG. 5 is a graph showing a relationship between a temperature (° C.) of the LCD 21 and a driving voltage (V).

FIG. 6 shows an NPN bipolar transistor existing in a CMOS process.
FIG. 2 is a diagram showing a transistor and an NPN bipolar transistor.

FIG. 7 is a diagram showing a specific example of a distance measuring circuit using a parasitic NPN transistor in a CMOS process.

FIG. 8 is a graph showing a relationship between a reciprocal 1 / a of a subject distance a and an output voltage value.

FIG. 9 is a flowchart for explaining a distance measuring sequence by the distance measuring circuit block 4;

FIG. 10 is a diagram showing a configuration of a photometric circuit block 13 using a parasitic NPN transistor in a CMOS process.

FIG. 11 is a diagram showing a configuration of a modified example of the photometric circuit block 13 in which the output Is of the reference voltage circuit differs between the average and the spot in advance.

FIG. 12 is a diagram showing a configuration of a modified example of the photometry circuit block 13 which is adjusted by adding a level shift circuit.

13 is a diagram showing a detailed configuration of a part of the photometry circuit block 13 shown in FIG.

FIG. 14 is a diagram showing a specific circuit configuration for generating a T stable and T proportional reference current for a DAC.

FIG. 15 is a flowchart showing a photometry sequence performed by the photometry circuit block 13;

FIG. 16 is a diagram showing a configuration of a temperature measurement circuit block 10 in a CMOS process.

FIG. 17 is a diagram illustrating a configuration of a specific example in which a motor drive circuit, a booster circuit, a plunger drive circuit, and the like are incorporated in the first embodiment.

FIG. 18 is a diagram showing a configuration of a remote control receiving circuit block of the camera.

FIG. 19 is a diagram showing operation waveforms of respective units when a remote control signal by infrared light is received.

FIG. 20 is a flowchart showing a subroutine "remote control reception interrupt" sequence.

FIG. 21 is a flowchart showing a subroutine “remote control setting” sequence.

FIG. 22 is a diagram showing a specific configuration of an NPN motor pre-driver circuit block 5 when a pre-driver circuit for a motor drive is formed on the same chip as a CPU and various measurement circuits of a camera.

FIG. 23 is a diagram illustrating a specific configuration of an analog timer circuit that does not use a clock.

FIG. 24 is a flowchart showing the operation of the analog timer circuit.

FIG. 25 is a timing chart related to the operation of the analog timer circuit.

FIG. 26 is a timing chart relating to the operation of the analog timer circuit.

FIG. 27 is a graph showing a relationship between a timer time and a D / A set value.

FIG. 28 is a diagram showing a specific configuration of a photometric circuit using an analog timer.

FIG. 29 is a flowchart showing the operation of a photometric circuit using an analog timer.

FIG. 30 is a diagram showing a specific configuration of an analog timer and a distance measuring circuit.

FIG. 31 is a flowchart showing the operation of an analog timer and distance measuring circuit.

FIG. 32 is a diagram showing a specific configuration of a circuit in which an analog timer is applied to evaluation of a remote control reception signal.

FIG. 33 is a diagram illustrating a state of output of a remote control light receiving circuit according to a circuit in which an analog timer is applied to evaluation of a remote control reception signal.

FIG. 34 is a flowchart showing an operation of a circuit in which an analog timer is applied to evaluation of a remote control reception signal.

FIG. 35 is a diagram showing a configuration of a camera controller using a CMOS analog circuit according to a second embodiment of the present invention.

FIG. 36 is a diagram showing a configuration of a camera controller using a CMOS analog circuit according to a second embodiment of the present invention.

FIG. 37 is a flowchart showing an operation for A / D converting a battery voltage.

FIG. 38 is a timing chart for explaining an operation for A / D conversion of a battery voltage.

FIG. 39 is a flowchart showing an operation for A / D converting a strobe charging voltage.

FIG. 40 is a timing chart for explaining an operation for A / D converting a strobe charging voltage.

FIG. 41 is a flowchart showing an operation of A / D converting a measured voltage value.

FIG. 42 is a timing chart for explaining an operation of A / D converting a measured voltage value.

FIG. 43 is a flowchart for describing in detail an operation of A / D converting a photometric value.

FIG. 44 is a timing chart for explaining an operation of A / D converting a photometric value.

FIG. 45 is a flowchart showing a sequence when three AD conversions of photometry, temperature measurement, and battery voltage are simultaneously performed.

FIG. 46 shows drain current ID and gate-source voltage VGS.
It is a graph which shows the relationship of.

FIG. 47 is a diagram illustrating a field-effect transistor according to an example.

FIG. 48 is a diagram showing a state of an IC package including a microcomputer.

FIG. 49 is a diagram showing a specific circuit configuration when a region where the drain current is several hundreds nA or less is applied to a distance measuring circuit.

FIG. 50 is a diagram showing a specific circuit configuration when a region where the drain current is several hundred nA or less is applied to a photometric circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU (microcom core), 2 ... booster circuit block, 3 ... remote control circuit block, 4 ... distance measuring circuit block, 5 ... NPN motor pre-driver circuit block, 6 ...
Motor constant voltage circuit block, 7 ... T stable T proportional DAC circuit block, 8 ... Comparator, 9 ... B. C circuit block, 10 temperature measurement circuit block, 11 reset circuit block, 12 reference voltage circuit block, 13 photometry circuit block, 14 flash light voltage detection circuit block, 1
5: PI / PR detection circuit block, 16: PLED driver circuit block, 17: PNP motor pre-driver circuit block, 18: EEPROM, 19: strobe circuit block, 20: switch, 21: LCD.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 1/00 H03K 17/00

Claims (1)

(57) [Claims] 1. A signal processing system comprising: a digital signal processing system; an oscillation circuit for generating a clock pulse signal to be supplied to the digital signal processing system; and a weak signal processing analog circuit system formed on a common semiconductor substrate. In the system, a reference current source, a charging unit that charges a capacitor by the reference current source and resets the capacitor, and D / A conversion
Means and a temperature detecting means, and D / A according to the detected temperature.
An analog timer circuit including a reference voltage setting unit for correcting the conversion output and a comparison unit for comparing the charging voltage of the capacitor to be charged with the reference voltage, when the analog circuit for weak signal processing is operated. A signal processing system that activates the analog timer circuit and inhibits the operation of the oscillation circuit according to the output of the analog timer circuit.