JP3535849B2 - Semiconductor device with dummy pattern of multilayer wiring structure - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with a dummy wiring pattern having a multi-layer wiring structure, and more particularly to a semiconductor device.
Function adding as bi ring pad is related to a multilayer wiring structure easy dummy wiring path <br/> turn.

[0002]

2. Description of the Related Art In a semiconductor device having a multilayer wiring structure, it is known that the density of wiring layers and wiring patterns affects the manufacturing process of the semiconductor device. That is, the density of the wiring pattern in each layer of the semiconductor device having a multilayer structure is
This may affect the flatness of the surface of the interlayer insulating layer formed in the upper layer and may also affect the dimensional accuracy of the wiring pattern in the upper layer, resulting in a decrease in the manufacturing yield of the semiconductor device.

[0003] Therefore, in the conventional semiconductor device of this type, the lower wiring pattern density of the wiring layer region, to form an independent pattern unrelated to the original wiring pattern of the dummy wiring pattern, the wiring density We are trying to stabilize the process by alleviating.

The form of such a dummy wiring pattern is a rectangular pattern having a large area covering the entire area where the wiring pattern does not exist, or a striped pattern which is independent of each other or is connected to each other like a normal wiring pattern. The pattern was used. When a striped pattern is used, it is often connected to a ground layer or a power supply layer to fix the potential.

An example of the technique of a semiconductor device having the above-mentioned dummy wiring pattern is disclosed in Japanese Patent Laid-Open No. 11-297841. FIG. 13 is a plan view of a dummy wiring pattern of this semiconductor device. As shown in FIG. 13, the dummy wiring pattern 100 has a stripe shape connected to each other.

[0006]

In a semiconductor device having a multi-layer wiring structure as shown in FIG. 13, when a probing pad for facilitating the probing of the lower layer wiring is formed, the probing pad 101 is formed on the uppermost layer. Wiring for pad connection 102 to create and probe
It is necessary to connect to the probing pad 101 with (Fig. 14).

Since the probing pad 101 is newly formed, all the layers from the layer to be probed to the uppermost layer are modified. At this time, since it is necessary to create the probing pad 101 separately from the dummy wiring pattern 100, if the dummy wiring pattern already exists, it is necessary to create the probing pad so as not to interfere with the dummy wiring pattern. .

Further, in a high frequency circuit, crosstalk may occur due to parasitic capacitance generated between the probing pad and the dummy wiring pattern, which may affect the characteristics of the circuit, and thus the probing pad 101 and the dummy wiring pattern. In some cases, the interval between the 100 and 100 cannot be ignored. Therefore, when creating a probing pad, resulting changes such partial deletion of the moving and the dummy wiring pattern of the dummy wiring <br/> pattern, becomes impossible uniform arrangement of the dummy wiring pattern, also, for probing There was a problem that the mask production cost increased due to the pad production man-hour, modification and addition.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems of the prior art and to provide a semiconductor device having a dummy wiring pattern of a multi-layer wiring structure in which a function as a propping pad can be easily added. It is a thing.

[0010]

A semiconductor device having a dummy wiring pattern of a multilayer wiring structure of the present invention has a multilayer wiring region formed by alternately providing an insulating layer and a wiring layer on a semiconductor element, On the semiconductor element, there is a vacant region in which the wiring layer is not formed continuously for a predetermined number of layers from a predetermined layer of the multilayer wiring to a surface layer, and the vacant region has the same number of layers as the predetermined number of layers. A plurality of multi-layered dummy wiring patterns are arranged, and the plurality of multi-layered dummy wirings are arranged.
At least one dummy of the multilayer structure of the pattern
Probing the dummy wiring pattern on the top layer of the wiring pattern
And wherein to Rukoto and ring pad serves dummy wiring pattern.

In the above-described structure of the semiconductor device of the present invention, a plurality of dummy wiring patterns are independently arranged in the empty area, and the dummy wiring patterns arranged independently of each other can be connected by through holes.

In the above structure of the semiconductor device of the present invention,
The through holes above and below a predetermined layer of the dummy wiring pattern can be arranged so as to be displaced from each other.

Further, in the above-described structure of the semiconductor device of the present invention, the dummy wiring patterns having a multi-layered structure may have a size different from each other in the layers immediately above and below.

In the above structure of the semiconductor device of the present invention,
A ring-shaped potential fixing dummy wiring pattern connected to the power supply layer or the ground layer of the semiconductor device can be provided so as to surround the dummy wiring pattern of each layer.

[0015] In the semiconductor device of the configuration of the present invention described above, the lowermost layer of the dummy wiring pattern of a predetermined dummy wiring pattern <br/> down in the dummy wiring pattern for wiring normal wiring layer of a semiconductor device The dummy wiring pattern can be used as a probing pad by connecting with a wiring different from the wiring and a through hole.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the semiconductor device of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a perspective view showing the basic structure of multilayer wiring of a dummy wiring pattern of a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the dummy wiring pattern has a three-layer structure shown by reference numerals 1a to 1c. Number of wiring layers of the dummy wiring pattern is determined by the number of layers in the region of the dummy wiring pattern. When up to 3 layers are used for the wiring of the device in the 5-layer wiring process, a multi-layer structure of a 2-layer dummy wiring pattern is obtained. When up to 3 layers are used for device wiring in the 7-layer wiring process, a 4-layer dummy wiring pattern is used.

The materials for the dummy wiring patterns 1a to 1c and the through holes 3 are usually Al, Al alloy, Cu.
Alternatively, a metal such as a Cu alloy is used, but is not limited to these metal materials.

The dummy wiring pattern of FIG. 1 is repeatedly arranged in a region on a semiconductor element where normal wiring is not formed. The size of the dummy wiring pattern and the interval between the patterns are determined in consideration of the process design rule.

FIG. 2 is a plan view in which the dummy wiring pattern of FIG. 1 is repeatedly arranged on a semiconductor element. Each dummy
Since the wiring pattern is to be arranged independently, if probing pad is required, available dummy wiring pattern as probing pad by connecting the points to be subjected to probing to any dummy wiring pattern, the probing pad The steps required to create the wirings are to arrange wirings and through-holes for connection from the desired point of probing to the bottom layer of the dummy wiring pattern.

[0021] In FIG. 2, reference numeral 2 is a dummy wiring pattern, i.e. probing pad serves dummy wiring pattern used in probing pad. The probing pad / dummy wiring pattern 2 uses the uppermost dummy wiring pattern 1c in FIG. 1 as a probing pad. The lowermost dummy wiring pattern 1a is connected to the probing portion of the semiconductor element by the pad connecting wiring 4.

The probing portion of the semiconductor device, the pad connection wiring 4 is connected dummy wiring pattern 1a, the dummy wiring path <br/> turns 1b and the top layer probing pad serves dummy wiring pattern 2 via the through-hole 3 It As described above, by utilizing the multilayer wiring structure of the dummy wiring pattern of the present invention, a part of the dummy wiring pattern 1c can be used as the probing pad without newly providing the probing pad.

Since the dummy wiring patterns of the semiconductor device of the present invention are uniformly arranged, the metal usage rate can be made uniform.

FIG. 3 shows the dummy wiring pattern A of FIG.
-A sectional view taken along the line B. In the figure, reference numeral 6 indicates a probing portion of a semiconductor element, reference numeral 7 indicates a portion where a probing pad is changed, and reference numeral 5 indicates an insulating layer made of an inorganic compound such as silicon oxide or an organic compound such as polyimide. When the probing pad is formed, the wiring (pad connection wiring 4) from the location where the probing is performed to the lowermost dummy wiring pattern 1a of the arbitrary dummy wiring pattern and the through hole 3a are formed. Dummy distribution
For use in a line pattern 1c and probing pad serves dummy wiring <br/> pattern 2, the upper layer of the dummy wiring pattern <br/> over down part does not need to perform a correction for probing. Since the dummy wiring pattern is arranged independently of other wirings and exists up to the uppermost layer, it can be used as a probing pad after connection.

Next, a multilayer wiring structure of a dummy wiring pattern of a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a perspective view showing the basic structure of the multilayer wiring of the dummy wiring pattern of the semiconductor device according to the second embodiment of the present invention. In this embodiment, the through holes 3 of the dummy wiring pattern in FIG. 1 are arranged so as to be displaced.

Referring to FIG. 4, and a through hole 3b for connecting the dummy wiring pattern 1b of the most lower dummy wiring <br/> pattern 1a and the intermediate layer, the dummy wiring interlayer pattern <br/> over emissions 1b Also, through holes 3c for connecting the dummy wiring patterns 1c in the uppermost layer are arranged in a staggered manner. The effect of the dummy wiring pattern structure of the present embodiment is that it can be applied to a process in which it is prohibited to dispose the upper through hole 3c immediately above the lower through hole 3b.

Next, a multilayer wiring structure of a dummy wiring pattern of a semiconductor device according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a perspective view showing the basic structure of the multilayer wiring of the dummy wiring pattern of the semiconductor device according to the third embodiment of the present invention. In the present embodiment, the shape of the dummy wiring pattern of the intermediate layer of FIG. 1 is made larger than that of the other layers. That is, the dummy of the two layers immediately above and below
This is when the size of the wiring pattern is changed. The effect of the present invention is that the present invention can be applied with an appropriate metal usage rate even when the required metal usage rate differs depending on the layer.

Referring to FIG. 5, the dummy wiring path <br/> magnitude of the turn 1d of the intermediate layer, the lower layer of the dummy wiring pattern 1a
And is formed larger than the dummy wiring pattern 1c in the upper layer. In the present embodiment, it is the ability to reduce the parasitic capacitance generated between the dummy wiring pattern is compared with the multilayer wiring structure of the dummy wiring pattern <br/> over emissions of FIG.

Next, a multilayer wiring structure of a dummy wiring pattern of a semiconductor device according to a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a plan view illustrating the basic structure of the multilayer wiring of the dummy wiring pattern of the semiconductor device according to the fourth embodiment of the present invention. In the present embodiment, FIG.
This is a case where the shape of the dummy wiring pattern is changed from a rectangular shape (FIG. 6A) to a polygonal shape (FIG. 6B). Figure 6 is a dummy
An example in which the shape of the wiring pattern is a regular octagon is shown.

In the above-described multilayer wiring structure of dummy wiring patterns according to the first to third embodiments of the present invention, since each dummy wiring pattern is in a floating state in which the potential is not biased, a high frequency circuit is provided. If used in, the cross-section of the wiring layer between each dummy wiring pattern and the lower layer wiring may be connected through the dummy wiring pattern due to the coupling due to the parasitic capacitance generated in the insulating layer, which may cause crosstalk. . Therefore, in the present embodiment, as shown in FIG. 6, the dummy wiring pattern has a rectangular shape.
Reduce the opposing cross-sectional area between the dummy wiring pattern <br/> down by changing the (FIG. 6 (a)) from the polygonal dummy wiring pattern 1e (FIG. 6 (b)), occurs between the dummy wiring pattern Reduced parasitic capacitance. Note that showed the shape of the dummy wiring pattern 6 most lower but also the same as the shape of the dummy wiring pattern of other layers. FIG. 7 is a perspective view showing the basic structure of the multilayer wiring of the dummy wiring pattern of the semiconductor device according to the fourth embodiment of the present invention. The lowermost dummy wiring pattern 1e, the intermediate dummy wiring pattern 1f, and the uppermost dummy wiring pattern 1g are connected by through holes 3. Also in this embodiment, it is possible to make the size larger than the size of the dummy wiring pattern of the intermediate layer,
Further, by arranging the through holes between the respective layers so as to be offset from each other, the same effect as that of FIG. 5 or 4 can be obtained.

Next, a multilayer wiring structure of a dummy wiring pattern of a semiconductor device according to a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a plan view showing the multilayer wiring structure of the dummy wiring pattern of the semiconductor device according to the fifth embodiment of the present invention. FIG. 9 is a perspective view thereof. In the present embodiment, the dummy wiring patterns around the probing pad / dummy wiring pattern 2 are connected to each other by wirings (indicated by guard ring wirings 8a to 8c) in the same layer. In a multilayer wiring structure of the dummy wiring pattern of the present embodiment, the probing pads combined dummy distribution
That is, the line pattern 2 can be protected from coupling with other wirings and dummy wiring patterns. Any of the inventions of the above-described first to fourth embodiments can be used for the multilayer wiring structure of the dummy wiring pattern.

[0032] The above fourth embodiment the dummy wiring pattern <br/> over emissions of the multilayer wiring structure near the dummy wiring path when the coupling is also to reduce the parasitic capacitance that becomes a problem with the the <br/> turn connected respectively, to fix the potential to connect to such GND, using dummy wiring pattern around the probing pad serves dummy wiring pattern <br/> down 2 as a guard ring. Although the parasitic capacitance with respect to GND increases, this guard ring can prevent the target probing pad from coupling with surrounding circuits.

Next, a multilayer wiring structure of a dummy wiring pattern of a semiconductor device according to a sixth embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a plan view showing the basic structure of the multilayer wiring of the dummy wiring pattern of the semiconductor device according to the sixth embodiment of the present invention, and FIG. 11 is its perspective view. This embodiment is an example of a case constituted by two kinds of patterns of the connecting pattern of the combined dummy wiring pattern probing pad dummy wiring pattern and the other dummy wiring <br/> patterns. In the above-described first to fourth embodiments, a ring-shaped potential fixing dummy wiring pattern 9 (guard ring wiring) surrounding the dummy wiring patterns of each layer
Will be added. Figure 12 is a perspective view showing an example of repeatedly arranged as potential fixing the dummy wiring pattern <br/> down 9 of the dummy wiring pattern adjacent a pattern to connect each other. For all of probing pad also serves as dummy distribution
Since the line pattern 2 is guarded, crosstalk due to coupling of parasitic capacitance does not occur.

[0034]

As described above, the following effects can be obtained in the multilayer wiring structure of the dummy wiring pattern of the semiconductor device of the present invention. (1) Since the dummy wiring pattern itself also serves as a probing pad, it is not necessary to change the dummy wiring path <br/> turn due to the need and probing pads created to create a probing pad separately probing pad In order to create the above, only the through hole and the wiring layer for connecting to the dummy wiring pattern are required. (2) Therefore, both the probing pad and the dummy wiring pattern can be easily created, additional correction can be performed at the minimum cost, and the mask manufacturing cost can be greatly improved. (3) By providing the card ring wiring around the dummy wiring pattern that also serves as the probing pad, it is possible to prevent crosstalk due to coupling of parasitic capacitance.

[Brief description of drawings]

FIG. 1 is a perspective view showing a basic structure of a multilayer wiring of a dummy pattern of a semiconductor device according to a first exemplary embodiment of the present invention.

FIG. 2 is a plan view in which the dummy pattern of FIG. 1 is repeatedly arranged on a semiconductor device.

FIG. 3 is a cross-sectional view taken along the line AB of the dummy pattern portion of FIG.

FIG. 4 is a perspective view showing a basic structure of multilayer wiring of a dummy pattern of a semiconductor device according to a second exemplary embodiment of the present invention.

FIG. 5 is a perspective view showing a basic structure of a multilayer wiring of a dummy pattern of a semiconductor device according to a third exemplary embodiment of the present invention.

FIG. 6 is a plan view illustrating a basic structure of a multilayer wiring of a dummy pattern of a semiconductor device according to a fourth exemplary embodiment of the present invention.

FIG. 7 is a perspective view showing a basic structure of a multilayer wiring of a dummy pattern of a semiconductor device according to a fourth exemplary embodiment of the present invention.

FIG. 8 is a plan view showing a multilayer wiring structure of a dummy pattern of a semiconductor device according to a fifth exemplary embodiment of the present invention.

FIG. 9 is a perspective view showing a multilayer wiring structure of a dummy pattern of a semiconductor device according to a fifth exemplary embodiment of the present invention.

FIG. 10 is a plan view showing a basic structure of a multilayer wiring of a dummy pattern of a semiconductor device according to a sixth exemplary embodiment of the present invention.

FIG. 11 is a perspective view showing a basic structure of multilayer wiring of a dummy pattern of a semiconductor device according to a sixth exemplary embodiment of the present invention.

FIG. 12 is a perspective view showing an example in which the patterns of FIG. 11 are repeatedly arranged so that adjacent guard ring wirings of dummy patterns are connected to each other.

FIG. 13 is a plan view showing the structure of a dummy pattern of a conventional semiconductor device.

FIG. 14 is a plan view for explaining a method of providing a probing pad in a dummy pattern arrangement region of a conventional semiconductor device.

[Explanation of symbols]

1a to 1g, 100 dummy patterns 2 Dummy pattern that also serves as a pad for probing 3 through holes 4 Pad connection wiring 5 insulating layers 6 Probing points 7 Probing Pad Making Changes 8a, 8b, 8c Guard ring wiring 9 Potential fixing dummy pattern

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-11-26576 (JP, A) JP-A-2000-150599 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/82 H01L 21/822 H01L 27/04

Claims (8)

(57) [Claims] 1. A multilayer wiring region formed by alternately providing an insulating layer and a wiring layer on a semiconductor element, wherein a predetermined layer to a surface layer of the multilayer wiring are continuously provided on the semiconductor element. It has a free space in which the wiring layer is not formed over a number of layers, double the same number of layers and the predetermined the layer number spatial-out area
A plurality of dummy wiring patterns having a multi-layered structure are arranged ,
At least one of a number of multi-layered dummy wiring patterns
The uppermost layer of the dummy wiring pattern of the above-mentioned multilayer structure
-Dummy wiring that also serves as a pad for probing wiring patterns
Dummy with a multi-layer wiring structure characterized by forming a pattern
A semiconductor device having a wiring pattern. 2. The plurality of dummy wiring patterns of the multilayer structure are independently arranged in the empty area, and the independently arranged dummy wiring patterns are connected by through holes. A semiconductor device comprising the dummy wiring pattern having the multilayer wiring structure according to claim 1. 3. The dummy wiring pattern having a multilayer wiring structure according to claim 1, wherein the through holes above and below a predetermined layer of the dummy wiring pattern are arranged so as to be displaced from each other. Equipped semiconductor device. 4. with a dummy wiring pattern of the multilayer wiring structure according to claim 1, wherein the dummy wiring pattern is immediately above and below each other size in the layer of the multilayer structure are different from each other Semiconductor device. 5. The planar shape of the dummy wiring pattern is a polygonal shape of a quadrangle or more.
A semiconductor device comprising the dummy wiring pattern having the multilayer wiring structure according to any one of items 1 to 4. 6. An insulating layer and a wiring layer are alternately formed on a semiconductor element.
The semiconductor element.
Continuously from the predetermined layer of the multilayer wiring to the surface layer on the child
A blank area where the wiring layer is not formed over a predetermined number of layers
The number of layers equal to the predetermined number of layers in the empty area.
A dummy wiring pattern having a layered structure is arranged, and a ring-shaped potential fixing dummy wiring pattern connected to the power supply layer or the ground layer of the semiconductor device is provided so as to surround the dummy wiring pattern of each layer of the multilayer structure. A semiconductor device provided with a dummy wiring pattern having a multilayer wiring structure characterized by being provided. 7. The lowermost dummy wiring pattern of a predetermined dummy wiring pattern of the dummy wiring patterns is connected to the wiring of the wiring layer of the semiconductor device by a wiring different from the wiring and a through hole. it semiconductor device including a dummy wiring pattern of the multilayer wiring structure according to any one of claims 1 to 6, wherein. 8. Alternating insulating layers and wiring layers on semiconductor elements
The semiconductor element.
Continuously from the predetermined layer of the multilayer wiring to the surface layer on the child
A blank area where the wiring layer is not formed over a predetermined number of layers
A plurality of layers having the same number of layers as the predetermined number of layers in the empty area.
A plurality of dummy wiring patterns having a multi-layered structure are arranged,
At least one of a number of multi-layered dummy wiring patterns
The uppermost layer of the dummy wiring pattern of the above-mentioned multilayer structure
-Dummy wiring that also serves as a pad for probing wiring patterns
A semiconductor device having a pattern, comprising:
Each layer of the multilayer structure for each of the dummy wiring patterns
The semiconductor device so as to surround the dummy wiring pattern of
Ring-shaped potential connected to the power or ground layer of
Features a fixed dummy wiring pattern
With a dummy wiring pattern of a multilayer wiring structure
Body device.