JP3531133B2 - Power module substrate and method of manufacturing the same - Google Patents
Power module substrate and method of manufacturing the sameInfo
- Publication number
- JP3531133B2 JP3531133B2 JP05425797A JP5425797A JP3531133B2 JP 3531133 B2 JP3531133 B2 JP 3531133B2 JP 05425797 A JP05425797 A JP 05425797A JP 5425797 A JP5425797 A JP 5425797A JP 3531133 B2 JP3531133 B2 JP 3531133B2
- Authority
- JP
- Japan
- Prior art keywords
- power module
- substrate
- metal
- chip
- mounting portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
Description
【０００１】[0001]
【０００２】本発明は高強度セラミックス金属複合体か
らなる回路基板に関し、更に詳しくは集積回路や半導体
部品の実装に好適な高ヒートサイクル性を有するパワー
モジュール基板に関するものである。The present invention relates to a circuit board made of a high-strength ceramic metal composite, and more particularly to a power module board having a high heat cycle property suitable for mounting integrated circuits and semiconductor parts.
【０００３】[0003]
【従来の技術】従来より、パワートランジスタ、ＩＧＢ
Ｔ、ＩＰＭ、パワーモジュール等熱が大量に発生する電
力デバイス用の実装基板としては、導電回路を有するセ
ラミックス回路基板が広く用いられており、特に近年で
は、高熱伝導率を有する回路基板を製造するために、セ
ラミックス基板の製造・導電回路の形成などに様々な工
夫がなされている。2. Description of the Related Art Conventionally, power transistors and IGBs have been used.
BACKGROUND ART Ceramic circuit boards having conductive circuits are widely used as mounting boards for power devices that generate a large amount of heat such as T, IPM, and power modules. In particular, in recent years, circuit boards having high thermal conductivity are manufactured. Therefore, various measures have been taken in the manufacture of ceramics substrates, formation of conductive circuits, and the like.
【０００４】図１は、パワーモジュール用基板を示し、
パワーモジュール用基板として用いられるセラミックス
基板１はアルミナ基板や窒化アルミニウムや窒化ケイ素
等の窒化物であり、これらの基板１の少なくとも片面に
銅板を直接接合法で接合したり、あるいは活性金属ろう
材を介して接合されている。FIG. 1 shows a power module substrate,
The ceramic substrate 1 used as a power module substrate is an alumina substrate or a nitride such as aluminum nitride or silicon nitride. A copper plate is directly bonded on at least one surface of these substrates 1 or an active metal brazing material is used. Are joined through.
【０００５】接合された金属は、所定形状の回路面を有
するようにエッチング処理により形成し、回路面にメッ
キ処理を施したものに半導体チップとしてのＳｉチップ
を搭載して、半導体モジュール基板として使用してい
る。The bonded metal is formed by etching so as to have a circuit surface of a predetermined shape, and the circuit surface is plated with a Si chip as a semiconductor chip to be used as a semiconductor module substrate. is doing.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら上記パワ
ーモジュール用基板上にＳｉチップを搭載する場合に
は、半田を用いて接着するのが一般的であるが、半田づ
けの際に半田自体が流れたり、チップの位置がずれると
いう問題があった。However, when the Si chip is mounted on the power module substrate, it is common to use solder to bond the solder, but the solder itself may flow during soldering. There was a problem that the position of the chip was misaligned.
【０００７】この問題を解決する一手段として、Ｓｉチ
ップ搭載部パターンの周囲部に穴を設け、半田流れを防
止していたが、この方法でも一部の半田流れの流出を止
めることはできず、不良品の発生を防ぐことはできなか
った。As a means for solving this problem, a hole is provided in the peripheral portion of the Si chip mounting portion pattern to prevent the solder flow. However, this method cannot stop a part of the solder flow. It was not possible to prevent the generation of defective products.
【０００８】本発明は、新規な手段を開発することによ
ってＳｉチップの位置ずれを防止したパワーモジュール
用基板及びその製造法を提供するものである。The present invention provides a power module substrate in which the displacement of the Si chip is prevented by developing a novel means, and a manufacturing method thereof.
【０００９】[0009]
【課題を解決するための手段】本発明者らは、斯かる課
題を解決するために鋭意研究したところ、従来のような
Ｓｉチップ搭載部周囲に穴を設けることに代えて、チッ
プ搭載部の周辺部の金属部分を他の部分より厚くするこ
とによって半田流れを防止し、チップ位置ずれを防ぐも
のである。Means for Solving the Problems The inventors of the present invention have made earnest studies to solve such problems. As a result, instead of providing a hole around the Si chip mounting portion as in the conventional case, By making the metal portion of the peripheral portion thicker than other portions, the solder flow is prevented and the chip position shift is prevented.
【００１０】本発明のパワーモジュール用基板は、セラ
ミックス基板と金属板との接合基板において、金属板の
半導体搭載部周辺部が半導体搭載部より 0.1mm 厚く、且
つ他の金属部分より0.15mm厚いことを特徴とする。The power module substrate of the present invention is a bonding substrate of a ceramic substrate and a metal plate , wherein the peripheral portion of the metal mounting portion of the metal plate is 0.1 mm thicker than the semiconductor mounting portion , and
One wherein the 0.15mm thicker than the other metal parts.
【００１１】上記セラミックス基板は、Ａｌ2 Ｏ3 、Ａ
ｌＮ、Ｓｉ3 Ｎ4 から選ばれる少なくとも１種のセラミ
ックス基板であることを特徴とする。The above ceramic substrate is made of Al 2 O 3 , A
l N, and wherein the at least one ceramic substrate selected from Si 3 N 4.
【００１２】上記金属板は、銅またはアルミニウム板で
ある。The metal plate is a copper or aluminum plate.
【００１３】上記接合は、金属板が平板状又は回路パタ
ーン状のものをセラミックス基板に直接接合あるいはろ
う接合することを特徴とする。The above-mentioned bonding is characterized in that a metal plate having a flat plate shape or a circuit pattern shape is directly bonded or brazed to a ceramic substrate.
【００１４】本発明のパワーモジュール用基板の製造法
は、セラミックス基板の少なくとも一面に金属板を接合
する工程と、上記金属板をエッチング処理して回路パタ
ーン形成する工程と、半導体搭載部及びその周辺部を除
いた上記回路パターン部分をエッチング処理して、上記
半導体搭載部周辺部を半導体搭載部より 0.1mm 厚く、他
の金属部分より 0.15mm 厚く、且つ上記他の金属部分の厚
さを 0.25mm とすることを特徴とする。A method of manufacturing a power module substrate according to the present invention comprises a step of bonding a metal plate to at least one surface of a ceramic substrate, a step of etching the metal plate to form a circuit pattern, a semiconductor mounting portion and its periphery. the circuit pattern portion excluding the part by etching, the
The peripheral part of the semiconductor mounting part is 0.1 mm thicker than the semiconductor mounting part , etc.
0.15 mm thicker than the metal part of , and the thickness of the other metal parts above
It is characterized in that the height is 0.25 mm .
【００１５】これらのセラミックス基板に接合する金属
は、銅、アルミニウム材及びこれらの合金であり、回路
形成後に回路面上にニッケルメッキを施すこともある。Metals bonded to these ceramic substrates are copper, aluminum materials and alloys thereof, and the circuit surface may be nickel-plated after the circuit is formed.
【００１６】回路面に半導体チップであるＳｉチップを
搭載する場合に、従来は半田を用いて接合させているが
半田自体が流れたりしてチップの位置がずれることがあ
ることから、これを防止するためにチップ搭載部周辺部
分の金属に穴を開けたり、あるいはチップ搭載周辺部に
ソルダーレジストを塗布したりしているが、本発明では
チップ搭載部の周辺部の金属部分を他の部分より厚くし
て半田流れを防止し、チップの位置ずれを防止してい
る。When a Si chip, which is a semiconductor chip, is mounted on the circuit surface, it is conventionally joined by using solder, but since the solder itself may flow and the position of the chip may shift, this is prevented. In order to do this, holes are made in the metal around the chip mounting portion, or solder resist is applied to the chip mounting peripheral portion.However, in the present invention, the metal portion in the peripheral portion of the chip mounting portion is better than other portions. It is made thicker to prevent solder flow and prevent chip displacement.
【００１７】この場合チップ搭載部の周辺部を他の部分
より厚くする手段としては二段エッチングを行なうが、
通常金属板の厚みが０．４ｍｍであれば０．１５〜０．
３５ｍｍの厚みを有するようにエッチングするのが好ま
しい。In this case, as a means for making the peripheral portion of the chip mounting portion thicker than other portions, two-step etching is performed.
Usually, if the thickness of the metal plate is 0.4 mm, 0.15 to 0.
It is preferably etched to have a thickness of 35 mm.
【００１８】[0018]
【発明の実施の形態】以下図面によって本発明の実施例
を説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to the drawings.
【００１９】（実施例１）(Example 1)
【００２０】セラミックス基板１として、５３×２９×
０．６３５ｍｍのＡｌ2 Ｏ3 基板を用い、この基板１の
両面に０．４ｍｍと０．４ｍｍの銅平板をそれぞれ回路
板２と放熱板３として不活性雰囲気下、１０６０℃で直
接接合した後、回路板２にエッチングレジストを塗布し
て印刷硬化し、塩化第二鉄溶液でエッチング処理を行い
図１に示すような銅パターンを形成した。As the ceramic substrate 1, 53 × 29 ×
After using a 0.635 mm Al 2 O 3 substrate and directly bonding 0.4 mm and 0.4 mm copper flat plates to the both surfaces of this substrate 1 as a circuit board 2 and a heat sink 3 in an inert atmosphere at 1060 ° C. The circuit board 2 was coated with an etching resist, print-cured, and etched with a ferric chloride solution to form a copper pattern as shown in FIG.
【００２１】次いで図３の回路基板断面図に示すように
チップ搭載部４を除いた回路板２部分をハーフエッチン
グ処理して厚さ例えば０．２５ｍｍとし、次いでチップ
搭載部４の周辺部厚みが他の金属部分より厚くなるよう
ハーフエッチング処理することによって０．３０ｍｍ厚
の搭載部４を得た。Next, as shown in the circuit board sectional view of FIG. 3, the circuit board 2 portion excluding the chip mounting portion 4 is half-etched to a thickness of, for example, 0.25 mm, and then the peripheral portion thickness of the chip mounting portion 4 is reduced. Half-etching treatment was performed so that the mounting portion 4 had a thickness of 0.30 mm so as to be thicker than other metal portions.
【００２２】次いで上記チップ搭載部においてＳｉチッ
プのサイズに０．１０ｍｍ厚の半田板を置き、その上に
Ｓｉチップを載せて、３６０℃、還元雰囲気中で加熱し
て半田付けをした。チップ搭載を複数個の回路基板に５
０ヶ行ったところ、いずれにも半田流れやチップの位置
ずれ等の不具合品はみられなかった。Next, in the chip mounting portion, a 0.10 mm thick solder plate was placed on the size of the Si chip, and the Si chip was placed on the solder plate and heated at 360 ° C. in a reducing atmosphere for soldering. Chip mounting on multiple circuit boards 5
When 0 was performed, no defective products such as solder flow and chip position shift were found.
【００２３】（実施例２）(Example 2)
【００２４】セラミックス基板１として、５３×２９×
０．６３５ｍｍのＡｌＮ基板を用い、その両面に０．４
ｍｍと０．４ｍｍの銅平板をＡｇ−Ｃｕ−Ｔｉ−ＴｉＯ
2 からなる活性金属ろう材を用いて加熱接合した。As the ceramic substrate 1, 53 × 29 ×
With A l N substrate of 0.635 mm, 0.4 on both surfaces
mm- and 0.4-mm copper plates on Ag-Cu-Ti-TiO
Heat-bonding was performed using an active metal brazing material composed of 2 .
【００２５】得られた接合体を用いて実施例１に示す方
法で図２に示した回路基板を得て、同様にＳｉチップを
複数個の回路基板に５０ヶ搭載して半田付けをしたとこ
ろ、いずれにも半田流れやチップの位置ずれ等の不具合
品は見られなかった。Using the obtained joined body, the circuit board shown in FIG. 2 was obtained by the method shown in Example 1, and 50 Si chips were similarly mounted on a plurality of circuit boards and soldered. In each case, no defective products such as solder flow and chip position shift were found.
【００２６】（実施例３）(Example 3)
【００２７】実施例２で用いたＡｌＮ基板に代えてＳｉ
3 Ｎ4 基板を用いた他は、まったく同一な手段で図２に
示す回路基板を得た。これらも同様に複数個の回路基板
に５０ヶのＳｉチップを搭載したところ、いずれにも半
田流れや位置ずれ等の不具合品は見られなかった。Si was used in place of the AlN substrate used in Example 2.
The circuit board shown in FIG. 2 was obtained by exactly the same means except that the 3 N 4 board was used. Similarly, when 50 Si chips were mounted on a plurality of circuit boards, no defective products such as solder flow or misalignment were found in any of them.
【００２８】（比較例１）(Comparative Example 1)
【００２９】セラミックス基板１として、５３×２９×
０．６３５ｍｍのＡｌ2 Ｏ3 基板を用い、その両面に
０．４ｍｍと０．４ｍｍの銅平板をそれぞれ回路板２と
放熱板３として不活性雰囲気下、１０６０℃で直接接合
した後、エッチングレジストを塗布して印刷硬化し、塩
化第二鉄溶液でエッチング処理を行い図１に示すような
銅パターンを形成した。As the ceramic substrate 1, 53 × 29 ×
A 0.635 mm Al 2 O 3 substrate was used, and 0.4 mm and 0.4 mm copper flat plates were directly bonded to both surfaces as the circuit board 2 and the heat sink 3 in an inert atmosphere at 1060 ° C., and then an etching resist was used. Was applied, printed and cured, and etched with a ferric chloride solution to form a copper pattern as shown in FIG.
【００３０】次いでＮｉメッキをパターン部に施した基
板１に搭載するＳｉチップの大きさに印刷方式でクリー
ム半田を印刷し、その上にＳｉチップを３６０℃で半田
付けしたところ、５０ヶの中で１割近い不具合品が見ら
れた。Next, cream solder was printed by the printing method on the size of the Si chip to be mounted on the substrate 1 on which the Ni plating was applied on the pattern portion, and the Si chip was soldered thereon at 360 ° C. Approximately 10% of defective products were found.
【００３１】[0031]
【発明の効果】上述のように本発明パワーモジュール基
板は、従来構造上やむを得なかった半田流れをなくすこ
とができることによって、チップの位置ずれという問題
も解決することができることから品質管理工程上コスト
削減に大いに寄与できるものである。As described above, the power module board of the present invention can eliminate the problem of chip misalignment by eliminating the solder flow, which was unavoidable in the conventional structure, thus reducing the cost in the quality control process. It can greatly contribute.
【図１】本発明のパワーモジュール用基板の製造工程を
示すための平面図である。FIG. 1 is a plan view showing a manufacturing process of a power module substrate of the present invention.
【図２】本発明のパワーモジュール用基板の斜視図であ
る。FIG. 2 is a perspective view of a power module substrate of the present invention.
【図３】本発明のパワーモジュール用基板の断面図であ
る。FIG. 3 is a cross-sectional view of a power module substrate of the present invention.
１ セラミックス基板 ２ 回路板 ３ 放熱板 ４ チップ搭載部 1 Ceramics substrate 2 circuit boards 3 heat sink 4 chip mounting part
───────────────────────────────────────────────────── フロントページの続き (72)発明者 高原 昌也 東京都千代田区丸の内一丁目８番２号 同和鉱業株式会社内 (56)参考文献 特開 昭59−150453（ＪＰ，Ａ) 特開 昭57−39545（ＪＰ，Ａ) 特開 平８−51172（ＪＰ，Ａ) 特開 平５−226385（ＪＰ，Ａ) 特開 平４−170088（ＪＰ，Ａ) 特開 平４−103150（ＪＰ，Ａ) 特開 平１−59986（ＪＰ，Ａ) 実開 昭56−56653（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 21/52 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masaya Takahara 1-8-2 Marunouchi, Chiyoda-ku, Tokyo Dowa Mining Co., Ltd. (56) References JP-A-59-150453 (JP, A) JP-A-57 -39545 (JP, A) JP-A-8-51172 (JP, A) JP-A-5-226385 (JP, A) JP-A-4-170088 (JP, A) JP-A-4-103150 (JP, A) ) Japanese Patent Laid-Open No. 1-59986 (JP, A) Actual Development Sho 56-56653 (JP, U) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23/12 H01L 21/52
Claims (4)
において、金属板の半導体搭載部周辺部が半導体搭載部
より0.1mm厚く、且つ他の金属部分より0.15mm厚いこと
を特徴とするパワーモジュール用基板。In the bonded substrate with a 1. A ceramic substrate and the metal plate, and wherein the 0.15mm thicker than the semiconductor mounting portion periphery 0. 1 mm thicker than the semiconductor mounting portion, and other metal parts of the metal plate Power Module board.
り、且つ上記他の金属部分の厚さが0.25mmであることを
特徴とする請求項１記載のパワーモジュール用基板。Wherein the thickness of the semiconductor mounting portion is 0.3mm der
Ri, and the power module substrate according to claim 1, wherein the thickness of the other metal part is 0.25 mm.
であることを特徴とする請求項１または２記載のパワー
モジュール用基板。3. The thickness of the semiconductor mounting portion peripheral portion is 0.4 mm.
The substrate for a power module according to claim 1 or 2, wherein
属板を接合する工程と、上記金属板をエッチング処理し
て回路パターン形成する工程と、半導体搭載部及びその
周辺部を除いた上記回路パターン部分をエッチング処理
して、上記半導体搭載部周辺部を半導体搭載部より 0.1m
m 厚く、他の金属部分より 0.15mm 厚く、且つ上記他の金
属部分の厚さを 0.25mm とすることを特徴とするパワーモ
ジュール用基板の製造法。4. A step of joining a metal plate to at least one surface of a ceramic substrate, a step of etching the metal plate to form a circuit pattern, and an etching of the circuit pattern portion excluding the semiconductor mounting portion and its peripheral portion. After processing, the peripheral part of the semiconductor mounting part is 0.1m from the semiconductor mounting part.
m thick, 0.15 mm thicker than other metal parts , and gold other than the above
A method for manufacturing a power module substrate, characterized in that the thickness of the metal portion is 0.25 mm .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05425797A JP3531133B2 (en) | 1997-02-24 | 1997-02-24 | Power module substrate and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05425797A JP3531133B2 (en) | 1997-02-24 | 1997-02-24 | Power module substrate and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10242331A JPH10242331A (en) | 1998-09-11 |
| JP3531133B2 true JP3531133B2 (en) | 2004-05-24 |
Family
ID=12965513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05425797A Expired - Lifetime JP3531133B2 (en) | 1997-02-24 | 1997-02-24 | Power module substrate and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3531133B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002353255A (en) * | 2001-05-30 | 2002-12-06 | Moric Co Ltd | Land pattern for soldering semiconductor chip |
| JP4923224B2 (en) * | 2007-10-01 | 2012-04-25 | Ｄｏｗａメタルテック株式会社 | Plating method for metal ceramic composite member and pattern manufacturing method for metal ceramic composite member |
| JP5002614B2 (en) * | 2009-04-30 | 2012-08-15 | 株式会社東芝 | Manufacturing method of ceramic circuit board |
| JP5691475B2 (en) * | 2010-12-15 | 2015-04-01 | 富士電機株式会社 | Semiconductor device and manufacturing method thereof |
| KR102005520B1 (en) * | 2011-11-11 | 2019-07-30 | 엘지이노텍 주식회사 | Lighting apparatus |
| EP3306655B1 (en) | 2015-05-27 | 2021-06-23 | NGK Electronics Devices, Inc. | Substrate for power modules, substrate assembly for power modules, and method for producing substrate for power modules |
| JP7301805B2 (en) | 2020-09-24 | 2023-07-03 | 株式会社東芝 | semiconductor module |
-
1997
- 1997-02-24 JP JP05425797A patent/JP3531133B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10242331A (en) | 1998-09-11 |
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