JP3530384B2 - Pixel signal processing circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pixel signal processing circuit , and more particularly, to a pixel signal processing circuit for subjecting an original pixel signal to horizontal zoom processing.

[0002]

2. Description of the Related Art Referring to FIG. 8, in a conventional zoom circuit 1, one of two pixel signals continuous in the horizontal direction is delayed by a register 2 for one pixel period, and both pixel signals are simultaneously multiplied by a multiplier 3 and I was typing in 4. As a result, the weighted signals to which predetermined weighting has been applied are simultaneously output from the multipliers 3 and 4, and the weighted signals are added by the adder 5 to obtain a pixel signal subjected to horizontal zoom.

[0003]

However, the timing for updating the two pixel signals to be processed becomes longer as the zoom magnification becomes larger, and becomes shorter as the zoom magnification becomes smaller. That is, as the zoom magnification increases, the number of times the same pixel signal is used for zoom processing increases, resulting in a longer update timing. On the other hand, if the zoom magnification is small, the same pixel signal may not be used twice or even once in some cases. As a result, the update timing becomes shorter as the zoom magnification becomes smaller.

Therefore, in the prior art, reduction zoom processing was impossible unless the input speed of the pixel signal was higher than the horizontal zoom processing speed. Therefore, a main object of the present invention is to provide a pixel signal processing circuit capable of performing reduction zoom processing without inputting pixel signals at high speed.

[0005]

Pixel signal according to the present invention
The processing circuit holds a plurality of horizontal pixel signals.
From the first holding means, the first output end and the second output end.
The two pixel signals output respectively are output by the first holding means.
Selecting means for selecting from a plurality of held pixel signals,
And zoom processing to the pixel signal output from the selection means.
Pixel signal processing circuit including zoom processing means
And the selection means is the same as when the enlarged zoom mode is selected.
One pixel signal or pixel signals consecutive in the horizontal direction
Sequential output from the output end, reduced zoom mode is selected
At this time, two pixel signals consecutive in the horizontal direction are fed to the first output terminal.
And simultaneously output from the second output terminal, the zoom processing means,
Two second holding means each holding one pixel signal,
The pixel signal output from one of the two second holding units is multiplied.
The first multiplication means for performing the multiplication and the other of the two second holding means
Second multiplier that multiplies the pixel signals output from the
Steps, and when the zoom mode is selected
2 holding means is connected in series with the first output terminal to reduce the zoom mode.
Mode is selected, the two second holding means are connected to the first output end.
And connection change means for connecting to the second output end, respectively
It is characterized by

[0006]

The first holding means is provided with a plurality of horizontally continuous images.
The elementary signal is held and the selection means has a first output end and a second output.
The first holding means holds two pixel signals respectively output from the ends.
Is selected from the plurality of pixel signals held by.
The pixel signal output from the selection means is sent to the zoom processing means.
Therefore, zoom processing is performed. Here, the selection means
The same pixel signal or when the large zoom mode is selected
Pixel signals continuous in the horizontal direction are sequentially output from the first output end.
And continuously in the horizontal direction when the reduced zoom mode is selected.
Two pixel signals from the first output end and the second output end
Output at the same time. In addition, the zoom processing means includes two second
Holding means, first multiplication means, second multiplication means and connection
Including change means. Each of the two second holding means is one image
The first multiplication means holds two elementary signals, and the second multiplication means holds two second holding means.
The pixel signal output from one of the
The calculation means outputs the image output from the other of the two second holding means.
Multiply the elementary signal. The connection change method is the enlarged zoom mode.
Mode is selected, the two second holding means are connected to the first output end.
Connected in series to and two when reduced zoom mode is selected
Second holding means for the first output end and the second output end, respectively.
Connect.

[0007]

According to the present invention, two consecutive pixel signals are selected at the same time. Therefore, even if the zoom processing speed and the pixel signal selection speed are the same, the zoom processing does not break down. That is, even when a small zoom magnification is set and the update timing of the pixel signal becomes short, the zoom process can be appropriately executed.

The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 1 and 2, a digital camera 10 of this embodiment includes an SRAM 12. SRAM
12 is formed by two banks as shown in FIG. 5, the number of words in each bank is "32", and each word is 32 bits. Then, addresses of "0" to "31" are assigned to the respective words. In the bank 0, for example, luminance data (Y data) and color data (C data) for 64 pixels of the previous line are stored,
Bank 1 stores, for example, Y data and C data for 64 pixels of the current line. That is, the SRAM 12 stores Y data and C data for a total of 128 pixels (for the first number of pixels) in the horizontal direction of two consecutive lines.

Both Y data and C data are 8 bits per pixel. Since one word has 32 bits, Y data or C data corresponding to 4 pixels (third pixel number) is written in each word. Y data is written to the addresses “0” to “15” of each bank,
The C data is written in the addresses "16" to "31" of each bank.

The memory control circuit 13 is such an SRAM.
Access 12 to read 32-bit Y or C data from the desired word. First Y ₀ data to Y ₃ data of the previous line from the address "0" of the bank 0 are read, then the current line from the address "0" Bank 1 Y ₀ data to Y ₃ data is read. Then, from the address "0" of bank 0, the C ₀ data to C _{3 of the} previous line
Data is read, C ₀ data -C ₃ data of the current line is read from the address "0" Bank 1. Such an operation is repeated up to the address "31" of each bank. In other words, the Y data of bank 0, the Y data of bank 1, the C data of bank 0, and the C data of bank 1 are accessed in this order, and the Y data and the C data are read word by word.

The 32-bit Y data of the previous line is DF
The 32-bit Y data of the current line, which is latched by the enable signal Yen0 in the F circuit 14, is transferred to the D-FF circuit 1.
At 6 it is latched by the enable signal Yen1. Also, the 32-bit C data of the previous line is the D-FF circuit 1
8 is latched by the enable signal Cen0, and the 32-bit C data of the current line is latched by the D-FF circuit 20 by the enable signal Cen1. The enable signals Yen0, Yen1, Cen0 and Cen1 are
It is generated at different timings based on the 24 MHz clock (CLK24). The enable signals Yen0, Yen1, Cen0 and Cen1 are output in synchronization with the access to the corresponding word.

The outputs of the D-FF circuits 14 and 16 are D-
Common load signal given to FF circuits 21 and 22
Latched by siglod. As a result, Y of 4 pixels (second pixel number) included in each of two consecutive lines
Data is output from the D-FF circuits 21 and 22 at the same timing. The load signal siglod is also generated based on the clock CLK24.

The outputs of the D-FF circuits 21 and 22 are directly input to the 6-2 selectors 30 and 32, respectively. The outputs of the D-FF circuits 21 and 22 are also output via the selectors 23 and 24 to the D-FF circuits 26 and 2.
8 and the outputs of the D-FF circuits 26 and 28 are 6
-2 selectors 30 and 32 respectively. The selectors 23 and 24 select the lower 16 bits of the input 32-bit data, and the D-FF circuits 26 and 28 latch the outputs of the selectors 23 and 24 in response to the load signal siglod. Therefore, 6-
Each of the two selectors 30 and 32 has a SRA
In addition to the Y data for 4 pixels read from M12,
Of the four pixels of Y data read out from the SRAM 12 last time, the latter two pixels are input.

That is, Y data for 6 pixels that are continuous in the horizontal direction in the previous line are input to the 6-2 selector 30, and Y for 6 pixels that are continuous in the horizontal direction in the current line.
The data is input to the 6-2 selector 32. 6-2 Selectors 30 and 32 select signal SEL generated based on a clock (CLK12) having a rate of 12 MHz.
According to 0 and SEL1, Y data for two consecutive pixels are selected from the input Y data for six pixels.

The 6-2 selector 30 is specifically constructed as shown in FIG. The output of the D-FF circuit 46 is D-
It is input to the FF circuit 30a and the output of the D-FF circuit 22 is input to the D-FF circuit 30b. D-FF circuit 30a
And 30b both latch input data in response to the load signal siglod. The D-FF circuit 30a has 16
Bit data, that is, Y data corresponding to two pixels is serially input, and Y data for these two pixels is output in parallel pixel by pixel. 32-bit data, that is, Y data corresponding to 4 pixels is input to the D-FF circuit 30b, and the Y data for 4 pixels is also output in parallel for each pixel. That is, Y data for 6 pixels that are continuous in the horizontal direction in the previous line are simultaneously output from the D-FF circuits 30a and 30b.

When paying attention to these 6 consecutive pixels, the Y data of the pixel located on the leftmost side is given to the terminals S (-2) and S '(-2), and the Y data of the pixel located second from the left. Data is provided at terminals S (-1) and S '(-1). Similarly, the Y data of the pixels located at the third, fourth, and fifth positions from the left are the terminals S (0) and S '.
(0), terminals S (1) and S '(1) and terminal S
(2) and S '(2), respectively, and the Y data of the pixel located on the rightmost side is supplied to terminals S (3) and S' (3). The switch 30c is connected to any of the terminals S (-2) to S (3) according to the selection signal SEL0, and the switch 30d is connected to any of the terminals S '(-2) to S' (3) according to the selection signal SEL1. To be done. As a result, from the Y data for 6 consecutive pixels,
Y data for two consecutive predetermined pixels are selected.

Since the 6-2 selector 32 has the same configuration as the 6-2 selector 30, duplicated description will be omitted. One output terminal of the 6-2 selector 30 has a D-FF circuit 3
4 is connected to the input end, and the output end of the D-FF circuit 34 is
It is connected to the input end of the multiplier 42 and one input end of the switch SW1. The other output end of the 6-2 selector 30 is connected to the other input end of the switch SW1, and the switch SW1
Is connected to the input end of the D-FF circuit 38. D
The output terminal of the -FF circuit 38 is connected to the input terminal of the multiplier 44. The D-FF circuits 34, 38, 36 and 40, and D-FF circuits 54, 56 and 6 to be described later.
4 latches the input data in response to the clock CLK12.

When the operator sets the enlargement zoom mode or the reduction zoom mode with the mode switching button 35, the switch control circuit 37 switches the switches SW1 and SW2 according to the setting mode. The switches SW1 and SW2 are connected to the D-FF circuits 34 and 36 in the enlargement zoom mode, and are connected to the 6-2 selectors 30 and 32 in the reduction zoom mode. That is,
In the enlargement zoom mode, the D-FF circuits 34 and 38 are serially connected, and in the reduction zoom mode, the D-FF circuits 34 and 38 are connected in parallel.

Therefore, in the enlarged zoom mode, 6-
The output from one output end of the 2-selector 30 is input to the multiplier 42 via the D-FF circuit 34, and D
-Input to the multiplier 44 through the FF circuits 34 and 38. Therefore, the Y data for two pixels output from one output end of the 6-2 selector 30 is input to the multipliers 42 and 44 pixel by pixel and simultaneously. On the other hand, in the reduction zoom mode, two pixels of Y data simultaneously output from the one output end and the other output end of the 6-2 selector 32 are passed through the D-FF circuits 34 and 38 to the multiplier 4
Input to 4 and 48 simultaneously.

The 6-2 selector 32, the D-FF circuits 36 and 40, the switch SW2 and the multiplier 46.
Since and 48 are also configured and operate in the same manner as described above, redundant description will be omitted. The coefficient generating circuit 39 outputs the horizontal zoom coefficient HZOOM, and the complement generating circuit 41 outputs the horizontal zoom coefficient HZOOM for "1".
The complement of (1 / HZOOM) is output. In the magnifying zoom mode, the complement generating circuit 41 is connected to the multiplier 42,
The coefficient generating circuit 39 is connected to the multiplier 44. Therefore, the complement (1 / HZOOM) is input to the multiplier 42 and the coefficient HZOOM is input to the multiplier 44. In the reduction zoom mode, the coefficient generation circuit 39 is connected to the multiplier 42, and the complement generation circuit 41 is connected to the multiplier 44. Therefore, the coefficient HZOOM is input to the multiplier 42, and the complement (1 / HZOOM) is input to the multiplier 44. When the switch control circuit 37 controls the switch SW3 according to the setting mode, the coefficient HZ
The OOM and complement (1 / HZOOM) are input to the desired multipliers 42 and 44 as described above.

Therefore, in the enlargement zoom mode, DF
The output of the F circuit 34 is weighted by the complement (1-HZOOM), and the output of the D-FF circuit 38 is the coefficient HZOOM.
Weighted by Conversely, in the reduced zoom mode,
The output of the D-FF circuit 34 is weighted by the coefficient HZOOM, and the outputs of the D-FF circuits 38 and 40 are weighted by the complement (1-HZOOM).

The 6-2 selector 30 continuously outputs the previous pixel data and the current pixel data from one output end in the enlargement zoom mode. That is, these data are output in the order of the previous pixel data and the current pixel data over a period of two pixels. As a result, the previous pixel data is input to the multiplier 44, and the current pixel data is input to the multiplier 42. On the other hand, in the reduction zoom mode, the 6-2 selector 30
The previous pixel data and the current pixel data are simultaneously output from one output end and the other output end. Therefore, the previous pixel data is input to the multiplier 42, and the current pixel data is input to the multiplier 4
4 is input. Thus, the multipliers 42 and 44
Since the pixel data given to the switch is inverted depending on the mode, the switch control circuit 37 switches the switch SW3 according to the mode.

The outputs of the multipliers 42 and 44 are the adder 5
0 is added, and the outputs of the adders 46 and 48 are added by the adder 5
It is added by 2. In this way, Y data having a desired horizontal zoom magnification, that is, horizontal zoom Y data, is generated from Y data for a predetermined two pixels that are continuous in the horizontal direction.
It should be noted that the multipliers 46 and 48 and the adder 52 are also configured and operate in the same manner as described above, and thus redundant description will be omitted.

The horizontal zoom Y data of the previous line and the horizontal zoom Y data of the current line are respectively supplied to the D-FF circuit 5.
Input to multipliers 58 and 60 via 4 and 56. In the multiplier 58, the complement (1-VZOOM) obtained by subtracting the vertical zoom coefficient VZOOM from "1" is multiplied by the horizontal zoom Y data of the previous line, and in the multiplier 60, the vertical zoom coefficient VZOOM is the horizontal zoom Y of the current line. The data is multiplied. The outputs of the multipliers 58 and 60 are added by the adder 62. As a result, zoom Y data that has undergone zoom processing in both the horizontal direction and the vertical direction is obtained, and is output to a monitor (not shown) via the D-FF circuit 64.

The C data output from the D-FF circuits 18 and 20 is also subjected to the same processing as described above, and as a result, zoom C data subjected to zoom processing in both the horizontal direction and the vertical direction is obtained. can get. Therefore, the same reference numerals and "'" are given to the corresponding circuits, and the duplicate description is omitted. Referring to FIG. 4, enable signals Yen0, Yen1, Cen0 and Cen1, load signal siglod and selection signal SE
L0 and SEL1 are created as follows. The active-low reset signal is input to one terminal of the logic circuit 66 and the reset terminal of the counter 82 in response to the horizontal synchronizing signal. The logic circuit 66 inputs a high level signal to the reset terminal of the counter 68 if either one of the two inputs is at a low level. Counter 68
And 82 are both clock synchronous counters,
It is reset in response to the first clock after the reset pin input rises.

The clock terminals of the counters 68 and 82 have the clock CLK shown in FIGS. 6A and 7A.
24 is input. However, the enable terminal of the counter 82 is connected to the carry-out terminal of the counter 68,
The counter 82 is activated only when the carry signal is output from the counter 68. Therefore, initially, only the counter 68 responds to the clock CLK24 and is shown in FIG.
It is incremented as shown in (C) and FIG. 7 (C). 6 shows the operation timing when the reduction zoom mode is set, and FIG. 7 shows the operation timing when the enlargement zoom mode is set.

The counter 68 is a counter that changes between "0" and "4", and the count value is output from the Q terminal to the comparators 70 to 74 and the decoder 76. The comparator 70 outputs a high level signal when the count value takes "4", the comparator 72 outputs a high level signal when the count value takes "0" to "3", and the comparator 74
Outputs a high level signal when the count value takes "3". Further, the decoder 76 outputs the enable signal Yen0 shown in FIGS. 6D and 7D and the load signal siglod shown in FIGS. 6H and 7H when the count value is “0”. To do. The decoder 76 also operates when the count value is "1" as shown in FIGS. 6 (E) and 7 (E).
When the count value is "2", the enable signal Yen1 shown in FIG. 6 is output, and when the count value is "3", the enable signal Cen0 is output. (G) and the enable signal Cen1 shown in FIG. 7 (G) are output.

On the other hand, the counter 82 inputs the count value from the Q terminal to the comparator 84, and the comparator 84 outputs a high level signal when the input count value is "0". The counter 82 is activated only while the carry signal is input from the counter 68, and the clock CLK24
Is incremented by. The counter 68 does not output the carry signal during the period in which the count value is incremented from “0” to “4” for the first time. As a result, the count value of the counter 82 maintains “0”, and the comparator 84
Keeps outputting a high level signal. Therefore, while the counter 82 outputs the count value “0”, the counter 68 is
Will continue to be activated. That is, the enable terminal of the counter 68 is connected to the comparators 72 and 84 via the OR circuit 80.
Is connected, but the output of the counter 68 is "4" for the first time.
When taking, the counter 68 is output by the output of the comparator 84.
Is activated.

When the output of the counter 68 is "3", the comparator 74 outputs a high level signal. Since the comparator 84 continues to output the high level signal until the counter 68 outputs the carry signal, the AND circuit 86 outputs the high level signal to the reset terminal of the latch circuit 88 only when the counter 68 first outputs the count value “3”. A signal is input. The latch circuit 88 is also a clock synchronous type, and
First clock C after the output of D circuit 86 falls
Reset by LK.

When the output of the counter 68 takes "4" for the first time, the counter 68 is in the activated state. Therefore, the output of the counter 68 immediately returns to "0" after taking "4".
That is, as shown in FIGS. 6C and 7C, after the count value takes “4” for the first time, the clock CLK2
It returns to "0" at the rising edge of 4. At the same time when the count value returns to "0", the carry signal is output from the counter 68. The counter 82 is activated by this carry signal and incremented by the clock CLK24. Therefore, the count value of the counter 68 takes a value other than "0", and the output of the comparator 84 falls from the high level to the low level. As a result, the counter 68 is activated by the output of the comparator 72 while the count values “0” to “3” are output, but when the count value becomes “4”,
Disabled. The count value is shown in FIG.
Maintain "4" as shown in (C).

Although the comparator 70 outputs a high level signal in response to the count value "4", the NAND circuit 78 is provided unless the carry signal is output from the latch circuit 88.
The output of keeps high level. Therefore, the counter 6
8 is not reset and remains disabled. In other words, when the carry signal is output from the latch circuit 88, the counter 68 is reset and simultaneously activated.

The output terminal of the inverter 92 is connected to the enable terminal of the latch circuit 88, and the clock CLK12 shown in FIGS. 6B and 7B is input to the input terminal of the inverter 92. The latch circuit 88 keeps the clock CLK24 while the clock CLK12 is at a low level.
In response to, the output of the adder 90 is latched. The output of the latch circuit 88 is fed back to the adder 90. The reciprocal of the horizontal zoom coefficient (1 / HZOOM) is input to the adder 90, and the reciprocal (1 / HZOOM) is added. The reciprocal (1 / HZOOM) is integrated at the timing shown in FIG. 6 (I) or FIG. 7 (I). When the reciprocal (1 / HZOOM) is “1.3”, the integration operation is performed at the timing shown in FIG. 6 (I), and the reciprocal (1 / HZOOM) is calculated.
When OM) is “0.65”, the integrating operation is performed at the timing shown in FIG.

The latch circuit 88 outputs a carry signal when the integrated value becomes "4" or more, and the integrated value is "4".
Subtract. In the reduction zoom mode, as shown in FIGS. 6 (I) and 6 (J), the integrated value output from the latch circuit 88 changes from “3.9” to “1.2”, and at the same time, a carry signal is output. It In enlarged zoom mode,
As shown in (I) and (J), the integrated value output from the latch circuit 88 changes from "3.9" to "0.55", and the carry signal is output at the same time. The carry signal is output only during a period corresponding to two clocks CLK24.

The carry signal output from the latch circuit 88 is input to the other terminal of the NAND circuit 78. The output of the counter 68 is still maintained at "4" and the comparator 70 outputs a high level signal. Therefore, the output of the NAND circuit 78 becomes low level, and FIG.
The counter 68 is reset and activated at the timing shown in (C).

The output timing of the carry signal depends on the reciprocal (1 / HZOOM). That is, the smaller the reciprocal, the later the carry signal output timing, and the larger the reciprocal, the earlier the carry signal output timing. The comparator 94 receives the integrated value output from the latch circuit 88, and outputs a high level signal when the integrated value becomes "2" or more. The RS-FF circuit 96 is a comparator 94.
Is reset when the output becomes high level and is set in response to the carry signal from the latch circuit 88. As can be seen from FIGS. 6M and 7M, the output of the RS-FF circuit 96 rises in response to the fall of the carry signal and falls when the integrated value becomes “2” or more. . The output of the RS-FF circuit 96 is input to the conversion table 104 as a control signal CTL.

The integrated value output from the latch circuit 88 is also given to the selector 98, and the selector 98 selects only the integer of this integrated value. D-FF circuits 100 and 102
Also, the input is latched in response to the clock CLK24 while the clock CLK12 is at the low level. The integer output from the selector 98 is input to the conversion table 104 via such D-FF circuits 100 and 102.

The conversion table 104 outputs the output of the D-FF circuit 102 as it is while the control signal CTL is at the low level, but when the control signal CTL is at the high level, the integer output from the D-FF circuit 102 is output. Convert to a predetermined value. That is, "3" is converted into "-1" and "2" is converted into "-2". However, if the output of the D-FF circuit 102 is “0” or “1”, even if the control signal CTL is at the high level, the value is output without being converted. The output of the conversion table 104 becomes the selection signal SEL0.

The output of the conversion table 104 is also added with "1" in the adder 106, and the output of the adder 106 becomes the selection signal SEL1. Therefore, the selection signals SEL0 and SEL1 shown in FIGS. 6K and 6L are output in the reduction zoom mode, and FIG.
Selection signals SEL0 and SE shown in (K) and (L)
L1 is output.

The first load signal siglod shown in FIGS. 6 (H) and 7 (H) is meaningless. Second load signal
In response to siglod, pixel data (original pixel data) for a total of 8 pixels of the previous line and the current line is loaded. That is, the Y data for 4 pixels in each line is D-FF.
The circuits 21 and 22 are loaded respectively, and the C data for four pixels in the same line are loaded to the D-FF circuits 21 'and 22', respectively. At this time, no pixel data is output from the D-FF circuits 26, 28, 26 'and 28'. Therefore, the selection signals SEL0 and SEL1 change only between "0" and "3", and the switches 30c and 30d shown in FIG. 3 are connected only to terminals having the same numerical value.

In response to the next load signal siglod, the pixel data for four consecutive pixels in the horizontal direction is transferred to the D-FF circuit 2.
1, 22, 21 'and 22'. At the same time, the pixel data of the preceding two pixels is transferred to the D-FF circuit 2.
6, 28, 26 'and 28'. As a result, pixel data for 6 consecutive pixels are output simultaneously,
The selection signals SEL0 and SEL1 are "-1" and "-".
The value of 2 ″ is obtained. The pixel data for 6 consecutive pixels is updated by 2 pixels thereafter. 6-2 Selectors 30 and 3
2, 30 'and 32' are the selection signals SEL0 and S
Pixel data for two pixels is selected according to EL1.

As can be seen from FIGS. 6K and 6L, pixel data for two consecutive pixels are simultaneously selected in the reduction zoom mode. Specifically, the selection signal SEL0
The previous pixel data is selected by and the current pixel data is selected by the selection signal SEL1. On the other hand, in the magnifying zoom mode, pixel data for two consecutive pixels is sequentially selected by the selection signal SEL0 as shown in FIG. 7 (K). That is, when the selection signal SEL0 takes "0" and "1" and takes "1" and "2", the previous pixel data and the current pixel data are selected in this order.

The numerical values of the selection signals SEL0 and SEL1 change at a rate of 12 MHz, and as a result, the selected pixel data also changes at a rate of 12 MHz. The horizontal zoom coefficient HZOO is added to the pixel data selected in this way.
M and the vertical zoom coefficient VZOOM are weighted, and as a result, zoom pixel data is obtained.

Assuming that the number of pixels included in each word of the SRAM 12 is "N", the ratio of the clock CLK24 used to access the SRAM 12 and the clock CLK12 used to generate zoom pixel data (CLK12 / CLK
24) is assumed to be "α". Then, the number of pixels that must be used for generating zoom pixel data in each word is αN. Below this αN, SRAM1
The access speed to 2 does not catch up with the generation speed of the zoom pixel data, and the zoom process fails. Therefore, the minimum zoom magnification that can be set is αN / (N-1).
Becomes Note that (N-1) indicates the distance between pixels included at both ends of one word.

In this embodiment, since N = 4 and α = 1/2, αN = 2. Therefore, the minimum value of the zoom magnification is "2/3".

[Brief description of drawings]

FIG. 1 is a block diagram showing a part of an embodiment of the present invention.

FIG. 2 is a block diagram showing another part of the embodiment of the present invention.

FIG. 3 is a block diagram showing a part of the embodiment shown in FIG.

FIG. 4 is a block diagram showing another part of the embodiment of the present invention.

5 is an illustrative view showing a part of the embodiment in FIG. 1; FIG.

FIG. 6 is a timing chart showing a part of the operation of the embodiment in FIG. 4;

FIG. 7 is a timing chart showing another part of the operation of the embodiment in FIG. 4;

FIG. 8 is a block diagram showing a conventional technique.

[Explanation of symbols]

10 ... Digital camera 12 ... SRAM 30, 32, 30 ', 32' ... 6-2 selector 35 ... Mode switching button 37 ... Switch control circuit 39 ... Coefficient generating circuit 41 ... Complement generating circuit 42, 44, 46, 48, 42 ', 44', 46 ', 4
8 '... Multipliers 50, 52, 50', 52 '... Adder

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/228

Claims (4)

(57) [Claims] 1. Holding a plurality of pixel signals that are continuous in the horizontal direction
Two holding means, each of which outputs from the first output end and the second output end
A plurality of pixel signals held by the first holding means
Selecting means for selecting from among the pixel signals of
Zoom that applies zoom processing to the pixel signals output from the means
In the pixel signal processing circuit including processing means, the selection means is the same when the enlargement zoom mode is selected.
One pixel signal or pixel signals consecutive in the horizontal direction
Sequential output from the first output end, and reduction zoom mode is selected.
The two pixel signals that are continuous in the horizontal direction when the first
Simultaneous output from the output end and the second output end, and the zoom processing means holds one pixel signal each.
Two second holding means, one of the two second holding means
First multiplier that multiplies the pixel signals output from the
Stage, the pixel output from the other of the two second holding means
Second multiplying means for multiplying a signal, and the expansion unit
The two second holding means when the boom mode is selected.
Connected in series to the first output terminal, the reduction zoom mode
When selected, the two second holding means output the first output
End and connection change hand for connecting to the second output end, respectively
A pixel signal processing circuit including a stage. 2. A first coefficient generator for generating a first multiplication coefficient.
Stage, second coefficient generating means for generating a second multiplication coefficient, and
Note that when the enlarged zoom mode is selected, the first multiplier
A number and the second multiplication coefficient to the first multiplication means and
And the second multiplying means respectively, and
When the first mode is selected, the first multiplication coefficient and
The second multiplication coefficient and the second multiplication means;
Assign change means assigned to each multiplication means
The pixel signal processing circuit according to claim 1, further comprising: 3. The first multiplication coefficient corresponds to “1”
The pixel signal according to claim 2, which is a complement of the second multiplication coefficient.
Processing circuit. 4. A pixel according to any one of claims 1 to 3.
A digital camera having a signal processing circuit.