JP3519506B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a plurality of MIS (me
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a ring oscillator is composed of tal-insulator-semiconductor (transistor-semiconductor) transistors, and more particularly to measures for increasing the operation speed of the semiconductor device.

[0002]

2. Description of the Related Art A MIS transistor is a four-terminal device having a substrate portion, a gate, a source and a drain. In this MIS transistor, a threshold voltage Vt defined as a voltage applied to a gate terminal required to form a channel changes according to a voltage applied to a substrate portion, that is, a substrate bias Vsub. FIG. 8 shows a drain current Id with respect to a general gate-substrate voltage Vgs.
It is shown that the change characteristic of V changes with the substrate bias Vsub. Further, FIG. 9 shows a general substrate bias V
The change characteristic of the threshold voltage Vt with respect to sub is shown. In FIG. 8, the horizontal axis represents the gate-substrate voltage Vgs.
The vertical axis represents the drain current Id, and the gate-substrate voltage Vgs at the point indicated by the white circle in the figure corresponds to the threshold voltage Vt. As shown in FIGS. 8 and 9, generally, the threshold voltage Vt increases as the substrate bias Vsub becomes deeper, that is, the substrate bias Vsub increases toward the negative side. In the submicron MIS transistor, the power supply voltage is usually 3.3V or 5V, and the threshold voltage Vt is set to about 0.5V. Also, the substrate bias V
Sub is fixed to, for example, -2V or 0V.

By the way, as the pulse oscillator using the MIS transistor, for example, a ring oscillator having a basic structure of a plurality of stages of inverters as shown in FIG. 10 is used. In FIG. 10, 50 is a power supply voltage application terminal, 51 is an output terminal, and 52 to 56 are inverters.
Here, the odd-numbered stages of inverters 52 to 54 (only three stages are shown here, but the number of stages is not limited to this) form a feedback loop. FIG. 11 is a diagram showing an example of the circuit configuration of the ring oscillator of FIG.
In the figure, the same reference numerals as those in FIG. 10 denote the same or corresponding parts, 52a, 53a, 54a, 55a are P-channel transistors, and 52b, 53b, 54b, 55b are N-type.
It is a channel transistor. That is, the ring oscillator of FIG. 10 is configured by connecting in series the inverters 52 to 54 each including a parallel connection body of a P-channel transistor and an N-channel transistor.

[0004]

Generally, in the case of a ring type oscillator, a waiting time of about 10 cycles is required from the power is supplied until the oscillation frequency stabilizes even in an ideal state. In particular, a ring-type oscillator, for example PLL (pha
se locked loop) When incorporating in a signal processing circuit system such as a clock generator, the waiting time of 10
Double the margin is required. In recent years, the demand for high-speed operation in semiconductor devices has been remarkably high.
In a ring-type oscillator that uses transistors, there is a demand for shortening the waiting time from when power is supplied until the oscillation frequency stabilizes.

The present invention has been made in view of the above problems, and in a semiconductor device in which a ring oscillator is constituted by MIS transistors, a semiconductor device provided with a ring oscillator for quickly stabilizing the oscillation frequency thereof. It is intended to provide.

[0006]

A semiconductor device according to the present invention is a semiconductor device in which a ring oscillator is constituted by a plurality of MIS transistors.
A substrate bias self-adjusting MIS in which a bias is applied to a substrate portion of a transistor through a resistor and the substrate bias changes in a self-adjusting state during operation and during non-operation.
As a result, when the substrate bias self-adjusting MIS transistor is operated, a potential difference is generated across the resistor due to the substrate current, the substrate bias becomes shallow, and During operation, the substrate current does not flow, and the substrate bias becomes the bias potential itself from the outside. Therefore, since the time constant RC required for switching the substrate bias is usually shorter than the oscillation period of the ring oscillator, the substrate bias changes within one period of the oscillation period. When the ring oscillator operates, the substrate bias changes. The substrate bias of the bias self-adjusting MIS transistor becomes shallow within the oscillation period and is fixed, and the MIS transistor that constitutes the ring oscillator is maintained in a state in which its driving capability is improved. As a result, the time from the supply of power to the ring oscillator to the stabilization of the oscillation frequency is greatly shortened.

Further, the semiconductor device according to the present invention has a PL
It is characterized in that the voltage controlled oscillator of the L clock generator incorporates the ring oscillator constituted by the plurality of substrate bias self-adjusting MIS transistors, whereby the oscillation of the ring oscillator is achieved. Since the frequency stabilizes quickly, the operation of the PLL clock generator can be speeded up.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION In the above structure, a plurality of substrate bias self-adjusting MISs constituting the ring type oscillator.
If the transistors are configured such that the bias is applied to the respective substrate portions through the same resistor, it is not necessary to provide a resistor for each transistor, so the manufacturing process is simplified. It can be anything.

In the above structure, the plurality of substrate bias self-adjusting MIS transistors forming the ring oscillator may be such that the bias is applied to each of the substrate portions via a dedicated resistor. If
Each of the plurality of substrate bias self-adjusting MIS transistors can be operated with a substrate bias capable of significantly improving the maximum transconductance Gmmax by adjusting the resistance value of its dedicated resistor.

[0010]

EXAMPLES Example 1 1 is a block diagram showing a configuration of a PLL clock generator according to a first embodiment of the present invention.
Reference numeral 10 is a semiconductor substrate of a predetermined conductivity type.
A phase comparator 1, a low pass filter 2, and a voltage controlled oscillator 3 are formed in the. Here, the voltage controlled oscillator 3 is configured by using the ring oscillator shown in FIGS. 10 and 11, and has a conductivity type different from that of the substrate 10 formed in a predetermined region of the substrate 10. It is formed in the well 11. The well 11 electrically isolates the voltage-controlled oscillator 3 from the substrate region in which the phase comparator 1 and the low-pass filter 2 are formed. Reference numeral 20 denotes a substrate bias generation circuit, which is directly connected to the phase comparator 1 and the low-pass filter 2 (the substrate region in which they are formed), and the voltage controlled oscillator 3 (the substrate region in which it is formed).
Is connected via a resistor 4 made of a substance having a high electric resistance. Therefore, the MIS transistor forming the voltage controlled oscillator (ring type oscillator) 3 becomes a substrate bias self-adjusting transistor, and the MIS transistors forming the other circuits (MIS transistors forming the phase comparator 1 and the low-pass filter 2). Is a fixed substrate bias type transistor.

FIG. 2 is a cross-sectional view for explaining the structure and operation of the substrate bias self-adjusting MIS transistor. In the figure, the same reference numerals as those in FIG. 1 designate the same or corresponding portions, and the LOCOS of the semiconductor substrate 21 is shown. (local oxi
The substrate region separated from other regions by the dation silicon) film 26 is defined as a P well 21a.
A source 24 and a drain 25 are formed in a. A gate oxide film 23 is formed on the surface of the substrate, and the gate 22 is formed on the gate oxide film 23. A bias voltage applying terminal 27 is connected to the semiconductor substrate 21 via the resistor 4 made of the substance having a high electric resistance, and the bias generating circuit 20 outputs Vbb. As shown in the figure, when a current flows from the drain 25 to the source 24, electrons flow from the source 24 to the drain 25. At this time, electrons are rapidly accelerated by a high electric field channel region near the drain 25 (usually at a potential midway between the source 24 and the drain 25) and collide with the lattice of the semiconductor substrate 21 to form a hot electron-hot hole pair. Occurs. The hot electrons generated in this way are attracted to the gate 22, but the hot holes flow into the semiconductor substrate 21 (P well 21a) at a low potential and become the substrate current Isub. Then, the substrate current Isub causes a potential difference across the resistor 4, and the substrate bias Vsub is self-adjusted by the potential difference.

FIG. 3A shows a substrate bias self-adjusting MI.
FIG. 3B is a diagram showing a setting state of the substrate bias Vsub between the operating state and the non-operating (standby) state in the S transistor, and FIG. 3B is a substrate bias self-adjusting MI.
FIG. 3C is a diagram showing a change characteristic of the substrate current Isub between the operating state and the non-operating (standby) state in the S transistor, and FIG. 3C is the operating state and the non-operating (standby) state in the substrate bias self-adjusting MIS transistor. It is a figure showing the change characteristic of substrate bias Vsub between states. In these figures, the same reference numerals as those in FIG. 2 indicate the same or corresponding portions. This FIG. 3 (a) -FIG.
As shown in (c), when the substrate bias self-adjusting MIS transistor is in operation, the substrate current Isub causes a potential difference across the resistor 27, and the substrate bias Vsub becomes shallow. On the other hand, since the substrate current Isub does not flow during non-operation (standby), the substrate bias Vsub
Becomes equal to the output Vbb of the substrate bias generation circuit.
That is, in the substrate bias self-adjusting MIS transistor, the substrate bias Vsub changes between the operating state and the non-operating state. Therefore, this substrate bias self-adjusting MI
In the ring type oscillator of the voltage controlled oscillator 3 configured by using the S transistor, the time constant RC required for switching the substrate bias Vsub is shorter than the oscillation period of the ring type oscillator (for example, 10 ns even if it is very short). , The substrate bias Vsub changes within one cycle of the oscillation cycle.

FIG. 4 shows the substrate bias self-adjusting MIS.
It is a figure showing the gate voltage dependence of the drain current and substrate current in a transistor. At the time of operation "Active" indicated by the solid line in the figure, the substrate bias Vsub becomes as shallow as 0 V, so that the threshold voltage is lowered and the driving capability is improved. On the other hand, the non-operating "Sta indicated by the broken solid line in the figure
In ndby ", the substrate bias Vsub is deepened to -2 V to increase the threshold voltage and suppress the off leak current.

From the above description, the PLL according to the present embodiment
In the clock generator, when the voltage controlled oscillator 3 is operating, that is, when the ring oscillator is operating, at a certain moment, at least one inverter forming the ring oscillator is in a transient state. It can be seen that the substrate current Isub steadily flows in the substrate bias self-adjusting MIS transistor that constitutes the ring oscillator. Therefore, during operation of the ring oscillator, the substrate bias self-adjusting MIS transistor forming the ring oscillator has a substrate bias Vsub that becomes shallow within the oscillation period of the ring oscillator, and is fixed, and its driving capability is reduced. Maintained in improved condition. Therefore, the time from when power is supplied to the ring oscillator to when the oscillation frequency stabilizes is greatly shortened.

In the device of this embodiment, since the common resistor 4 is provided on the substrate of the voltage controlled oscillator 3, the substrate potentials of all the transistors in the voltage controlled oscillator 3 become shallow during the operation of the voltage controlled oscillator 3. Become. Therefore, the off-leakage current of the non-operating transistor in the voltage controlled oscillator 3 increases, and the power consumption of the voltage controlled oscillator 3 increases to some extent. However, the off-leakage current of the transistor in the non-operating state is at least several orders of magnitude different from the operating current of the transistor in the operating state, and is extremely small, and the power consumption during the operation of the voltage controlled oscillator 3 does not increase. It can be almost ignored. On the other hand, when the voltage controlled oscillator 3 is in the non-operating state, the substrate potential is set deep, so that the standby current does not change at all as compared with the one configured by using the normal MIS transistor.

Embodiment 2 . Hereinafter, a PLL clock generator according to a second embodiment of the present invention will be described with reference to FIGS.

FIG. 5 is a sectional view showing the structure of the substrate bias self-adjusting MIS transistor adopted in this embodiment. In the figure, the same reference numerals as those in FIG. 2 indicate the same or corresponding portions, and 21a indicates a semiconductor substrate. The substrate portion is divided into island shapes by the resistance layer 28 of 21. In the first embodiment, there is a 1
Although one resistor 4 is provided so that the entire circuit block of the voltage controlled oscillator 3 is controlled by the substrate bias generation circuit, in the device of this embodiment, as shown in FIG. Transistors to be controlled by the substrate bias generating circuit of
The substrate portion 21a is surrounded by 8, and the substrate bias Vsub of each transistor is adjusted by the resistance value of the resistance layer 28. Further, since the substrate region in which the substrate bias changes is divided by the resistor 28 to be narrowed (smaller), the parasitic capacitance in this region becomes smaller and the time constant becomes smaller. That is, the structure is such that the substrate potential easily follows the substrate current.

FIGS. 6 and 7 are graphs showing the resistance value Rext dependence of the resistor in the current-voltage characteristic and the saturation current characteristic when the substrate bias Vsub follows the substrate current Isub. In the figure, each characteristic curve is such that the resistance value Rext of the resistor is 0, in the direction of the arrow in the figure.
The characteristics of the transistors of 0.5, 1, 1.5 and 2 MΩ are shown, and the characteristic curve of which the resistor Rext is 0Ω shows the characteristics of the conventional substrate bias fixed MIS transistor. Further, in FIG. 6, the vertical scale showing the drain current Id on the left side is made up of both the Log scale and the linear scale, and the substrate bias fixed MI is used.
This is a display for clarifying the difference in drain current Ld between the S transistor and the substrate bias self-adjusting MIS transistor. From these figures, the resistance value of the resistor Rex
It can be seen that by controlling t, the maximum transconductance Gmmax can be significantly improved without changing the subthreshold characteristic that is a current-voltage characteristic equal to or lower than the threshold voltage.

That is, in the PLL clock generator of this embodiment, each of the substrate bias self-adjusting MIS transistors forming the voltage controlled oscillator including the ring oscillator is adjusted by adjusting the resistance value of its resistance layer 28. It operates with the substrate bias Vsub that can significantly improve the maximum transconductance Gmmax without changing the subthreshold characteristic which is the current-voltage characteristic below the threshold voltage. Therefore, the ring oscillator normally repeats its operation in the vicinity of the maximum transconductance Gmmax.
The L clock generator is superior to the PLL clock generator of the first embodiment in this respect.

In the above description, the ring oscillator of the voltage controlled oscillator in the PLL clock generator is constructed by using an inverter as a circuit element. However, in the present invention, the ring oscillator of the voltage controlled oscillator includes another logic circuit such as a NAND circuit. It may be configured as a circuit element.

In the first and second embodiments, the MIS transistor of the entire circuit block of the voltage controlled oscillator is the substrate bias self-adjusting MIS transistor. However, in the present invention, the MIS transistor of the entire PLL clock oscillator is connected to the substrate. The bias self-adjusting MIS transistor may be applied, or the substrate bias self-adjusting MIS transistor may be applied to the MIS transistor of the ring oscillator only in the voltage controlled oscillator. This P
When the substrate bias self-adjusting MIS transistor is applied to the MIS transistor of the entire LL clock oscillator, it is not necessary to distinguish the formation region of the substrate bias self-adjusting MIS transistor and the substrate bias fixed type transistor in the substrate. The manufacturing process can be simplified, and the power consumption of the entire PLL clock oscillator can be reduced.

Further, in the present invention, the PLL clock generator may have a frequency divider for generating a frequency higher than an external clock.

[0023]

As described above, according to the semiconductor device of the present invention, in a semiconductor device in which a ring-type oscillator is composed of a plurality of MIS transistors, the plurality of MIS transistors are connected to the substrate portion thereof by resistors. Since a substrate bias self-adjusting MIS transistor in which a bias is applied through the body and the substrate bias changes in a self-adjusting manner during operation and when not in operation, the substrate bias self-adjusting during operation of the ring oscillator. The substrate bias of the ring-type MIS transistor becomes shallow within the oscillation period of the ring-type oscillator, and is fixed, so that the ring-type oscillator is constructed.
The IS transistor is maintained in a state in which its driving capability is improved, and as a result, there is an effect that the time from the supply of power to the ring oscillator to the stabilization of the oscillation frequency can be greatly shortened.

Further, according to the semiconductor device of the present invention, the voltage controlled oscillator of the PLL clock generator incorporates the ring oscillator constituted by the plurality of substrate bias self-adjusting MIS transistors. Therefore, the oscillation frequency of the ring oscillator is quickly stabilized, which has the effect of speeding up the operation of the PLL clock generator.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a PLL clock generator according to a first embodiment of the present invention.

2 is a cross-sectional view for explaining the structure and operation of a substrate bias self-adjusting MIS transistor that constitutes the voltage controlled oscillator in the PLL clock generator of FIG.

FIG. 3A is a diagram showing a setting state of a substrate bias Vsub between an operating state and a non-operating (standby) state in a substrate bias self-adjusting MIS transistor, and FIG. 3B is a substrate bias self-adjusting MIS. The figure which shows the change characteristic of the substrate current Isub between an operating state and a non-operating (standby) state in a transistor, FIG. (C) is the substrate between the operating state and a non-operating (standby) state in a substrate bias self-adjusting MIS transistor. Bias Vsub
It is a figure which shows the change characteristic of.

FIG. 4 is a diagram showing a gate voltage dependency of a drain current and a substrate current in a substrate bias self-adjusting MIS transistor.

FIG. 5 is a sectional view showing the structure of a substrate bias self-adjusting MIS transistor which constitutes a voltage controlled oscillator in a PLL clock generator according to a second embodiment of the present invention.

FIG. 6 is a resistance value Re of a resistor in a current-voltage characteristic when a substrate bias Vsub in a substrate bias self-adjusting MIS transistor follows a substrate current Isub.
It is a figure which shows xt dependence.

FIG. 7 is a resistance value Rex of a resistor in a saturation current characteristic when a substrate bias Vsub in a substrate bias self-adjusting MIS transistor follows a substrate current Isub.
It is a figure which shows t dependence.

FIG. 8 is a diagram showing changes in drain current characteristics with respect to changes in substrate bias of a general MOS transistor.

FIG. 9 is a diagram showing a change characteristic of a threshold voltage with respect to a change of a substrate bias of a general MOS transistor.

FIG. 10 is a diagram showing a circuit configuration of a general ring oscillator.

11 is a diagram showing the circuit configuration of the ring oscillator of FIG. 10 in more detail.

[Explanation of symbols]

1 Phase Comparator 2 Low-pass Filter 3 Voltage Controlled Oscillator 4 Resistor 10 PLL Oscillator 20 Substrate Bias Generation Circuit 21 Semiconductor Substrate 22 Gate 23 Gate Oxide Film 24 Source 25 Drain 26 LOCOS Film 27 Bias Voltage Application Terminal 28 Resistance Layer 50 Power Supply Voltage application terminal 51 Output terminals 52-56 Inverters 52a, 53a, 54a, 55a, 56a P-channel transistors 52b, 53b, 54b, 55b, 56b P-channel transistors

Continuation of front page (51) Int.Cl. ⁷ identification code FI H03L 7/099 (58) Fields investigated (Int.Cl. ⁷ , DB name) H03K 3/354 H01L 21/822 H01L 27/04 H01L 29 / 78 H03K 19/0948 H03L 7/099

Claims (4)

(57) [Claims] 1. A plurality of MISs (metal-insulator-semico)
In the semiconductor device in which a ring-type oscillator is configured by a transistor, a bias is applied to the substrate portion of the plurality of MIS transistors via a resistor, and the substrate bias is different between operating and non-operating. A semiconductor device comprising a substrate bias self-adjusting MIS transistor that changes in a self-adjusting manner. 2. The plurality of substrate bias self-adjusting MIS transistors forming the ring oscillator are those to which the bias is applied to the respective substrate portions via the same resistor. 1. The semiconductor device according to 1. 3. The plurality of substrate bias self-adjusting MIS transistors forming the ring oscillator are each configured such that the bias is applied to each of the substrate portions via a dedicated resistor. 1. The semiconductor device according to 1. 4. A semiconductor device in which the ring oscillator according to claim 1 or 2 is incorporated in a voltage controlled oscillator of a PLL (phase locked loop) clock generator.