JP3518318B2 - Stacked voltage measurement device - Google Patents
Stacked voltage measurement deviceInfo
- Publication number
- JP3518318B2 JP3518318B2 JP05468998A JP5468998A JP3518318B2 JP 3518318 B2 JP3518318 B2 JP 3518318B2 JP 05468998 A JP05468998 A JP 05468998A JP 5468998 A JP5468998 A JP 5468998A JP 3518318 B2 JP3518318 B2 JP 3518318B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- capacitor
- multiplexer
- switch
- measuring device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
- G01R31/389—Measuring internal impedance, internal conductance or related variables
Landscapes
- Measurement Of Current Or Voltage (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
- Electronic Switches (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は直列接続された電圧
源の個々の電圧を絶縁計測する積層電圧計測装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated voltage measuring device for insulation-measuring individual voltages of voltage sources connected in series.
【０００２】[0002]
【従来の技術】電気自動車などの数百Ｖの高出力電源
は、ニッケル水素蓄電池のような２次電池を多数個直列
接続して構成される。直列接続された電池は充放電制御
のために個々の電池の能力の状態を監視する必要があ
る。具体的には240セルの直列電池で288Ｖの総電圧が得
られるが、個々の電池を監視するのは物量的に困難なた
め10セルで１モジュールとしモジュール単位即ち24個の
モジュール毎の電圧を計測している例がある。（特開平
８−１４０２０４4号公報参照）電気自動車において高
電圧系統は危険防止のためシャーシから絶縁されてい
る。一方、充放電を制御するプロセッサはシャーシが基
準電位であるため前記電池の電圧は絶縁的に計測される
必要がある。前記の例においては個々のモジュール毎に
オペアンプ、ADコンバータ、フォトカップラ、電源等を
含む絶縁回路ユニットを備えており、非常に複雑となっ
ていた。2. Description of the Related Art A high output power source of several hundreds of volts for an electric vehicle is constructed by connecting a large number of secondary batteries such as nickel-hydrogen storage batteries in series. For batteries connected in series, it is necessary to monitor the state of capacity of each battery for charge / discharge control. Specifically, a total voltage of 288V can be obtained with a 240-cell series battery, but since it is physically difficult to monitor each battery, one cell is defined as 10 cells, and the voltage of each module, that is, every 24 modules, is set. There is an example of measurement. In the electric vehicle, the high voltage system is insulated from the chassis to prevent danger. On the other hand, in the processor that controls charge / discharge, the voltage of the battery needs to be measured in an insulating manner because the chassis has a reference potential. In the above example, each module is provided with an insulating circuit unit including an operational amplifier, an AD converter, a photocoupler, a power supply, etc., which is very complicated.
【０００３】センサ等の出力電圧を絶縁的に計測する方
式としてフライング・キャパシタ回路が知られている。
図13にフライング・キャパシタ方式による従来のマルチ
プレクサの構成例（特開平９−１６１７号公報参照）を
示しており、それぞれスイッチ23,33,43を開いた状態で
スイッチ21,31,41を閉じることによりセンサ等の電圧源
20,30,40の電圧をコンデンサ22,32,42に充電し、次にそ
れぞれスイッチ21,31,41を開いた状態でスイッチ23,33,
43を順次走査（マルチプレックス）することによりコン
デンサ22,32,42の端子電圧をADコンバータ24で計測す
る。このような各スイッチ動作の位相関係により各電圧
源と計測回路の絶縁性が確保される。A flying capacitor circuit is known as a method of insulatingly measuring the output voltage of a sensor or the like.
FIG. 13 shows a configuration example of a conventional multiplexer using the flying capacitor system (see Japanese Patent Application Laid-Open No. 9-1617), in which the switches 23, 33, 43 are opened and the switches 21, 31, 41 are closed. Voltage source such as sensor
Charge the capacitors 20, 32, 42 with the voltage of 20, 30, 40, and then switch 23, 33, with the switches 21, 31, 41 open.
The terminal voltages of the capacitors 22, 32 and 42 are measured by the AD converter 24 by sequentially scanning (multiplexing) 43. Due to such a phase relationship of each switch operation, insulation between each voltage source and the measurement circuit is secured.
【０００４】[0004]
【発明が解決しようとする課題】従来の技術で説明した
電気自動車の電池のモジュール電圧の計測に図12のフラ
イング・キャパシタ方式の回路構成をとれば回路がかな
り簡単になる。しかし、24のモジュールに対し高価な高
耐圧の絶縁駆動型アナログスイッチ素子を計96個も使用
するというのはコスト、サイズ、信頼性などの面で更な
る改善が必要である。If the circuit configuration of the flying capacitor system shown in FIG. 12 is used for measuring the module voltage of the battery of the electric vehicle described in the prior art, the circuit becomes considerably simple. However, using a total of 96 high-voltage insulation drive type analog switch elements with high withstand voltage for 24 modules requires further improvements in terms of cost, size, and reliability.
【０００５】本発明は、従来の積層電圧計測装置の構成
を更に簡素化することを目的とする。An object of the present invention is to further simplify the structure of a conventional laminated voltage measuring device.
【０００６】[0006]
【課題を解決するための手段】この課題を解決するため
に本発明は、直列接続されたＮ個の電圧源に接続された
（Ｎ＋１）個の電圧検出端子と、コンデンサと、奇数番
目の前記電圧検出端子を前記コンデンサの一方の端子に
選択的に接続する第一のマルチプレクサと、偶数番目の
前記電圧検出端子を前記コンデンサの他方の端子に選択
的に接続する第２のマルチプレクサと、電圧計測回路
と、前記コンデンサの両端子を前記電圧計測回路に接続
するサンプルスイッチと、奇数番目の前記電圧源と偶数
番目の前記電圧源の検出電圧極性を揃える極性補正手段
とを備えたものである。In order to solve this problem, the present invention provides (N + 1) voltage detection terminals connected to N voltage sources connected in series, a capacitor, and an odd-numbered one. A first multiplexer for selectively connecting a voltage detection terminal to one terminal of the capacitor, a second multiplexer for selectively connecting the even-numbered voltage detection terminal to the other terminal of the capacitor, and voltage measurement A circuit, a sample switch for connecting both terminals of the capacitor to the voltage measuring circuit, and a polarity correcting means for aligning the detected voltage polarities of the odd-numbered voltage source and the even-numbered voltage source.
【０００７】[0007]
【発明の実施の形態】以下、本発明の実施の形態につい
て、図１から図12を用いて説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS. 1 to 12.
【０００８】（実施の形態１）図１は本発明の一実施の
形態による積層電圧計測装置の構成を示し、電圧源の数
（Ｎ）を５個として説明する。直列接続された電圧源V1
〜V5は電圧検出端子T1〜T6からスイッチS1,S3,S5から成
る第一のマルチプレクサ１およびスイッチS2,S4,S6から
成る第２のマルチプレクサ２を経由してコンデンサ３に
接続され、さらにコンデンサ３はスイッチ4a,4bから成
るサンプルスイッチ４を経由して電圧計測回路５に接続
されている。(Embodiment 1) FIG. 1 shows the configuration of a laminated voltage measuring device according to an embodiment of the present invention, and the number of voltage sources (N) will be described as five. Voltage source V1 connected in series
˜V5 is connected to the capacitor 3 from the voltage detection terminals T1 to T6 via the first multiplexer 1 composed of the switches S1, S3, S5 and the second multiplexer 2 composed of the switches S2, S4, S6, and further to the capacitor 3 Is connected to the voltage measuring circuit 5 via a sample switch 4 including switches 4a and 4b.
【０００９】図２は本発明の実施例の動作を説明するた
めの各スイッチの開閉タイミングを示し、図２に基づい
て図１の動作を説明する。各スイッチ素子は開いた状態
を基準とし、期間P1において、スイッチS1とS2を閉じれ
ば電圧源V1の電圧がコンデンサ３に充電され、次にスイ
ッチS1とS2を開いた後サンプルスイッチ４を閉じると電
圧計測回路５にコンデンサ３の充電電圧即ち電圧源V1の
電圧が入力される。各スイッチの駆動回路とスイッチの
接点は当然のことながら絶縁が保たれているとして、マ
ルチプレクサ１，２とサンプルスイッチ４は同時に閉じ
ないため電圧源Vと電圧は絶縁的に計測される。同様
に、期間P2でスイッチS2とS3を、期間P3でS3とS4をとい
う具合に順次マルチプレックスしていく。FIG. 2 shows the opening / closing timing of each switch for explaining the operation of the embodiment of the present invention, and the operation of FIG. 1 will be explained based on FIG. Each switch element is based on the open state, and in the period P1, when the switches S1 and S2 are closed, the voltage of the voltage source V1 is charged in the capacitor 3, and when the sample switches 4 are closed after opening the switches S1 and S2. The charging voltage of the capacitor 3, that is, the voltage of the voltage source V1 is input to the voltage measuring circuit 5. As a matter of course, the drive circuit of each switch and the contact point of the switch are kept insulated. Since the multiplexers 1 and 2 and the sample switch 4 are not closed at the same time, the voltage source V and the voltage are measured in an insulated manner. Similarly, switches S2 and S3 are sequentially multiplexed in period P2, and S3 and S4 are sequentially multiplexed in period P3.
【００１０】ここで図１において注意すべきことは、奇
数番目の電圧源に対して偶数番目の電圧源の電圧が極性
反転して電圧計測回路５に入力されることである。この
ための極性補正手段６の一実施例を図３に示す。極性補
正手段６よく知られた絶対値回路で電圧計測回路５のＡ
Ｄコンバータに入力される電圧極性を揃える役割をし、
電池の様な単極性の電圧源Vに対して有効である。極性
補正手段６はこの様なアナログ回路でなく、両極入力の
ＡＤコンバータの極性出力ビットを無視するようなデジ
タル回路であっても良い。Here, it should be noted that in FIG. 1, the voltages of the even-numbered voltage sources are inverted in polarity with respect to the odd-numbered voltage sources and are input to the voltage measuring circuit 5. An embodiment of the polarity correction means 6 for this purpose is shown in FIG. Polarity correction means 6 A of the voltage measuring circuit 5 is a well-known absolute value circuit.
It plays the role of aligning the voltage polarities input to the D converter,
It is effective for a unipolar voltage source V such as a battery. The polarity correction means 6 may not be such an analog circuit, but may be a digital circuit that ignores the polarity output bit of the AD converter with bipolar input.
【００１１】（実施の形態２）図４は本発明の極性補正
手段６の別の実施例であり、図１のサンプルスイッチ４
に極性反転スイッチ4c,4dを加えた構成で、スイッチ4a,
4bを図２のSSPのタイミングでスイッチ4c,4dをSSNのタ
イミングで開閉して極性補正が行われる。(Embodiment 2) FIG. 4 shows another embodiment of the polarity correcting means 6 of the present invention, which is the sample switch 4 of FIG.
Polarity reversing switches 4c and 4d are added to switch 4a,
Polarity correction is performed by opening / closing switch 4c and 4d at the timing of SSP in FIG. 2 and at the timing of SSN in FIG.
【００１２】（実施の形態３）図５は本発明の極性補正
手段のさらに別の実施例であり、極性補正手段６はコン
デンサ３のまえに設けられた極性選択スイッチ７であ
る。スイッチ7a,7bを図２のMUPのタイミングでスイッチ
7c,7dをMUNのタイミングで開閉して極性補正が行われ
る。この場合は、前の実施例と比べて単極性の電圧源V
に対してコンデンサ５は単極性用で済む特徴がある。(Third Embodiment) FIG. 5 shows still another embodiment of the polarity correcting means of the present invention. The polarity correcting means 6 is a polarity selecting switch 7 provided before the capacitor 3. Switch 7a and 7b at the timing of MUP in Fig. 2.
Polarity correction is performed by opening and closing 7c and 7d at the timing of MUN. In this case, a unipolar voltage source V
On the other hand, the capacitor 5 is characterized in that it is sufficient for unipolarity.
【００１３】（実施の形態４）図６は電圧計測における
コモンモード誤差を説明する図であり、電圧源V（図に
おいてはゼロVoltとしている）が電圧計測回路５の基準
電位（図における接地電位）に対してコモンモード電圧
Enを持っており、マルチプレクサ１，２の閉動作でコン
デンサ３の端子電圧がゼロVoltになり、マルチプレクサ
１，２を開いた後にサンプルスイッチ４を閉じた状態を
示している。オン抵抗の低い半導体スイッチはオフ時の
寄生容量が比較的大きく、図のようにオフ状態のスイッ
チS1〜S6はコンデンサで、オン状態のスイッチ4a,4bは
抵抗で表現できる。サンプルスイッチ４が閉じる直前で
は、コンデンサ３の両端子の電位はそれぞれEnであり各
スイッチS1〜S6のオフ容量に蓄えられた電荷はゼロであ
る。その後、サンプルスイッチが閉じられるとコンデン
サ３の両端子の電位は接地電位に向かう変化をする。こ
の間各スイッチS1〜S6のオフ容量に対する電荷の移動に
伴うリーク電流Ia,Ibが発生する。電流IaとIbは対照で
同じ値であるが、図６に示した電圧計測回路５では流れ
る経路が非対称で電流Iaはコンデンサ３を経由して接地
電位に落ちる。この影響でコンデンサ３にオフセット電
圧が発生して計測誤差の要因になる。このコモンモード
誤差は絶縁された電圧源Vに乗った外来ノイズのみなら
ず本来の直列接続による各電圧源自身の電位の違いによ
って生ずる問題であり、特に多数の電圧源を計測する構
成ではマルチプレクサを構成する多数のスイッチの並列
オフ容量により問題が大きかった。(Embodiment 4) FIG. 6 is a diagram for explaining a common mode error in voltage measurement, in which a voltage source V (zero Volt in the drawing) is a reference potential of the voltage measuring circuit 5 (ground potential in the drawing). ) Common mode voltage
En is held, the terminal voltage of the capacitor 3 becomes zero Volt by the closing operation of the multiplexers 1 and 2, and the sample switch 4 is closed after the multiplexers 1 and 2 are opened. A semiconductor switch having a low on-resistance has a relatively large parasitic capacitance when it is turned off. As shown in the figure, the off-state switches S1 to S6 can be expressed by capacitors and the on-state switches 4a and 4b can be expressed by resistors. Immediately before the sample switch 4 is closed, the potentials at both terminals of the capacitor 3 are En and the electric charges stored in the off capacitances of the switches S1 to S6 are zero. After that, when the sample switch is closed, the potentials of both terminals of the capacitor 3 change toward the ground potential. During this time, leak currents Ia and Ib are generated due to the movement of charges with respect to the off capacitances of the switches S1 to S6. The currents Ia and Ib have the same value in contrast, but in the voltage measuring circuit 5 shown in FIG. Due to this influence, an offset voltage is generated in the capacitor 3 and causes a measurement error. This common-mode error is a problem caused not only by external noise on the insulated voltage source V but also by the difference in the potential of each voltage source itself due to the original series connection. The problem was large due to the parallel off-capacitance of a large number of switches.
【００１４】図７はコモンモード誤差を低減するための
本発明の一実施形態を示し、マルチプレクサ１とコンデ
ンサ３の間に図２のMUBのタイミングで開閉するスイッ
チ８を設けている。従来例で示した24個のモジュール電
圧源の場合、マルチプレクサ１の13個の並列オフ容量が
スイッチ８の１個分のオフ容量と直列になるためコモン
モード誤差を約13分の１に低減できる。FIG. 7 shows an embodiment of the present invention for reducing the common mode error, and a switch 8 which opens and closes at the timing of the MUB of FIG. 2 is provided between the multiplexer 1 and the capacitor 3. In the case of the 24 module voltage sources shown in the conventional example, the 13 parallel off-capacitances of the multiplexer 1 are in series with the off-capacitance of one switch 8 so that the common mode error can be reduced to about 1/3. .
【００１５】（実施の形態５）図８はコモンモード誤差
を低減するための本発明の別の実施形態を示し、電圧計
測回路５は差動入力型であり、図１におけるコンデンサ
３を２個の直列コンデンサ3a,3bで構成するとともにそ
の中間点と接地電位の間にサンプルスイッチ４と同じタ
イミングで開閉するスイッチ９を設けている。図６での
説明と同様に発生するリーク電流Ia,Ibはそれぞれコン
デンサ3a,3bを経由し、スイッチ９を通して接地電位に
落ちる。図８に示した電流の向きの場合、リーク電流Ia
はコンデンサ3aに正のオフセット電圧をリーク電流Ibは
コンデンサ3bに負のオフセット電圧をそれぞれ発生させ
る。これらのオフセット電圧は、回路の対照性により絶
対値が等しく、電圧計測回路５の差動特性でキャンセル
されるためコモンモード誤差は原理的に発生しない。(Fifth Embodiment) FIG. 8 shows another embodiment of the present invention for reducing a common mode error. The voltage measuring circuit 5 is a differential input type, and two capacitors 3 in FIG. And a switch 9 that opens and closes at the same timing as the sample switch 4 is provided between the midpoint of the series capacitors 3a and 3b and the ground potential. The leak currents Ia and Ib generated similarly to the description in FIG. 6 pass through the capacitors 3a and 3b, respectively, and fall to the ground potential through the switch 9. In the case of the current direction shown in FIG. 8, the leakage current Ia
Generates a positive offset voltage in the capacitor 3a, and the leak current Ib generates a negative offset voltage in the capacitor 3b. These offset voltages have the same absolute value due to the contrast of the circuits, and are canceled by the differential characteristics of the voltage measuring circuit 5, so in principle no common mode error occurs.
【００１６】（実施の形態６）図９はコモンモード誤差
を更に低減するための本発明の別の実施形態を示し、図
８の構成に対しそれぞれマルチプレクサ１，２とコンデ
ンサ3a,3bの間に更に図２のMUBのタイミングで開閉する
スイッチ8a,8bを設けている。図８の説明での回路の対
照性はそれぞれマルチプレクサ１，２の並列オフ容量値
およびコンデンサ3a,3bの容量値の対照性に係わるわけ
であるが、実際の部品にはバラツキがあるためキャンセ
ル誤差が残る。キャンセル誤差を低減するには、部品そ
のものの精度を上げるより回路構成的に原因となるリー
ク電流を減らすのが得策である。スイッチ8a,8bを設け
ることにより図７におけるスイッチ８と同様の効果で図
８の実際的な構成で発生するコモンモード誤差を更に低
減できる。(Embodiment 6) FIG. 9 shows another embodiment of the present invention for further reducing the common mode error. Between the multiplexers 1 and 2 and the capacitors 3a and 3b, respectively, in the configuration of FIG. Furthermore, switches 8a and 8b that open and close at the timing of the MUB in FIG. 2 are provided. The circuit contrast in the description of FIG. 8 is related to the parallel off capacitance values of the multiplexers 1 and 2 and the capacitance values of the capacitors 3a and 3b, respectively. Remains. In order to reduce the cancellation error, it is a good idea to reduce the leakage current that causes the circuit configuration rather than increase the accuracy of the components themselves. By providing the switches 8a and 8b, the common mode error generated in the practical configuration of FIG. 8 can be further reduced by the same effect as the switch 8 in FIG.
【００１７】（実施の形態７）図10は電圧源Vの各電圧
とともに直列接続された合計電圧を計測するための本発
明の一実施形態を示し、図１の積層電圧計測装置の構成
に加えて、直列接続された電圧源Vの両端の電圧をスイ
ッチ10を介して抵抗分圧器11に導きスイッチ12とスイッ
チS6でマルチプレックスする構成としている。抵抗分圧
器11の分圧比をＮ：１にとると計測レンジ上都合が良
く、また計測時以外はスイッチ10を開状態にすることに
より省電力化がはかれる。(Embodiment 7) FIG. 10 shows an embodiment of the present invention for measuring the total voltage connected in series together with each voltage of the voltage source V. In addition to the configuration of the laminated voltage measuring device of FIG. The voltage across the voltage source V connected in series is led to the resistance voltage divider 11 via the switch 10 and multiplexed by the switch 12 and the switch S6. It is convenient for the measurement range to set the voltage division ratio of the resistance voltage divider 11 to N: 1, and power saving can be achieved by opening the switch 10 except during measurement.
【００１８】（実施の形態８）図11は高周波ノイズの影
響を低減できる本発明の一実施形態を示し、図１の構成
に加えて、マルチプレクサ１とコンデンサ３の間に抵抗
器13を設けている。本発明の主な利用対象である高出力
積層電池電源の負荷の殆どはモーターや照明装置を駆動
するインバータ装置である。このインバータ系には数キ
ロヘルツ以上の繰り返しの多位相の急峻なパルスノイズ
が散在し負荷電流を介して電池の検出電圧にも現れる。
マルチプレクサ１，３によってコンデンサ３にこのパル
スノイズを含めて検出電圧がトラックホールドされると
必要な計測精度に誤差を与えるため対策が必要である。
図11の抵抗器13はコンデンサ３に対して高周波応答低減
の時定数を与える。抵抗器はコンデンサ３より前であれ
ばどこでも良いがこの位置では数が少なくて済む。回路
を対照的にする場合はマルチプレクサ２とコンデンサ３
の間にも同様に抵抗器を設ければよい。(Embodiment 8) FIG. 11 shows an embodiment of the present invention capable of reducing the influence of high frequency noise. In addition to the configuration of FIG. 1, a resistor 13 is provided between the multiplexer 1 and the capacitor 3. There is. Most of the loads of the high-power laminated battery power source, which is the main target of the present invention, are inverter devices that drive motors and lighting devices. Repeated multiphase steep pulse noise of several kilohertz or more is scattered in this inverter system and appears in the detection voltage of the battery via the load current.
If the multiplexer 3 and 3 track-hold the detected voltage including this pulse noise in the capacitor 3, an error will occur in the required measurement accuracy, and a countermeasure is required.
The resistor 13 in FIG. 11 gives the capacitor 3 a time constant for reducing the high frequency response. The resistor may be anywhere before the capacitor 3, but the number is small at this position. Multiplexer 2 and capacitor 3 for contrasting circuits
A resistor may be similarly provided between the two.
【００１９】（実施の形態９）図12に本発明の実施に好
適なスイッチ素子の例を示す。このＬＥＤ14の光で光電
素子15を介してＭＯＳトランジスタを開閉する構成のス
イッチ素子は駆動側との光絶縁効果、高オフ耐圧・低オ
ン抵抗のスイッチ特性などに優れ、欠点である高オフ容
量は本発明で対策できるため実用性が高い。(Embodiment 9) FIG. 12 shows an example of a switch element suitable for implementing the present invention. The switching element configured to open and close the MOS transistor by the light of the LED 14 through the photoelectric element 15 is excellent in the optical insulation effect with the driving side, the high off-breakdown voltage and the low on-resistance switch characteristics, and the high off-capacitance which is a defect is It is highly practical because it can be taken by the present invention.
【００２０】[0020]
【発明の効果】以上のように本発明によれば、極めて簡
素な回路構成で高精度の絶縁計測が可能な積層電圧計側
装置が実現できるという顕著な効果が得られる。As described above, according to the present invention, a remarkable effect that a laminated voltmeter side device capable of performing highly accurate insulation measurement with an extremely simple circuit configuration can be realized.
【図１】本発明の一実施の形態による積層電圧計測装置
の構成図FIG. 1 is a configuration diagram of a laminated voltage measuring device according to an embodiment of the present invention.
【図２】本発明の各実施例におけるスイッチの開閉タイ
ミング図FIG. 2 is a timing chart of switch opening / closing in each embodiment of the present invention.
【図３】本発明の一実施の形態による積層電圧計測装置
の部分構成図FIG. 3 is a partial configuration diagram of a laminated voltage measuring device according to an embodiment of the present invention.
【図４】本発明の一実施の形態による積層電圧計測装置
の部分構成図FIG. 4 is a partial configuration diagram of a laminated voltage measuring device according to an embodiment of the present invention.
【図５】本発明の一実施の形態による積層電圧計測装置
の部分構成図FIG. 5 is a partial configuration diagram of a laminated voltage measuring device according to an embodiment of the present invention.
【図６】電圧計測におけるコモンモード誤差の説明図FIG. 6 is an explanatory diagram of a common mode error in voltage measurement.
【図７】本発明の一実施の形態による積層電圧計測装置
の構成図FIG. 7 is a configuration diagram of a laminated voltage measuring device according to an embodiment of the present invention.
【図８】本発明の一実施の形態による積層電圧計測装置
の構成図FIG. 8 is a configuration diagram of a laminated voltage measuring device according to an embodiment of the present invention.
【図９】本発明の一実施の形態による積層電圧計測装置
の構成図FIG. 9 is a configuration diagram of a laminated voltage measuring device according to an embodiment of the present invention.
【図１０】本発明の一実施の形態による積層電圧計測装
置の構成図FIG. 10 is a configuration diagram of a laminated voltage measuring device according to an embodiment of the present invention.
【図１１】本発明の一実施の形態による積層電圧計測装
置の構成図FIG. 11 is a configuration diagram of a laminated voltage measuring device according to an embodiment of the present invention.
【図１２】本発明の一実施の形態によるスイッチ素子の
構成図FIG. 12 is a configuration diagram of a switch element according to an embodiment of the present invention.
【図１３】従来のフライング・キャパシタ回路の構成図FIG. 13 is a configuration diagram of a conventional flying capacitor circuit.
V 複数の電圧源 T1〜T6 電圧検出端子 1 第１のマルチプレクサ 2 第2のマルチプレクサ 3 コンデンサ 4 サンプルスイッチ 5 電圧計測回路 6 極性補正手段 V Multiple voltage sources T1 to T6 voltage detection terminals 1 First multiplexer 2 Second multiplexer 3 capacitor 4 sample switch 5 Voltage measurement circuit 6 Polarity correction means
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) G01R 19/00 - 19/32 H03K 17/00 ─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. 7 , DB name) G01R 19/00-19/32 H03K 17/00
Claims (11)
（Ｎ＋１）個の電圧検出端子と、コンデンサと、奇数番
目の前記電圧検出端子を前記コンデンサの一方の端子に
選択的に接続する第一のマルチプレクサと、偶数番目の
前記電圧検出端子を前記コンデンサの他方の端子に選択
的に接続する第２のマルチプレクサと、電圧計測回路
と、前記コンデンサの両端子を前記電圧計測回路に接続
するサンプルスイッチと、奇数番目の前記電圧源と偶数
番目の前記電圧源の検出電圧極性を揃える極性補正手段
とを備え、前記サンプルスイッチを開いた状態で前記マ
ルチプレクサにより所望の電圧源を選択した後に前記マ
ルチプレクサを開いて前記サンプルスイッチを閉じる動
作を繰り返すことにより前記電圧源の各電圧を計測する
ことを特徴とする積層電圧計測装置。1. A (N + 1) number of voltage detection terminals connected to N number of voltage sources connected in series, a capacitor, and an odd-numbered voltage detection terminal are selectively connected to one terminal of the capacitor. And a second multiplexer for selectively connecting the even voltage detection terminals to the other terminal of the capacitor, a voltage measuring circuit, and both terminals of the capacitor connected to the voltage measuring circuit. A sample switch, and polarity correction means for aligning the detection voltage polarities of the odd-numbered voltage sources and the even-numbered voltage sources, and after selecting the desired voltage source by the multiplexer with the sample switch open. A product characterized by measuring each voltage of the voltage source by repeating an operation of opening the multiplexer and closing the sample switch. Voltage measuring device.
記載の積層電圧計測装置。2. The polarity correcting means is an absolute value circuit.
The laminated voltage measuring device described.
ンプルスイッチである請求項１記載の積層電圧計測装
置。3. The laminated voltage measuring device according to claim 1, wherein the polarity correcting means is a sample switch having a polarity selecting function.
サの間に設けられたマルチプレクサと同様のタイミング
で開閉する極性選択スイッチである請求項１記載の積層
電圧計測装置。4. The laminated voltage measuring device according to claim 1, wherein the polarity correction means is a polarity selection switch that opens and closes at the same timing as the multiplexer provided between the multiplexer and the capacitor.
プレクサと同様のタイミングで開閉するスイッチを備え
る請求項１記載の積層電圧計測装置。5. The laminated voltage measuring device according to claim 1, further comprising a switch that opens and closes at the same timing as the multiplexer between the multiplexer and the capacitor.
ンサ素子から成り、それらの中間接続点と電圧計測回路
の基準電位の間にサンプルスイッチと同様のタイミング
で開閉するスイッチを備え、電圧計測回路が差動入力型
であることを特徴とする請求項１記載の積層電圧計測装
置。6. A voltage measuring circuit comprising a capacitor composed of two capacitor elements connected in series, and a switch which opens and closes at the same timing as a sample switch between an intermediate connection point between them and a reference potential of the voltage measuring circuit. 2. The laminated voltage measuring device according to claim 1, wherein is a differential input type.
プレクサと同様のタイミングで開閉する１対のスイッチ
を備える請求項６記載の積層電圧計測装置。7. The laminated voltage measuring device according to claim 6, further comprising a pair of switches between the multiplexer and the capacitor, the switches being opened and closed at the same timing as the multiplexer.
を抵抗分圧する分圧器と、前記分圧器の出力電圧を取り
込むマルチプレクサを備えることを特徴とする請求項１
記載の積層電圧計測装置。8. A voltage divider for resistance-dividing the voltage across the N voltage sources connected in series, and a multiplexer for taking in the output voltage of the voltage divider.
The laminated voltage measuring device described.
回路を分離するスイッチを備える請求項８記載の積層電
圧計測装置。9. The laminated voltage measuring device according to claim 8, further comprising a switch between the voltage source and the voltage divider, the switch separating the circuit when the voltage division is unnecessary.
器を備える請求項１記載の積層電圧計測装置。10. The laminated voltage measuring device according to claim 1, further comprising a resistor provided between the multiplexer and the capacitor.
ＭＯＳトランジスタのゲートを光絶縁駆動する半導体リ
レー素子であることを特徴とする請求項１〜10の何れか
に記載の積層電圧計測装置。11. The laminated voltage measuring device according to claim 1, wherein the analog switch element that constitutes the device is a semiconductor relay element that optically drives the gate of the MOS transistor.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05468998A JP3518318B2 (en) | 1998-03-06 | 1998-03-06 | Stacked voltage measurement device |
| EP99907870A EP0990913B1 (en) | 1998-03-06 | 1999-03-05 | Voltage measuring instrument with flying capacitor |
| DE69937220T DE69937220T2 (en) | 1998-03-06 | 1999-03-05 | VOLTAGE MEASURING DEVICE WITH FLYING CAPACITOR |
| PCT/JP1999/001075 WO1999045402A1 (en) | 1998-03-06 | 1999-03-05 | Voltage measuring instrument with flying capacitor |
| US09/403,512 US6362627B1 (en) | 1998-03-06 | 1999-03-05 | Voltage measuring instrument with flying capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05468998A JP3518318B2 (en) | 1998-03-06 | 1998-03-06 | Stacked voltage measurement device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11248755A JPH11248755A (en) | 1999-09-17 |
| JP3518318B2 true JP3518318B2 (en) | 2004-04-12 |
Family
ID=12977775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05468998A Expired - Fee Related JP3518318B2 (en) | 1998-03-06 | 1998-03-06 | Stacked voltage measurement device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3518318B2 (en) |
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| JP4557407B2 (en) * | 2000-10-31 | 2010-10-06 | パナソニック株式会社 | Laminate voltage measuring device |
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| JP4210030B2 (en) | 2000-11-02 | 2009-01-14 | パナソニック株式会社 | Laminate voltage measuring device |
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- 1998-03-06 JP JP05468998A patent/JP3518318B2/en not_active Expired - Fee Related
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