JP3512641B2 - Level shift circuit and semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit that shifts the voltage level of an input signal, and more particularly, to a level shift circuit.
This is intended for the case where a small amplitude input signal of V or 15V is level-shifted to a large amplitude signal of several tens to several hundreds V.

[0002]

2. Description of the Related Art When a voltage amplitude of an input signal is level-shifted to a large voltage amplitude, a logical change point (a rising edge or a falling edge) of the input signal is detected to level-shift in order to suppress current consumption. A level shift circuit is known in which a current flows only at a logic change point.

FIG. 3 is a block diagram showing the configuration of a level shift circuit and its peripheral portion in a conventional bootstrap type half bridge driver circuit of this type. The circuit of FIG. 3 includes a rising edge signal output circuit 1, a falling edge signal output circuit 2, and a high side driver 3.
, High-side driver control circuit 4, and capacitor C
1, a bootstrap diode D1, a low side driver 5, and a low side driver control circuit 6.

Each of the edge signal output circuits 1 and 2 shown in FIG.
Is the edge detection circuit 11 as shown in the detailed configuration of FIG.
, An inverter IV1, an nMOS transistor Q1, a resistor R1, and a level shift pulse receiving circuit 12.
The edge detection circuit 11, the inverter IV1 and the nMOS transistor Q1 operate by being supplied with the power supply voltage from the low side power supply (low voltage power supply of about 5V or 15V) line L1, and the level shift pulse receiving circuit 12 operates by the high side power supply ( It operates by being supplied with a power supply voltage from a high voltage power supply (line of several hundred V) line L2.

The common voltage (ground voltage) is always constant below the dotted line in FIG. 4 (hereinafter referred to as the low side), while above the dotted line (hereinafter referred to as the high side). , The common voltage (ground voltage) fluctuates with large amplitude. More specifically, the common voltage on the high side is the same voltage as the drive output of the high side driver 3, and varies greatly according to the voltage of the drive output.

The edge detection circuit 11 shown in FIG.
The rising edge or falling edge included in is detected and an edge detection pulse is output. Inverter IV1
Is composed of a pMOS transistor Q2 and an nMOS transistor Q3, and inverts and outputs an edge detection pulse. Inverter
The output of IV1 is input to the gate terminal of the nMOS transistor Q1.

When the edge detection circuit 11 detects an edge, the nMOS transistor Q1 turns on, and a current flows from the high side power supply line L2 through the resistor R1 to the low side common line. This current causes a potential difference across the resistor R1. This potential difference is detected by the level shift pulse receiving circuit 12, and the high side driver control circuit 4 drives the high side driver 3 in accordance with the detected potential difference.

The capacitor C1 shown in FIGS. 3 and 4 is connected between the high-side common line and the high-side power supply line L2, and charges and discharges in accordance with the drive output of the high-side driver 3. Specifically, when the drive output is low level, the capacitor C1 is charged by the current from the low side power supply line L1, and when the drive output is high level, the discharge current from the capacitor C1 is supplied to the high side power supply line L2. Supplied.

The bootstrap diode D1 prevents current from flowing backward so that the current from the high side power supply line L2 does not flow into the low side power supply line L1.
The high-side driver control circuit 4 has a latch circuit 21 and a gate signal generation circuit 22, as shown in FIG. The latch circuit 21 performs a latch operation according to the output signal of the level shift pulse receiving circuit 12 in each of the edge signal output circuits 1 and 2, and the input signal IN input to the circuit of FIG.
It outputs signals with the same frequency but different voltage amplitudes. The gate signal generation circuit 22 generates a gate signal for driving the high side driver 3 based on the output of the latch circuit 21.

[0010]

In the circuits of FIGS. 3 and 4, when the high-side driver 3 is turned on and off while the nMOS transistor Q1 is off, the common voltage on the high side changes accordingly. Then, the displacement current flows to the low side through the resistor R1. This current flows to the nMOS transistor Q3 in the inverter IV1 via the drain-gate capacitance of the nMOS transistor Q1. Therefore, when the current capacity of the inverter IV1 is not sufficient, the nMOS transistor Q3 is destroyed, the nMOS transistor Q3 and the pMOS transistor Q2 latch up, and the gate voltage of the nMOS transistor Q1 rises.
If the nMOS transistor Q1 malfunctions or a gate voltage higher than the breakdown voltage is applied to the nMOS transistor Q1,
The transistor Q1 may be destroyed. Further, in order to secure a sufficient current capacity of the nMOS transistor Q3, the size of the transistor must be increased, which makes it difficult to achieve high integration.

Further, if the level shift circuit of FIG. 3 is formed by using a thin film process in order to improve the degree of integration, the drain-gate capacitance of each MOS transistor becomes large and the gate breakdown voltage becomes low. growing.

The present invention has been made in view of the above circumstances, and an object thereof is to achieve high integration and a level shift circuit in which a transistor is not destroyed even if a displacement current flows during a level shift. And to provide a semiconductor integrated circuit.

[0013]

In order to solve the above-mentioned problems, the present invention outputs a signal indicating a logical change position of an input signal by receiving a power supply voltage from a low-side power supply and a low-side common power supply. An edge signal output circuit, a first transistor that is turned on / off according to the logic of the output signal of the edge signal output circuit, and a high-side power supply that supplies a power supply voltage to turn on / off the first transistor. A high-side voltage generation circuit that outputs a level shift signal obtained by shifting the voltage level of the input signal in response to turning off, and a load drive circuit that drives a load based on the output of the high-side voltage generation circuit,
A level shift circuit including: a second transistor cascode-connected to the first transistor;
When the first transistor is in the off state, the displacement current flowing in the high side voltage generation circuit according to the fluctuation of the output voltage of the load drive circuit is transferred via the drain-gate capacitance of the second transistor. And a first current path flowing to the low-side power supply side, and the displacement current causes the displacement current to flow between the drain-source capacitance of the second transistor and the drain of the first transistor when the first transistor is off. A second current path that flows to the low-side common power source through the inter-gate capacitance.

Further, according to the present invention, a first edge position signal output circuit for outputting a signal indicating a rising edge position of an input signal and a second edge position signal for outputting a signal indicating a falling edge position of the input signal. An output circuit and the first
And a high side voltage generation circuit that outputs a level shift signal obtained by shifting the voltage level of the input signal based on the output signal of the second edge position signal output circuit, and based on the output of the high side voltage generation circuit In a level shift circuit including a load driving circuit for driving a load, the first edge position signal output circuit receives a power supply voltage from a low-side power supply and a low-side common power supply, thereby rising the input signal. A first edge detection circuit that detects an edge position, a first transistor that is turned on / off according to an output logic of the first edge detection circuit, and a second transistor that is cascode-connected to the first transistor. And a first transistor connected between the output terminal of the second transistor and the high-side power supply.
And a power supply voltage supplied from the high-side power supply, depending on the voltage across the first resistor,
A first level shift pulse output circuit that outputs a signal indicating a rising edge position of the input signal; and the high side according to a change in an output voltage of the load drive circuit when the first transistor is in an off state. A first current path that causes a displacement current flowing from the power source to the resistor to flow to the low-side power source side via the drain-gate capacitance of the second transistor, and the first transistor is in an off state, A second current path for causing a displacement current to flow to the low-side common power supply via the drain-source capacitance of the second transistor and the drain-gate capacitance of the first transistor. The edge position signal output circuit receives the power supply voltage from the low side power supply to detect the falling edge position of the input signal. A second edge detection circuit for outputting, a third transistor that is turned on / off according to an output logic of the second edge detection circuit, a fourth transistor cascode-connected to the third transistor, and Fourth
A second resistor connected between the output end of the transistor and the high-side power supply, and a power supply voltage supplied from the high-side power supply, and the second resistor is connected in accordance with the voltage across the second resistor. A second level shift pulse output circuit that outputs a signal indicating the falling edge position of the input signal, and the displacement current when the third transistor is in the off state, and the displacement between the drain-gate capacitance of the fourth transistor. A third current path flowing to the low-side power supply side through the displacement current and the displacement current to the drain-source capacitance of the fourth transistor and the drain of the third transistor when the first transistor is in an off state. A fourth current path that flows to the low-side common power source via the inter-gate capacitance.

The invention of claim 1 will be described with reference to, for example, FIG. 1 and FIG. 3. The "edge signal output circuit" includes a rising edge signal output circuit 1 and a falling edge signal output circuit 2 and a "first transistor". Is an nMOS transistor Q
1, the "high-side voltage generation circuit" corresponds to the high-side driver control circuit 4, the "load drive circuit" corresponds to the high-side driver 3, and the "second transistor" corresponds to the nMOS transistor Q4.

The invention of claim 2 will be described with reference to, for example, FIGS. 1 and 3, the "first edge signal output circuit" is the rising edge signal output circuit 1, and the "second edge signal output circuit" is the In the falling edge signal output circuit 2, the “first and second edge detection circuits” are the edge detection circuit 11
The "first and third transistors" are nMOS transistors Q1, and the "second and fourth transistors" are nMOS transistors.
In the transistor Q4, the “first and second level shift pulse output circuits” are the level shift pulse receiving circuit 12
, Respectively.

When the invention of claim 3 is described in association with FIG. 1, for example, the "first and second inverters" correspond to the inverter IV1.

The invention of claim 6 will be described with reference to FIG. 2, for example. The “low side power supply circuit” corresponds to the low side power supply circuit 21.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION A level shift circuit according to the present invention will be specifically described below with reference to the drawings.
The level shift circuit described below has a block configuration similar to that of FIG. 3, and includes a rising edge signal output circuit 1 and
The falling edge signal output circuit 2, the high side driver 3, the high side driver control circuit 4, the capacitor C1, the bootstrap diode D1, the low side driver 5, and the low side driver control circuit 6 are provided. Prepare

(First Embodiment) FIG. 1 is a circuit diagram showing the configuration of the main part of the level shift circuit according to the first embodiment. Details of the rising edge signal output circuit 1a and the falling edge signal output circuit 2a are shown. The configuration is shown.

The level shift circuit of this embodiment is formed in a semiconductor chip and has a low side power supply line L shown in FIG.
A low-side power supply voltage is supplied to 1 from a low-side power supply (not shown) provided outside the chip.

Below the dotted line in FIG. 1, a low voltage (for example, 5
It operates by receiving power supply from the low-side power supply line L1 of V or 15V) and receives power supply from the high-side power supply line L2 of high voltage (for example, several hundreds of V) above the dotted line. In FIG. 1, the same components as those of the conventional circuit shown in FIG. 4 are designated by the same reference numerals, and the difference will be mainly described below.

Each edge signal output circuit 1a, 2a of FIG.
Is an edge detection circuit 11 that detects a rising edge or a falling edge included in the input signal IN and outputs an edge detection pulse, and a pMOS transistor Q2 and an nMOS.
It has an inverter IV1 composed of a transistor Q3, an nMOS transistor Q1 to which an output signal of the inverter IV1 is input to its gate terminal, a resistor R1, and a level shift pulse receiving circuit 12. The above configuration is similar to that of FIG.

In addition, each of the edge signal output circuits 1a and 2a of FIG. 1 has an nMOS transistor Q4 cascode-connected to the nMOS transistor Q1. The drain terminal of the nMOS transistor Q4 is connected to the resistor R1, the gate terminal is connected to the low-side power supply line L1, and the diode D2 is connected between the gate terminal and the source terminal of the nMOS transistor Q4. nMOS transistor Q4
Has a higher breakdown voltage structure between the drain and the source than the nMOS transistor Q1. This is the nMOS transistor Q1
This is because when is on, a high voltage is applied only to the nMOS transistor Q4 due to the current limitation of the nMOS transistor Q1.

Next, the operation of the level shift circuit of the first embodiment will be described. The rising edge and the falling edge included in the input signal IN are the rising edge signal output circuit 1a and the falling edge signal output circuit 2a, respectively.
It is detected by each edge detection circuit 11 inside.

Each edge detection circuit 11 outputs an edge detection pulse when detecting an edge. This edge detection pulse is inverted by the inverter IV1 and input to the gate terminal of the nMOS transistor Q1. nMOS transistor Q1
Is temporarily turned on when an edge detection pulse is output from the edge detection circuit 11, and the voltage at the connection point between the nMOS transistor Q1 and the pMOS transistor Q4 decreases. As a result, the nMOS transistor Q4 also turns on, current flows from the high-side power supply line L2 to the low-side common line via the resistor R1, and a potential difference is generated across the resistor R1.

In the circuit of FIG. 1, the common voltage on the low side is always at a constant level (for example, 0 V), while the common voltage on the high side varies according to the drive output of the high side driver 3.

The level shift pulse receiving circuit 12 detects the potential difference across the resistor R1 and outputs a signal corresponding to the potential difference. The output of the level shift pulse receiving circuit 12 is input to the high side driver control circuit 4, as shown in FIG. The high side driver control circuit 4 is
It has a latch circuit 21 and a gate signal generation circuit 22, and outputs the output of each level shift pulse reception circuit 12 to the latch circuit 21.
, And the gate signal generation circuit 22 generates a gate signal for driving the high side driver 3 based on the output of the latch circuit 21.

When the high-side driver 3 is turned on / off while the nMOS transistor Q4 is off, the common voltage on the high-side changes accordingly, so that the high-side power supply line L2 passes through the resistor R1 and the low-side. Displacement current flows to the side. This displacement current flows to the low side by way of two paths indicated by arrows a and b in FIG.

An arrow a indicates a path which flows to the low side power supply line L1 via the drain-gate capacitance Cdg2 of the nMOS transistor Q4. The arrow b indicates the nMOS.
The drain-source capacitance Cds2 of the transistor Q4 and n
Drain-gate capacitance Cdg1 of MOS transistor Q1
And a path flowing through the drain-source of the nMOS transistor Q3 to the common line on the low side.

The low-side power supply (not shown) that supplies a voltage to the low-side power supply line L1 in FIG. 1 is premised on that it has sufficient current supply capability. Therefore, the displacement current passing through the resistor R1 is passed through the path indicated by the arrow a. It can be efficiently led to the low-side power supply line L1.

Further, since the drain-source capacitance Cds2 of the nMOS transistor Q4 and the drain-gate capacitance Cdg1 of the nMOS transistor Q1 on the path of the arrow b are connected in series, the total capacitance of both is 1 / (1 / Cds2 + 1 / Cdg1), and the capacitance value is smaller than each capacitance unit. Therefore, the current flowing through the arrow b becomes smaller than in the conventional case, and the degree of increase in the gate voltage of the nMOS transistor Q1 also becomes small. Further, since the diode D2 is connected between the drain terminal of the nMOS transistor Q1 and the gate terminal of the nMOS transistor Q4, the drain voltage of the nMOS transistor Q1 is limited to the same level as that of the low-side power supply line L1. No high voltage is applied to the drain terminal of the transistor Q1.

As described above, in the first embodiment, the nMOS transistor Q4 is provided between the nMOS transistor Q1 and the resistor R1.
And a displacement current flowing from the high-side power supply line L2 to the low-side side through the resistor R1 flows to the low-side power supply line L1 through the drain-gate capacitance Cdg2 of the nMOS transistor Q4 and the drain of the nMOS transistor Q4. Since the source-to-source capacitance Cds2, the drain-to-gate capacitance Q1 of the nMOS transistor Q1 and the drain-source of the nMOS transistor Q3 are made to flow, the current flowing through the nMOS transistor Q3 is reduced as compared with the conventional one, and the nMOS transistor Q3 has a voltage higher than the standard. The current stops flowing. Therefore, the breakdown of the nMOS transistor Q3 can be prevented.

Further, since the gate voltage of the nMOS transistor Q1 becomes lower than in the conventional case, the malfunction of the nMOS transistor Q1 can be prevented. Further, since the influence of the capacitance between the terminals of each transistor can be reduced, the level shift circuit can be formed using a thin film process having a large parasitic capacitance and a low gate breakdown voltage, and high integration is possible.

(Second Embodiment) If the low-side power supply voltage supplied from the outside exceeds the gate breakdown voltage of each MOS transistor in the level shift circuit, the MOS transistor may be destroyed. Therefore, the second embodiment described below is provided with a low-side power supply circuit that makes the low-side power supply voltage supplied from the outside equal to or lower than the gate breakdown voltage of the MOS transistor.

FIG. 2 is a circuit diagram showing the configuration of the main part of the level shift circuit of the second embodiment. The circuit of FIG. 2 is common to the circuit of FIG. 1 except that a low side power supply circuit 21 that outputs a low side power supply voltage is newly provided.

The low side power supply circuit 21 lowers the external low side power supply voltage so that the gate voltage of each MOS transistor does not exceed the gate breakdown voltage. The output terminal of the low-side power supply circuit 21 has a low-side power supply line L
1 is connected.

As a result, it becomes possible to use even a MOS transistor having a low gate breakdown voltage, such as in a thin film process.
A level shift circuit can be formed using a fine processing process in which it is difficult to manufacture a transistor having a high gate breakdown voltage, and the degree of integration can be improved.

In each of the above-mentioned embodiments, there are no particular restrictions on the voltage values of the low-side power supply voltage and the high-side power supply voltage.

In each of the above-described embodiments, the high-side common voltage and the drive output of the high-side driver 3 have the same voltage, but they do not necessarily have to have the same voltage.

[0041]

As described above in detail, according to the present invention, the second transistor is provided in the level shift circuit, and the displacement current flowing in the high side voltage generating circuit is controlled by the drain of the second transistor. Since it is made to flow to the low-side power supply side via the inter-gate capacitance, and is also made to flow via the drain-source capacitance of the second transistor and the drain-gate capacitance of the first transistor, the gate of the first transistor, etc. The rise in voltage can be suppressed, and the breakdown of these transistors can be prevented. Therefore, the level shift circuit can be formed using a thin film process having a large parasitic capacitance and a low gate breakdown voltage, and high integration can be achieved.

Further, since a part of the displacement current is made to flow to the low side power source side via the drain-gate capacitance of the second transistor, the amount of the displacement current flowing to the inverter in the level shift circuit is reduced, A level shift circuit can be formed using a small-sized transistor, and the element formation area can be reduced.

Further, by providing the low-side power supply circuit for outputting the low-side power supply voltage, the low-side power supply voltage does not exceed the gate breakdown voltage of the transistor, and even a transistor having a low gate breakdown voltage can be used. Therefore, a level shift circuit is formed using a thin film process. Can be formed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a main part of a level shift circuit according to a first embodiment.

FIG. 2 is a circuit diagram showing a configuration of a main part of a level shift circuit according to a second embodiment.

FIG. 3 is a block diagram of a conventional level shift circuit.

FIG. 4 is a circuit diagram showing a detailed configuration of a main part of the circuit of FIG.

[Explanation of symbols]

1,1a Rising edge signal output circuit 2,2a Falling edge signal output circuit 3 high side driver 4 High side driver control circuit 5 low side driver 6 Low-side driver control circuit 11 Edge detection circuit 12 level shift pulse receiving circuit IV1 inverter

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 19/0185 H03K 5/02 H03K 19/003

Claims (8)

(57) [Claims] 1. A low-side power supply and a low-side common power supply.
An edge signal output circuit that outputs a signal indicating a logical change position of an input signal when supplied with a power supply voltage from a source, and a first transistor that is turned on / off according to the logic of the output signal of the edge signal output circuit. And a high side voltage generation circuit that outputs a level shift signal obtained by shifting the voltage level of the input signal according to ON / OFF of the first transistor by receiving a power supply voltage from a high side power supply. A load drive circuit that drives a load based on the output of the high-side voltage generation circuit; a second transistor cascode-connected to the first transistor; and a first transistor. Is in the off state, the voltage flowing in the high side voltage generation circuit changes according to the fluctuation of the output voltage of the load drive circuit. A first current path through which a second current flows through the drain-gate capacitance of the second transistor to the low-side power supply side, and the displacement when the first transistor is in an off state.
A second current flowing through the low-side common power source through a drain-source capacitance of the second transistor and a drain-gate capacitance of the first transistor.
And a flow path . 2. A first edge position signal output circuit which outputs a signal indicating a rising edge position of an input signal, and a second edge position signal output circuit which outputs a signal indicating a falling edge position of the input signal. A high-side voltage generation circuit that outputs a level shift signal obtained by shifting the voltage level of the input signal based on the output signals of the first and second edge position signal output circuits; and an output of the high-side voltage generation circuit. And a load drive circuit that drives a load based on the input voltage of the first edge position signal output circuit, the first edge position signal output circuit receiving a power supply voltage from a low- side power supply and a low-side common power supply. A first edge detection circuit for detecting a rising edge position of a signal, and an output logic of the first edge detection circuit A first transistor that is turned on and off; a second transistor that is cascode-connected to the first transistor; and a first resistor that is connected between an output terminal of the second transistor and a high-side power supply. A first level shift pulse output circuit that outputs a signal indicating a rising edge position of the input signal according to a voltage across the first resistor by receiving a power supply voltage from the high-side power supply, When the first transistor is off, the load
The high side power supply according to the fluctuation of the output voltage of the drive circuit
The displacement current flowing from the second resistor to the resistor.
The low side via the drain-gate capacitance of the
A first current path flowing to the power supply side, and the displacement when the first transistor is in an off state
The current is applied to the drain-source capacitance of the second transistor.
And the drain-gate of the first transistor
A second power source that flows to the low-side common power source via a capacitor.
A second edge detection circuit that detects a falling edge position of the input signal by receiving a power supply voltage from the low side power supply. A third transistor that is turned on / off according to an output logic of the second edge detection circuit, a fourth transistor cascode-connected to the third transistor, an output terminal of the fourth transistor, and A second resistance connected between the high-side power supply and a power supply voltage supplied from the high-side power supply, so that a falling edge position of the input signal is generated according to a voltage across the second resistance. And a second level shift pulse output circuit that outputs a signal indicating that the displacement current is generated when the third transistor is in an off state.
Current to the drain-gate capacitance of the fourth transistor
Third current path flowing through the low-side power supply side via
And the displacement of the first transistor when the first transistor is off.
The current is applied to the drain-source capacitance of the fourth transistor.
Quantity and drain-gate of said third transistor
A fourth electric current that flows to the low-side common power source via a capacitor.
A level shift circuit having a flow path . 3. A first inverter that inverts and outputs the output signal of the first edge detection circuit by receiving a power supply voltage from the low-side power supply; and a power supply voltage from the low-side power supply. A second inverter that inverts and outputs the output signal of the second edge detection circuit, the output of the first inverter is input to the gate terminal of the first transistor, and the output of the second inverter The output is input to the gate terminal of the third transistor, and when the first transistor is in the off state, a part of the displacement current is transferred to the drain-source capacitance of the second transistor and the first transistor. The drain-gate capacitance of the transistor, and the second through the first inverter
Flowing in the current path of, and when the third transistor is in an off state, a part of the displacement current is drain-source capacitance of the fourth transistor, drain-gate capacitance of the third transistor, And the fourth through the second inverter
3. The level shift circuit according to claim 2, wherein the level shift circuit is caused to flow in the current path. 4. The first and second edge detection circuits,
A low-side circuit including the first and second inverters and the first to fourth transistors operates based on a common voltage having a constant voltage level and a voltage of the low-side power supply, and the high-side voltage A high-side circuit including a generation circuit and the resistor operates based on a common voltage whose voltage level varies according to an output voltage of the load drive circuit and a voltage of the high-side power supply. The level shift circuit according to claim 3. 5. The level shift circuit according to claim 4, wherein the common voltage of the high side circuit is the same voltage as the output voltage of the load drive circuit. 6. A low-side power supply circuit for generating a voltage of the low-side power supply based on a voltage supplied from the outside, wherein a part of the displacement current is supplied to the second side when the first transistor is in an off state. The displacement current is caused to flow through the drain-gate capacitance of the transistor to the low-side power supply circuit, and a part of the displacement current is passed through the drain-gate capacitance of the fourth transistor when the third transistor is off. The level shift circuit according to any one of claims 2 to 5, wherein the level shift circuit is supplied to a low-side power supply circuit. 7. The second and fourth transistors are nM
An OS transistor having first and second diodes respectively connected between gate and source terminals of the second and fourth transistors, wherein anode terminals of the first and second diodes are respectively 7. The level according to claim 2, wherein the level is connected to the source terminals of the second and fourth transistors, and the cathode terminal is connected to the gate terminals of the second and fourth transistors. Shift circuit. 8. A semiconductor integrated circuit in which the level shift circuit according to claim 1 is formed on a semiconductor substrate by using a thin film process.