JP3512561B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The invention disclosed in this specification includes:
The present invention relates to the structure of an electrode contact portion in a semiconductor integrated circuit. Further, the present invention relates to a manufacturing method thereof.

[0002]

2. Description of the Related Art An active matrix liquid crystal display device is known. This has a configuration in which a glass substrate or a quartz substrate is used as a substrate and a thin film transistor formed on the substrate is arranged for each pixel.

A process of manufacturing a pixel portion of a general active matrix type liquid crystal display device which has been conventionally used will be described below.

FIG. 6 and subsequent figures show a state in which a part of the active matrix circuit (a part of one pixel) is manufactured as viewed from above. Further, the cross section taken along the line AA 'in FIG. 6 is shown in FIG.
It shows in (A). Further, the cross section taken along the line BB 'in FIG. 6 is shown in FIG.
It shows in (B). The cross section taken along line aa 'in FIG. 7 is shown in FIG.
It shows in (A).

First, as shown in FIGS. 6A and 8A, a silicon oxide film 12 is formed as a base film on a glass substrate 11. After the silicon oxide film 12 is formed, an amorphous silicon film serving as a starting film of the active layer of the thin film transistor is formed.
Further, the amorphous silicon film is transformed into a crystalline silicon film by irradiation with laser light and heat treatment.

After the crystalline silicon film is obtained, it is patterned to form the pattern of the active layer 13. This active layer 1
The shape of 3 viewed from above is shown in FIG. A cross section taken along the line AA 'is shown in FIG.

Next, a film made of a conductive material for forming the gate electrode is formed. Various silicide materials and metal materials are used as the conductive material. Next, the film made of this conductive material is patterned to form a gate electrode 14.

The gate electrode 14 is formed so as to extend from the gate line 15 as shown in FIG. 6 (B). The gate lines 15 are arranged in a grid pattern in the active matrix region together with the source lines that will be formed later.

Next, impurity ions are implanted using the gate electrode 14 as a mask to form the source region 16 and the drain region 18 in a self-aligned manner. Here, if an N-channel type thin film transistor is manufactured, P (phosphorus) is injected. If a P-channel type thin film transistor is to be manufactured, B (boron) is injected.

Further, in the impurity ion implantation step, the region of the channel forming region 17 is determined in a self-aligned manner.

Thus, the cross-sectional state shown in FIG. 8B is obtained. Here, the cross section taken along the line BB ′ of FIG.
(B). Next, a silicon nitride film or a silicon oxide film is formed as the interlayer insulating film 19. Thus, the state shown in FIG. 8C is obtained.

Next, as shown in FIG. 8D, the source region 1
6 and the contact hole 20 for the drain region 18
And 21 are formed on the interlayer insulating film 19.

Then, as shown in FIG. 9A, an electrode 22 contacting the source region 16 and an electrode 23 contacting the drain region 18 are simultaneously formed.

FIG. 7 shows the state of the cross section shown in FIG. 9A as seen from above. The cross section taken along the line aa 'in FIG. 7 is shown in FIG.
Corresponds to (A).

As shown in FIG. 7, the contact portion of the source line 22 has a larger area than the source region 16 of the active layer. The pattern of the contact electrode 23 of the drain region 18 is also slightly larger than the pattern of the drain region 18.

This is alignment (mask alignment) when forming the contact holes 20 and 21.
This is because the margin (corresponding to the error (positional deviation)) and the marginal error (positional deviation) indicated by 22 and 23 at the time of forming the wiring and the electrode pattern are taken into consideration.

The above-mentioned misalignment occurs not a little due to the shrinkage of the glass substrate and the alignment error of the exposure machine itself. Generally, when manufacturing a liquid crystal display device, a glass substrate is used as a substrate, and the area thereof is large. Therefore, the above-mentioned positional deviation is caused by about several μm.
Therefore, a margin that allows for the positional deviation as described above is required.

After obtaining the state shown in FIG. 9A, a film 25 made of a resin material is formed as the second interlayer insulating film 25.
The reason why the film made of a resin material is used is that the surface can be made flat. Thus, the state shown in FIG. 9B is obtained.

Next, a contact hole reaching the electrode 23 is formed. The pixel electrode 26 made of ITO is formed.
Thus, the state shown in FIG. 9C is obtained.

Also, not the active matrix region,
12 and 13 show a schematic top view of a manufacturing process of a thin film transistor for forming a peripheral driver circuit and other integrated circuits.

FIG. 12A shows a state in which a gate insulating film (not shown) is formed on the active layer 1201 made of a silicon film, and a gate electrode 1202 is arranged on the gate insulating film.

Further, FIG. 12B shows that an interlayer insulating film (not shown) is formed in the state shown in FIG. 12A, and contact electrodes to the source and drain regions (further extend from the contact portion). Wiring 1203 and 1204 are formed.

Reference numerals 1205 and 1206 are contact holes formed in an interlayer insulating film (not shown).
The impurity region and the contact electrode are connected through this contact hole.

In such a structure, the active layer 120
1 alignment accuracy, contact holes 1205 and 12
In order to see a margin with respect to the alignment accuracy of 06 and the alignment accuracy of the electrodes 1203 and 1204, an extra area is required in the dimension indicated by a.

The dimension indicated by "a" is obtained by first activating the active layer 12
01 and the contact hole 1206 are required to be aligned, and a margin for allowing the contact hole 1206 and the electrode 1204 to be aligned is required.

[0026]

In the active matrix type liquid crystal display layer, it is required to increase the aperture ratio of the pixel portion as much as possible.

However, in the above-mentioned structure, the area occupied by the electrodes used for the contacts is large and the transmittance cannot be increased.

Generally, an aperture ratio of 100% is impossible. This is because there is an area occupied by the source line 22 and the gate line 15 as shown in FIG.

Therefore, in order to increase the aperture ratio, it is required to minimize the area occupied by the electrode pattern required for the contact.

For example, in the structure shown in FIG. 7, the source line 22 and the electrode 23 have a region which is not used for contact and is present as a factor for lowering the aperture ratio. This area is necessary to secure a margin for alignment, but becomes a dead space after the process is completed. This dead space becomes a light-shielding region, which reduces the aperture ratio.

In general, the following problems also occur in integrated circuits. Some active matrix type liquid crystal display devices are referred to as a peripheral drive circuit integrated type. This is a peripheral drive circuit that drives an active matrix circuit around the active matrix circuit is integrated on the same substrate.

Naturally, the peripheral drive circuit is composed of thin film transistors. The peripheral drive circuit is required to have a high degree of integration in order to reduce the size of the entire device.

However, with the general thin film transistor pattern as shown in FIG. 12, it is difficult to increase the degree of integration. One of them is that the dimension indicated by a cannot be reduced inevitably. This dimension is related to the shrinkage of the glass substrate and the mask alignment accuracy in the manufacturing process, and it is difficult to make it smaller than a certain value.

Particularly, in the case of an integrated circuit using a glass substrate which has a large area and shrinks, it is an important problem to secure the above alignment accuracy.

Generally, when the design rule is reduced, the contact hole is generally reduced correspondingly.

However, reducing the size of the contact hole causes problems such as increase in contact resistance and occurrence of contact failure.

For example, when the design rule is changed from the 5 μm rule to the 3 μm rule, the contact area is (5 μm) ² = 25 μm ² to (3 μm) ² = 9 μm ²
And decrease. That is, the contact area is reduced to about 1/3.

Design rule from 5 μm rule to 3 μm
Even if the rule is changed, the current value to be handled does not become 1/3. Therefore, in this case, the current density in the contact portion is almost tripled.

In such a situation, the contact portion is apt to be broken or defective due to local heating.

The research conducted by the inventors of the present invention has also confirmed that a large number of contact parts are broken down as a cause of defects caused when the design rule is reduced.

The reduction of the design rule is a matter which is required more and more in the future due to the necessity of reducing the circuit area.

Therefore, the situation in which the contact area decreases in proportion to the square as the design rules decrease as described above will become an even more serious problem in the future.

The invention disclosed in the present specification provides a structure in which an unnecessary electrode pattern is further deleted while ensuring a positioning margin required for forming a contact, thereby increasing the aperture ratio as much as possible. Is an issue.

Another object of the present invention is to provide a structure capable of further increasing the degree of integration, especially when integrating thin film transistors on a glass substrate.

An object of the present invention is to provide a structure in which the contact area can be maximized even if the degree of integration is increased (that is, the design rule is reduced).

[0046]

One of the inventions disclosed in this specification is to show a semiconductor layer existing under an interlayer insulating film 311 as shown in FIG. To the semiconductor layer, the contact being formed in an opening 312 exposing a portion 308 of the semiconductor layer, and patterned wiring 317 contacting the portion 308 of the semiconductor layer inside the opening. Is patterned into the same pattern as the wiring 317 inside the opening 312 (see FIG. 2).

In the above structure, a margin for alignment can be taken by making the area of the opening 312 larger than the area of the contact (the area where the semiconductor layer contacts the wiring).

FIG. 1 shows another specific example of the above configuration.
There is a configuration shown in FIG. In the structure shown in FIG. 14, there is a contact to the semiconductor layer 1401 existing under the interlayer insulating film, and the contact is formed in the opening 1407 where a part of the semiconductor layer is exposed, and the electrode patterned inside the opening. Alternatively, the wiring 1409 is in contact with the semiconductor layer, and the semiconductor layer is patterned in the same pattern as the electrode or the wiring inside the opening.

As shown in a concrete example in FIGS. 2 and 4C, another structure of the present invention is formed in the interlayer insulating film with respect to the semiconductor layer 308 existing under the interlayer insulating film 311. The electrode or wiring 317 is in contact with the inside of the opening 312, and at least a part of the end surface of the semiconductor layer and at least a part of the end surface of the electrode or the wiring match or substantially match with each other in the opening. Is characterized by.

By adopting the above structure, it is possible to realize a structure in which the contact area is secured and the design rule is made small. The above structure is inevitably obtained by patterning the wiring 317 in the contact opening 312.

In the structure of another invention, as shown in a concrete example in FIGS. 2 and 4C, the semiconductor layer 308 existing under the interlayer insulating film 311 is formed in the interlayer insulating film. The electrode or wiring 317 is in contact with the inside of the opening 312, and the electrode or wiring does not overlap at least one side of the edge of the opening in the opening.

The above structure is inevitably obtained by patterning the wiring 317 in the contact opening 312.

The structure of another invention has a thin film transistor arranged in a pixel of an active matrix type liquid crystal display device, as shown in FIG.
In the contact portion between the impurity region of the thin film transistor and the source line 317 forming the active matrix circuit, the impurity region is patterned into a pattern of the source line.

The structure of another invention has a thin film transistor arranged in a pixel of an active matrix type liquid crystal display device as shown in an example of the specific structure of FIG.
A part of the impurity region of the thin film transistor is patterned in a self-aligning manner with the shape of the metal electrode 318 or the metal wiring 317 that contacts.

Another structure of the present invention is a method of forming a contact to the semiconductor layer 308 existing under the interlayer insulating film 311, as shown in FIG. 3 and FIG. 2 includes a step of forming an opening 312 in which part of the layer is exposed and a step of forming a wiring 317 in contact with the semiconductor layer inside the opening, and when the wiring 317 is formed, as shown in FIG. Wiring to 3
The semiconductor layer 308 is patterned into 17 patterns.

[0056]

BEST MODE FOR CARRYING OUT THE INVENTION As shown in FIG. 4, the area of the wiring 317 is minimized by patterning the impurity region 308 in the opening 312 in a self-aligned manner with the pattern of the wiring 317 (see FIG. 2). Can be

That is, at the time of patterning the wiring 317, the impurity regions unnecessary for the contacts are simultaneously etched, so that only the impurity regions necessary for the contacts can remain in the openings 312.

Further, since the alignment is carried out in a self-aligning manner, the region of the wiring 317 which does not contribute to the contact (a large pattern which has been conventionally required) is not required. As a result, an active matrix circuit having a high aperture ratio can be obtained.

Further, a part of the active layer (a part of the impurity region forming the source and / or drain region) is also patterned into the area required for contact by the contact wiring or electrode, so that the active layer is formed. The component of light shielded by can be reduced. This is also a factor that makes it possible to obtain a high aperture ratio.

Further, the area used for the contact (the contact area between the wiring or the electrode and the semiconductor layer) can be secured large, while the area of the wiring or the electrode not used for the contact is removed, so that the design rule can be made small. You can

[0061]

【Example】

[Embodiment 1] In this embodiment, a configuration of a pixel portion in an active matrix type liquid crystal display device is shown. FIG. 1 and FIG. 2 are manufacturing process diagrams seen from the upper surface. 3 to 5 are cross-sectional manufacturing process diagrams.

First, as shown in FIG. 3A, the glass substrate 3
A silicon oxide film 302 is formed as a base film on 01 by a sputtering method to a thickness of 3000 Å.

Next, an amorphous silicon film (not shown) is subjected to plasma C
A film is formed to a thickness of 500Å by the VD method. Then, by irradiating with laser light, crystallization is performed and a crystalline silicon film is obtained.

Then, the obtained crystalline silicon film is patterned to obtain the active layer of the thin film transistor denoted by 303. Thus, the state shown in FIG. 3A is obtained.

The pattern shape of the active layer is shown in FIG. The cross section taken along the line AA ′ in FIG. 1A corresponds to FIG.

Next, a silicon oxide film 304 functioning as a gate electrode is formed to a thickness of 1000 Å by the plasma CVD method. (Fig. 3 (B))

Further, an aluminum film (not shown) for forming the gate line and the gate electrode extending from the gate line is formed to a thickness of 4000 Å by the sputtering method.
Here, 0.18 wt% of scandium is contained in the aluminum film. This is to suppress the formation of needle-like or stab-like protrusions called hillocks or whiskers due to abnormal growth of aluminum in the subsequent process.

After forming the aluminum film, patterning is performed to form the gate electrode 305. The gate electrode 305 is connected to the gate line 3 as shown in FIG.
It is formed in a state of extending from 07. B- in FIG. 1 (B)
The cross section cut along B'corresponds to FIG.

After forming the gate electrode 305, anodization is performed in the electrolytic solution with the gate electrode 305 as an anode. In this step, the anodic oxide film 306 is formed to 100
Form to a thickness of 0Å.

The anodic oxide film 306 has a function of physically and electrically protecting the surface of the aluminum pattern. Specifically, it has functions of preventing short-circuiting between wirings and preventing hillocks and whiskers. In addition, in the later impurity ion implantation step, it functions to form the offset gate region by the thickness thereof.

A plasma oxide film formed by plasma treatment in an oxidizing atmosphere can be used as a substitute for the anodic oxide film.

Impurity ions are implanted in the state shown in FIG. In this embodiment, B (boron) ions are implanted in order to manufacture a P-channel type thin film transistor. (If N-channel type is to be manufactured, P (phosphorus) ion implantation is performed)

In this step, B ions are implanted in the regions 308 and 310. The area 308 is the source area,
The region 310 serves as a drain region. The region 309 becomes the channel formation region.

Although not shown, an offset gate region is formed between the channel region 309 and the source / drain region with the thickness of the anodic oxide film 306.

Next, a silicon nitride film is formed as the first interlayer insulating film 311 by the plasma CVD method to a thickness of 5000 Å. Thus, the state shown in FIG. 3C is obtained.

Next, the source region 308 and the drain region 3
Contact holes (openings) 312 and 313 reaching 10
To form. Thus, the state shown in FIG. 3D is obtained. The shape and positional relationship of the contact holes 312 and 313 are shown in FIG. Dry etching is preferably used to form the contact holes.

Next, as shown in FIG. 4A, a metal film 314 having a thickness of 4000 Å is formed by a sputtering method. The metal film 314 is composed of a laminated film of a 500 Å thick titanium film, a 2000 Å thick aluminum film and a 500 Å thick titanium film.

The titanium film is used because it is easy to make ohmic contact with a semiconductor or various conductive materials. The aluminum film is used because its low resistance is required. In particular, since this metal film constitutes a source line, it is very important to reduce the wiring resistance.

After obtaining the state shown in FIG. 4A, resist masks 315 and 316 are arranged as shown in FIG. 4B.

Then, using the above mask, the metal film 3
14 is patterned. Thus, patterns 317 and 318 are formed.

At this time, as shown in FIG.
Also, the active layer is patterned at the same time as the patterning of the electrode 318. That is, the source line 317 and the electrode 318
The source region 308 and the drain region 310, which constitute one of the contacts in a self-aligned manner, are also patterned by the pattern of FIG. For this patterning, it is preferable that dry etching is utilized to continuously perform the patterning of the metal film 314 and the patterning of the active layer.

Thus, the state shown in FIG. 4B is obtained. Here, the cross section cut along CC 'in FIG. 2 corresponds to FIG.

In FIG. 4C, the pattern indicated by 317 is a source line. As is apparent from the figure, the source line 317 directly contacts the source region 308.

In this embodiment, the contact hole 3
12 is large, and the source line 317 directly contacts the drain region in the inside.

The important point here is the contact hole 31.
That is, the wiring 317 completely penetrates inside 2. That is, in the contact portion, the opening has a larger area than the area of the metal wiring to be contacted. The difference between the contact area and the opening area ensures a margin for alignment.

With such a structure, even if the position of the contact hole 312 is displaced or the position of the wiring 317 is displaced, the contact between the source region 308 and the source line 317 can be ensured. Also, the source line 3
The area occupied by 17 can be reduced. (See Figure 2)

Also in the drain contact portion,
The area of the contact electrode indicated by 318 can be made small. Also in this portion, the drain region 3
The area of the contact hole 313 to 10 is larger than the area where the contact electrode 318 contacts the drain region.

With such a structure, the position of the contact hole 313 is displaced, and the contact electrode 3 is formed.
Even if the 18 position is displaced, the contact between the drain region and the electrode 318 can be ensured. Also, the electrode 3
The area occupied by 18 need not be particularly large. (See Figure 2)

After obtaining the state shown in FIG. 4C, a second interlayer insulating film 319 is formed from a resin material. The resin material is used because its upper surface can be flattened. Thus, the state shown in FIG. 5A is obtained.

Next, as shown in FIG. 5B, a contact hole 320 is formed. A part of the contact electrode 318 is exposed at the bottom of the contact hole 320.

Next, the pixel electrode 321 is formed of ITO. In this way, the pixel portion of the active matrix circuit portion is completed. After that, steps of forming a rubbing film, rubbing, and assembling a liquid crystal panel are performed to complete a liquid crystal display device.

As is clear by comparing FIG. 7 and FIG.
When the configuration shown in this embodiment is adopted, the area of the metal film in the portion where the contact is made can be reduced. Therefore, the aperture ratio can be maximized.

[Embodiment 2] This embodiment is an example of using a bottom gate type thin film transistor as the type. FIG. 10 is a cross-sectional view corresponding to one state of the manufacturing process shown in FIG.

In FIG. 10, 1001 is a glass substrate, and 1003 is a gate electrode formed on the glass substrate. The gate electrode 1003 is formed as extending from the gate line.

Reference numeral 1002 is a gate insulating film. 1004
Is a source region, and 1006 is a drain region.
1005 is a channel formation region.

Reference numeral 1007 denotes an interlayer insulating film, and 1008 and 1009 are contact openings formed in the interlayer insulating film 1007.

Reference numeral 1010 is a source line, and the opening 1008 is provided.
The source region 1004 is in contact therewith.
Reference numeral 1011 is an electrode in contact with the drain region 1006. This electrode 1006 also contacts the drain region 1006 in the opening 1009.

Also in the structure shown in this embodiment, an extra pattern other than the contact portion can be removed as in the structure shown in the top view of FIG.

Example 3 The invention disclosed in this specification is
It can be used for an active matrix type liquid crystal display device in which a peripheral drive circuit is integrated.

The active matrix type liquid crystal display device can be used for the following applications. FIG. 11A shows a device called a digital still camera, an electronic camera, or a video movie that can handle a moving image.

This apparatus has a function of electronically storing an image photographed by a CCD camera (or an appropriate photographing means) arranged in the camera section 2002. Then, the captured image is displayed on the liquid crystal display device 200 arranged on the main body 2001.
3 has the function of displaying. The operation of the device is performed by the operation button 2004.

Utilizing the invention disclosed in this specification,
Since a liquid crystal display device having a high aperture ratio can be obtained, high brightness can be obtained. Further, since it has high brightness, it is possible to reduce power consumption for obtaining a predetermined brightness. Therefore, it is useful for a portable device as shown in FIG.

FIG. 11B shows a portable personal computer. In this device, a liquid crystal display device 2104 is provided on an openable cover (cover) 2102 attached to the main body 2101, and various information can be input from the keyboard 2103 and various arithmetic operations can be performed.

FIG. 11C shows an example in which a flat panel display is used in the car navigation system. The car navigation system is composed of a main body including an antenna unit 2304 and a liquid crystal display device 2302.

Switching of various information required for navigation is performed by the operation button 2303. Generally, the operation is performed by a remote control device (not shown).

Since the car navigation system may be used under direct sunlight, the structure shown in FIG. 1 should be adopted and a liquid crystal display device having a high aperture ratio and high brightness should be used. Will be useful.

FIG. 11D shows an example of a projection type liquid crystal display device. In the figure, the light emitted from the light source 2402 is optically modulated by the liquid crystal display device 2403 to form an image. The image is reflected by the mirrors 2404 and 2405 and displayed on the screen 2406.

FIG. 11E shows an example in which the main body 2501 of the video camera is provided with a display device called a viewfinder.

The viewfinder is roughly composed of a liquid crystal display device 2502 and an eyepiece part 2503 on which an image is displayed.

The video camera shown in FIG. 11E is operated by the operation button 2504, and the tape holder 25
An image is recorded on the magnetic tape housed in 05. The image captured by a camera (not shown) is displayed on the display device 2.
502 is displayed. Further, an image recorded on the magnetic tape is displayed on the display device 2502.

It is necessary to consider that the video camera as shown in FIG. 11E is used outdoors. Therefore,
It is important to utilize the invention disclosed in this specification to use a liquid crystal display device having an aperture ratio as high as possible and obtain high brightness.

[Embodiment 4] In this embodiment, for example, in an active matrix type liquid crystal display device, when an active matrix circuit and peripheral drive circuits, various memory circuits, and various arithmetic circuits are integrated on the same glass substrate. Can be used.

In the case of constructing various integrated circuits using thin film transistors, it is required to minimize the distance between the thin film transistors and pack as many thin film transistors as possible within a predetermined area.

FIG. 14 shows a circuit of the integrated thin film transistor of this embodiment. FIG. 14 shows a state in which two thin film transistors are integrated. FIG. 14 shows a configuration in which one gate electrode is commonly arranged for two thin film transistors.

In FIG. 14A, 1401 and 140
Reference numeral 2 is an active layer of the thin film transistor. The active layer is composed of a crystalline silicon film.

Reference numeral 1406 denotes a gate electrode pattern formed on a gate insulating film (not shown).
The gate insulating film is formed so as to cover the active layer.

Denoted by 1407 and 1408 are openings for the source and drain regions of the active layers 1401 and 1402. Note that 1403 is a source region of the active layer 1401 and 1404 is a drain region of the active layer 1402. Further, 1405 is a source region of the active layer 1402, and 1405 is a drain region of the active layer 1402.

Inside the openings 1407 and 1408, the source regions 1403 and 1405 and the drain regions 1404 and 1405 are exposed.

The alignment accuracy of the openings 1407 and 1408 is not so required. For example, the alignment accuracy of the opening 1407 depends on the drain region 1404 of the active layer 1401.
And the drain region 1405 of the active layer 1403 is allowed within the range exposed.

FIG. 14B shows a state in a process which is a step further advanced from the state shown in FIG. Figure 1
4B shows a state in which source electrodes (source wirings) 1409 and 1411 and drain electrodes (drain wirings) 1413 and 1415 are formed in addition to the state shown in FIG. 14A.

In the state shown in FIG. 14B, the electrode 1409 is provided in the source region 1 inside the opening 1407.
Contact 403. Inside the opening 1407, the source region 1403 is patterned in the pattern of the electrode 1409.

1410, 1412, 1414, 1416
Shows that each electrode is a semiconductor (source / drain impurity region)
Indicates the contact area.

In the following, significant points in the case of adopting the structure shown in this embodiment will be described by taking the contact electrode 1409 to the source region 1403 as an example.

The alignment accuracy of the electrode 1409 is allowed within the range where the pattern of the source region 1403 and the pattern of the electrode 1409 overlap. In other words, the dimensions of the active layer source region 1403 and the electrode 1410 are determined based on the alignment accuracy.

In the structure shown in FIG. 14B, the source region 1403 is patterned by the pattern of the electrode 1409 inside the opening 1407. That is, in the opening, the pattern of the semiconductor layer other than that required for the contact is removed.

Further, the labor required for alignment is reduced as compared with the conventional structure as shown in FIG.

In the structure shown in this embodiment, in the steps shown in the figure, a patterning step is required in (1) formation of the active layer 1401 and (2) formation of the electrode 1409.

In this case, the active layer 1401 and the electrode 1409
It is necessary to match the relative positional relationship of.

What is important here is that substantially no alignment accuracy is required when forming the opening 1407.

On the other hand, in the conventional method as shown in FIG. 12, three patterning steps of (1) patterning the active layer 1201, (2) forming contact holes 1205 and 1206, (3) forming electrodes 1203 and 1204 are performed. Is required.

Therefore, it is necessary to align the contact holes 1205 and 1206 with the active layer 1201 and align the electrodes 1203 and 1204 with the contact holes.

This means that the configuration shown in FIG. 12 doubles the burden of alignment as compared with the configuration shown in FIG.

When the configuration shown in FIG. 12 is adopted to implement the configuration in which two thin film transistors are integrated,
The degree of integration is as shown in 3. Here, a is a margin required to obtain a contact, and b is a dimension required to maintain a space between adjacent elements.

However, when the structure shown in this embodiment is adopted, the same design rule as in FIG.
It is possible to obtain the integration degree as shown in.

Since the positioning load can be halved,
The dimension indicated by c can also be made smaller than the dimension indicated by b in FIG.

Above all, it is not necessary to increase the area of the contacting electrode (indicated by 1409, for example) in order to secure a contact margin, and the contact area can be further increased.

[Embodiment 5] This embodiment is an example in which the configuration shown in Embodiment 4 is modified. 15 and 16 are top views of the manufacturing process of this example.

The figure shows a structure in which three thin film transistors are arranged (integrated).

First, as shown in FIG. 15A, there is a semiconductor thin film pattern 1501 which is a base forming an active layer of a thin film transistor. With this pattern 1501, the active layers of three thin film transistors will be formed later. 1502 and 1
Reference numeral 503 later becomes a groove for separating the thin film transistors from each other.

Reference numeral 1504 is a gate electrode formed on a gate insulating film (not shown) (covering the pattern 1501).

Shown in (B) is a state in which contact openings 1505 and 1506 have been formed after forming an interlayer insulating film (not shown). A part of the semiconductor thin film pattern 1501 is exposed inside the opening.

When the state shown in (B) is obtained, the gate electrode 1
Impurity ions are implanted using 504 as a mask to dope the region other than where the gate electrode 1504 exists with an impurity imparting one conductivity type.

Electrodes (and wirings) contacting the source / drain regions are formed on an interlayer insulating film (not shown).

In FIG. 16, 1507, 1509, 1
Reference numeral 511 denotes a source electrode (electrode that contacts the source region). Reference numerals 1513, 1515, and 1517 are drain electrodes (electrodes that contact the drain).

The active layer denoted by 1501 in FIG. 15A is patterned in the openings (denoted by 1505 and 1506) in the same shape as the electrode when the electrode denoted by 1507 and the like is patterned. At this time, element isolation is performed.

That is, the active layer is separated at the same time as the patterning of the contact electrode to the source and sorain regions. In this way, the pattern of each active layer shown by 1509, 1510, and 1511 is formed.

The feature of this embodiment is that the active layer is separated between the elements at the same time when the contact electrodes are formed. By doing so, the element spacing can be reduced and at the same time the contact area can be increased.

This is because the contact opening area is larger than the contact area and the impurity region is patterned in the opening by utilizing the pattern of the contacting electrode.

With such a structure, the alignment accuracy of the opening for contact does not matter, and the alignment of the active layer and the electrode for contact does not matter. Therefore, the same design rule as the conventional one is adopted. Even if used, the degree of integration can be increased.

[Embodiment 6] This embodiment relates to a structure in which the aperture ratio is increased as much as possible in an active matrix circuit.

FIG. 17 shows a schematic structure of this embodiment. In FIG. 17, 701 is a source line and 704 is a gate line. The shaded area is the active layer. Most of the active layer is arranged so as to overlap with the source line 701.

The contact between the source region of the active layer and the source line is made in the region 702 inside the opening 703.

Inside the opening 703, the active layer is patterned into the source line 701.

Reference numeral 705 denotes an electrode which contacts the drain region inside the opening 706.
Inside the opening 706, the drain region is patterned with the pattern of the electrode 705.

Also in the structure shown in the present embodiment, it is possible to adopt a structure which does not require an electrode area other than that required for the contact while taking a positioning margin for the contact. At the same time, the contact area can be increased.

The above significance is obtained by patterning the semiconductor of the contact partner in the opening for contact using the pattern of the electrode to be contacted.

[0157]

By utilizing the invention disclosed in this specification, a margin for alignment required for forming a contact is ensured, and an unnecessary electrode pattern is further removed to reduce the aperture ratio as much as possible. A configuration that enhances can be provided.

Further, the degree of integration of the drive circuit of the active matrix circuit and other various integrated circuits can be increased. Further, in the configuration in which the active matrix circuit and various integrated circuits are integrated on the same glass substrate, the degree of integration can be further increased.

The invention disclosed in this specification can be applied not only to a liquid crystal display device but also to a display device using an electrochromic material. Further, the device can be widely used for a flat panel display of a type in which light is transmitted.

[Brief description of drawings]

FIG. 1 is a top view illustrating a manufacturing process of a pixel portion.

2A to 2C are top views showing manufacturing steps of a pixel portion.

3A to 3C are cross-sectional views illustrating a manufacturing process of a pixel portion.

4A to 4C are cross-sectional views illustrating a manufacturing process of a pixel portion.

5A to 5C are cross-sectional views illustrating a manufacturing process of a pixel portion.

FIG. 6 is a top view showing a conventional manufacturing process of a pixel portion.

FIG. 7 is a top view showing a conventional manufacturing process of a pixel portion.

FIG. 8 is a cross-sectional view showing a conventional manufacturing process of a pixel portion.

FIG. 9 is a cross-sectional view showing a conventional manufacturing process of a pixel portion.

FIG. 10 is a cross-sectional view showing a manufacturing process of a pixel portion in which a bottom gate thin film transistor is arranged.

FIG. 11 is a diagram showing an application example of an active marix type liquid crystal display device.

FIG. 12 is a top view showing a configuration of a conventional thin film transistor.

FIG. 13 is a top view showing a configuration of a conventional integrated thin film transistor.

FIG. 14 is a top view showing a structure of an integrated thin film transistor.

FIG. 15 is a top view illustrating a manufacturing process of an integrated thin film transistor.

FIG. 16 is a top view showing a structure of an integrated thin film transistor.

FIG. 17 is a top view showing a pixel portion.

[Explanation of symbols]

301 glass substrate 302 base film (silicon oxide film) 303 active layer (crystalline silicon film) 304 gate insulating film (silicon oxide film) 305 gate electrode 306 anodized film 307 gate line 308 source region 309 channel formation region 310 drain region 311 Interlayer insulating film (silicon nitride film) 312, 313 Contact opening 314 Metal film (Ti / Al / Ti laminated film) 315, 316 Resist mask 317 Source line 318 Contact electrode 319 Interlayer insulating film (resin film) 320 For contact Opening 321 Pixel electrode ITO electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/768 H01L 21/28 H01L 21/336 H01L 29/786

Claims (6)

(57) [Claims] 1. An active layer of a thin film transistor, an interlayer insulating film formed on the active layer and having an opening overlapping a part of the active layer, and an electrode or wiring formed on the interlayer insulating film. the the electrode or the wiring and the active layer, in contact at the opening, is and patterned in the same pattern in the open interior, the more contact area between the electrode or wire and the active layer
A semiconductor device characterized in that the area of the opening is larger . 2. An active layer of a thin film transistor arranged in a pixel of an active matrix type display device, and an interlayer insulating film formed on the active layer and having an opening overlapping at least a part of an impurity region of the active layer, An electrode or a wiring formed on the interlayer insulating film, the electrode or the wiring and the impurity region of the active layer are in contact with each other in the opening, and are patterned in the same pattern inside the opening. A semiconductor device characterized by: 3. The semiconductor device according to claim 2 , wherein the area of the opening is larger than the contact area between the electrode or wiring and the active layer. 4. A semiconductor device having an active layer of a thin film transistor, an interlayer insulating film on the active layer, and an electrode or wiring on the interlayer insulating film, wherein the electrode or wiring and the active layer are in contact with each other. A method of manufacturing, comprising forming a semiconductor layer, forming an opening in the interlayer insulating film so that a part of the semiconductor layer is exposed, and forming a metal film in contact with the semiconductor layer inside the opening, A method for manufacturing a semiconductor device, characterized in that the metal film and the semiconductor layer are patterned so that the same pattern is formed inside the opening, and the electrode or wiring and the active layer are formed. 5. A semiconductor device having an active layer of a thin film transistor, an interlayer insulating film on the active layer, and an electrode or wiring on the interlayer insulating film, wherein the electrode or wiring and the active layer are in contact with each other. A method of manufacturing, comprising forming a semiconductor layer, forming an opening in the interlayer insulating film so that a part of the semiconductor layer is exposed, and forming a metal film in contact with the semiconductor layer inside the opening, A method for manufacturing a semiconductor device, comprising patterning a metal film to form the electrode or wiring, patterning the semiconductor layer in a self-aligned manner with the shape of the electrode or wiring, and forming the active layer. 6. The method of claim 4 or claim 5, manufacturing side of the semiconductor device which is characterized in that the pixels of the active matrix display device, and placing the thin film transistor
Law .