JP2001332738A - Thin film semiconductor device, liquid crystal display device and electroluminescent display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a point defect or a line defect of a thin film semiconductor device used for a display or the like. SOLUTION: In a thin film semiconductor device, a signal wiring 3, a gate wiring 2 and a thin film transistor TFT are formed on an insulating board to constitute a circuit. A semiconductor thin film 4 is extended along the signal wiring 3, and a distance from a contact hole CONS for electrically connecting the film 4 to the wiring 3 to a channel region Ch is lengthened. A protective member 2F of floating is arranged of the same material as that of a gate electrode along an edge of the film 4 disposed from the CONS to the channel region. The contact hole COND for connecting the drain region of the TFT to an intermediate wiring 3a and the contact hole CONP for connecting a pixel electrode to the wiring 3a are isolated from each other, and the former is arranged at a remote position from the TFT as compared with the latter. A part of the film 4 disposed under the wiring 3 via the CONS is extended at an outside in a width of at least 5 μm from an inner diameter of the CONS.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device, a liquid crystal display and an electroluminescence display. More specifically, the present invention relates to a technique for preventing point defects and line defects appearing in a display device.

[0002]

2. Description of the Related Art FIG. 9 is a schematic view showing an example of a conventional thin film semiconductor device. This thin film semiconductor device includes a pixel electrode in addition to a bottom gate thin film transistor, and is used as a drive substrate of a so-called active matrix display device. FIG. 9 shows a plan view of one pixel. As shown in the figure, the thin-film semiconductor device is formed by integrally forming, for example, a thin film transistor TFT having a bottom gate structure and an auxiliary capacitor Cs on an insulating substrate made of glass or the like. The TFT is provided at the intersection of the gate wiring 2 and the signal wiring 3, and the semiconductor thin film 4 is provided on the gate electrode 5.

FIG. 10 is a sectional view taken along the line XX shown in FIG. As shown in the figure, a gate electrode 5 is formed on a substrate 1 by patterning, and a semiconductor thin film 4 made of polycrystalline silicon or the like is formed thereon via a gate insulating film 12.
Are formed by patterning. Impurities are selectively implanted into the semiconductor thin film 4 to form a source region S and a drain region D of the TFT. A channel region of the TFT is formed immediately above the gate electrode 5 between the source region S and the drain region D. The TFT having the bottom gate structure is covered with an interlayer insulating film 14. The signal wiring 3 is formed thereon, and is electrically connected to the source region S of the TFT via a contact hole CONS opened in the interlayer insulating film 14. Also, the intermediate wiring 3 is formed in the same layer as the signal wiring 3.
a is formed, and is electrically connected to the drain region D of the TFT via a contact hole COND opened in the interlayer insulating film 14. The signal wiring 3 and the intermediate wiring 3a are covered with a flattening film 90, and the pixel electrode 10 is formed thereon by patterning. The pixel electrode 10 has a flattening film 90
Is electrically connected to the intermediate wiring 3a via a contact hole CONP opened at the bottom. As is apparent from FIG. 9, the contact holes CONP and COND overlap in a plan view.

[0004]

By the way, in order to reduce the resistance of the gate wiring 2, it is effective to increase the thickness of the metal film constituting the gate wiring 2 to, for example, 250 nm. In that case, the gate electrode 5 belonging to the same layer as the gate wiring 2 also becomes thick. As a result, as shown in FIG.
The tapered portion formed at the time of etching becomes conspicuous. When the tapered portion of the gate electrode 5 becomes remarkable,
Micro holes are generated in the semiconductor thin film 4 made of polycrystalline silicon or the like disposed thereon via the gate insulating film 12. The micro holes are formed in the semiconductor thin film 4 by, for example, irradiation with a laser beam.
Is likely to occur in a region just overlapping the tapered portion of the gate electrode 5. In this state, if the interlayer insulating film 14 is etched for forming the contact holes CONS and COND, the etchant penetrates the underlying gate insulating film 12 through the fine holes of the semiconductor thin film 4 described above, and The gate electrode 5 is short-circuited.
This leads to the occurrence of pixel point defects, and the image quality is degraded. Further, the contact hole C is formed in the interlayer insulating film 14.
When the ONS and COND are opened, the interlayer insulating film 14 may be excessively etched due to variations in etching conditions. When the overetch occurs in this manner, when the signal wiring 3 made of metal aluminum or the like is formed after the formation of the contact hole, the gate electrode 5 located in the lower layer is formed.
Or short circuit with the gate wiring 2. As a result, a line defect in which a vertical streak appears on the screen occurs, and the image quality deteriorates.

[0005]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, an object of the present invention is to prevent point defects and line defects in a thin film semiconductor device used for a display or the like. The following measures were taken in order to achieve this purpose.
That is, the first surface of the present invention, signal wiring, gate wiring,
A circuit is formed by forming a thin film transistor and a thin film transistor on an insulating substrate. The thin film transistor includes a semiconductor thin film in which a source region and a drain region are formed with a channel region therebetween, and the semiconductor thin film with a gate insulating film interposed therebetween. A gate electrode connected to the gate electrode, the signal wiring is formed above the semiconductor thin film via an interlayer insulating film, and the gate wiring is connected to the gate electrode. In a thin film semiconductor device connected to at least one of a source region and a drain region formed in the semiconductor thin film via a contact hole opened in an insulating film, a portion of the semiconductor thin film in which a source region or a drain region is formed is removed. The contact hole extends along the signal wiring and connects the source or drain region to the signal wiring. Characterized in that it expanded the distance to the channel region overlapping the. Preferably, the thin film transistor has a bottom gate type laminated structure in which the gate electrode overlaps a channel region of the semiconductor thin film via a gate insulating film from the substrate side. In this case, the gate electrode has a smaller thickness than the gate wiring.

A second aspect of the present invention is that a signal wiring, a gate wiring, and a thin film transistor are formed on an insulating substrate to form a circuit, and the thin film transistor has a source with a channel region therebetween. The semiconductor device has a bottom-gate stacked structure including a semiconductor thin film in which a region and a drain region are formed, and a gate electrode overlapping a channel region of the semiconductor thin film from the substrate side with a gate insulating film interposed therebetween. A signal line connected to a gate electrode, formed above the semiconductor thin film via an interlayer insulating film, and a source region and a drain region formed in the semiconductor thin film via a contact hole opened in the interlayer insulating film; A thin film semiconductor device connected to at least one of the source region and the drain region connected to a signal line through a contact hole. The lower along the edges of the semiconductor thin film located between until the channel region that overlaps with the electrode, and wherein placing the protective member in and floating potential is formed of the same material as the gate electrode. Preferably, the gate electrode has a smaller thickness than a gate wiring.

A third aspect of the present invention is to form a circuit by forming a signal wiring, a gate wiring, a thin film transistor, and an electrode driven by the thin film transistor on an insulating substrate. A stacked structure including a semiconductor thin film in which a source region and a drain region are formed with a region interposed therebetween, and a gate electrode overlapping a channel region of the semiconductor thin film via a gate insulating film; Connected to an electrode, the signal wiring was disposed above the semiconductor thin film via a first interlayer insulating film, and formed in the semiconductor thin film via a contact hole opened in the first interlayer insulating film. Connected to the source region, the electrode is disposed above the signal line via a second interlayer insulating film, and connected to the drain region via an intermediate line formed of the same material as the signal line. Is In the film semiconductor device, the intermediate wiring is connected to the drain region via a first contact hole opened in a first interlayer insulating film, and the electrode has a second contact hole opened in a second interlayer insulating film. And the first contact hole and the second contact hole are separated from each other so that their positions do not overlap with each other. Preferably, the first contact hole for connecting to the drain region is located farther from the channel region overlapping the gate electrode than the second contact hole for connecting to the electrode. Further, the thin film transistor has a bottom gate type laminated structure in which the gate electrode overlaps a channel region of the semiconductor thin film from the substrate side via a gate insulating film. In this case, the gate electrode has a smaller thickness than the gate wiring.

A fourth aspect of the present invention is that a signal wiring, a gate wiring, and a thin film transistor are formed on an insulating substrate to form a circuit, and the thin film transistor has a source region and a channel region with a channel region therebetween. The semiconductor device has a laminated structure including a semiconductor thin film on which a drain region is formed and a gate electrode overlapping a channel region of the semiconductor thin film via a gate insulating film, wherein the gate wiring is connected to the gate electrode, and the signal wiring is Is formed above the semiconductor thin film via an interlayer insulating film, and is connected to at least one of a source region and a drain region formed in the semiconductor thin film via a contact hole opened in the interlayer insulating film. In the thin-film semiconductor device, a portion of the semiconductor thin film located below the signal wiring with the contact hole therebetween is at least larger than the inner diameter of the contact hole. Characterized in that it extends outside the width of the [mu] m. Preferably, the thin film transistor has a bottom gate type laminated structure in which the gate electrode overlaps a channel region of the semiconductor thin film via a gate insulating film from the substrate side. In this case, the gate electrode has a smaller thickness than the gate wiring.

According to the first aspect of the present invention, the portion of the semiconductor thin film where the source region is formed is extended along the signal wiring,
The distance from the contact hole connecting the source region to the signal wiring to the channel region overlapping the gate electrode is increased. As described above, by increasing the distance between the TFT and the contact hole, a short circuit between the signal wiring and the gate electrode caused by over-etching of the contact hole can be prevented. According to the second aspect of the present invention, the same material as the gate electrode is formed on the lower side along the edge of the semiconductor thin film located between the source region or the drain region and the channel region overlapping the gate electrode. And a protective member at a floating potential. The above-described overetch often proceeds along the edge of the semiconductor thin film. Therefore, by forming a floating potential protection member between the contact hole and the thin film transistor TFT using a gate electrode material, it is possible to prevent the progress of overetch. Thereby, a short-circuit defect can be prevented. According to the third aspect of the present invention, the contact hole connecting the pixel electrode to the intermediate wiring and the contact hole connecting the intermediate wiring to the drain region are separated from each other so as not to overlap with each other. In particular, a contact hole for making a connection to the drain region is located farther from the channel region than a contact hole for making a connection to the pixel electrode. As described above, by dividing the contact hole provided for applying an image signal to the pixel electrode into two, it is possible to prevent a short-circuit defect caused by overetching or the like. According to the fourth aspect of the present invention, with the contact hole connecting the signal wiring and the source region therebetween, the portion of the semiconductor thin film located below the signal wiring is at least 5 μm from the inner diameter of the contact hole.
It extends outward with a width of. In this way, by laying the semiconductor thin film under a certain width under the signal wiring, it is possible to prevent disconnection and shape defect of the signal wiring, to suppress variation in characteristics, and to prevent adverse effects due to overetching. Can be. According to the fifth aspect of the present invention, the gate electrode is thinner than the gate wiring. In particular,
By selectively reducing the thickness of the gate electrode, the influence of the tapered portion can be suppressed. That is, it is possible to prevent the semiconductor thin film located immediately above the tapered portion of the gate electrode from having a large number of micropores due to laser crystallization or the like. As a result, short-circuit defects via the minute holes can be prevented, and as a result, point defects can be prevented.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic plan view showing an example of the thin film semiconductor device according to the present invention. To facilitate understanding, portions corresponding to those of the conventional thin film semiconductor device shown in FIG. 9 are denoted by corresponding reference numerals. As shown in the drawing, the thin-film semiconductor device has a circuit in which a signal wiring 3, a gate wiring 2, and a thin film transistor TFT are formed on an insulating substrate. On the surface of the substrate, lower wirings including the gate wirings 2 and the auxiliary capacitance wirings 20 are formed along the row direction. The gate electrode 5 is patterned at the same potential as the gate wiring 2 and at the same time.
An insulating film is formed so as to cover gate line 2, auxiliary capacitance line 20 and gate electrode 5. In particular, a portion of the insulating film formed on the gate electrode 5 becomes a gate insulating film. Further, a semiconductor thin film 4 constituting an element region of the thin film transistor TFT is formed on the insulating film. In this case, the semiconductor thin film 4 is made of polycrystalline silicon crystallized by laser light irradiation. A part of the semiconductor thin film 4 extends on the auxiliary capacitance line 20 and forms an auxiliary capacitance Cs. On the semiconductor thin film 4, an upper wiring including the signal wiring 3 in a row is formed via an interlayer insulating film. The signal wiring 3 is electrically connected to the source region of the thin film transistor TFT via the source side contact hole CONS opened in the interlayer insulating film. Further, a pixel electrode (not shown) is formed on the signal wiring 3 via a flattening layer. The pixel electrodes are contact holes COND, CON
It is electrically connected to the drain region of the thin film transistor TFT via P. When a transmissive display device is manufactured, a transparent conductive film such as ITO is used for a pixel electrode. In the case of a reflective display device, a metal material such as aluminum or silver is used for a pixel electrode.

The thin film transistor TFT includes a semiconductor thin film 4 having a source region and a drain region formed with a channel region Ch therebetween, and a semiconductor thin film 4 having a gate insulating film interposed therebetween.
And a gate electrode 5 overlapping the channel region Ch. The gate wiring 2 is connected to the gate electrode 5. The signal wiring 3 is formed above the semiconductor thin film 4 via an interlayer insulating film, and is connected to a source region formed in the semiconductor thin film 4 via a contact hole CONS opened in the interlayer insulating film. In some cases, depending on the circuit configuration, the signal wiring 3 may be electrically connected to the drain region of the thin film transistor TFT via a contact hole. As a first feature of the present invention, a portion of the semiconductor thin film 4 in which the source region is formed is extended along the signal wiring 3 and overlaps with the gate electrode 5 from a contact hole CONS connecting the source region and the signal wiring 3. The distance to the channel region Ch is increased. As described above, by increasing the distance between the contact hole CONS and the thin film transistor TFT, it is possible to prevent short-circuit defects between wirings caused by overetching of the contact hole CONS.

The thin film transistor TFT includes a semiconductor thin film 4 having a source region and a drain region formed with a channel region Ch therebetween, and a semiconductor thin film 4 having a gate insulating film interposed therebetween.
And a gate electrode 5 overlapping the channel region Ch from the substrate side. That is,
The gate electrode 5 is located below the semiconductor thin film 4. As described above, the gate wiring 2 is connected to the gate electrode 5. The signal wiring 3 is formed above the semiconductor thin film 4 with an interlayer insulating film interposed therebetween, and has a contact hole CO opened in the interlayer insulating film.
It is connected to a source region formed in the semiconductor thin film 4 via NS. As a second feature of the present invention, along the edge of the semiconductor thin film 4 located from the source region connected to the signal wiring 3 via the contact hole CONS to the channel region Ch overlapping the gate electrode 5. On the lower side, a protective member 2F formed of the same material as the gate electrode 5 and at a floating potential (floating) is arranged. By arranging the protection member 2F, it is possible to suppress an overetch that proceeds along the edge of the semiconductor thin film 4. In this embodiment, the protection member 2F is also provided between the channel region Ch and the contact hole COND on the drain region side.

As described above, the signal wiring 3 is disposed above the semiconductor thin film 4 via the first interlayer insulating film, and is connected to the semiconductor thin film 4 via the contact hole CONS opened in the first interlayer insulating film. It is connected to the formed source region. On the other hand, the pixel electrode (not shown) is disposed above the signal wiring 3 via a second interlayer insulating film (flattening film), and is disposed via an intermediate wiring 3a formed of the same material as the signal wiring 3. Connected to the drain region. The intermediate wiring 3a is connected to the drain region via a first contact hole COND opened in the first interlayer insulating film. The pixel electrode is connected to the intermediate wiring 3a via a second contact hole CONP opened in the second interlayer insulating film. As a third feature of the present invention, the first contact hole COND and the second contact hole CONP are arranged so that their positions do not overlap each other. In particular, the first contact hole COND for connection to the drain region is located farther from the channel region Ch than the second contact hole CONP for connection to the pixel electrode. Thus, CO
By separating ND and CONP and setting COND at a position far from the TFT, it is possible to prevent a short circuit between wirings due to over-etching of a contact hole or the like.

As described above, the signal wiring 3 is formed above the semiconductor thin film 4 via the interlayer insulating film, and is formed in the semiconductor thin film 4 via the contact hole CONS opened in the interlayer insulating film. Connected to As a fourth feature of the present invention, a contact hole CONS
The portion of the semiconductor thin film 4 located below the signal wiring 3 with the space therebetween is extended outward with a width of at least 5 μm from the inner diameter of the contact hole CONS. By arranging the semiconductor thin film 4 with a margin below the signal wiring 3 in this way, it is possible to prevent disconnection and shape failure of the signal wiring 3 and also to prevent adverse effects due to overetching.

As a fifth feature of the present invention, the TFT has a bottom gate structure, and the gate electrode 5 is connected to the gate wiring 2.
It is formed thinner. For example, while the gate wiring 2 has a laminated structure of the surface layer SL and the inner layer IL, the gate electrode 5 includes only the surface layer SL. As described above, by reducing the thickness of the gate electrode 5, it is possible to prevent the semiconductor thin film 4 located above the tapered portion of the gate electrode 5 from generating micro holes due to laser beam irradiation.

FIG. 2 is a sectional view taken along line X1-X1 in FIG. As shown, a signal wiring 3 is formed on a substrate 1. The upper portion of the signal wiring 3 is covered with an insulating layer 90 functioning as a flattening film. The source region of the semiconductor thin film 4 extends below the signal wiring 3 via an interlayer insulating film 14. Under the semiconductor thin film 4, the above-mentioned floating potential protection member 2F is formed of the same material as the gate electrode via the gate insulating film 12 along the edge thereof.

FIG. 3 is a sectional view taken along line Y1-Y1 shown in FIG. As illustrated, the floating protective member 2F described above is patterned in an island shape below the semiconductor thin film 4 extending along the signal wiring with a gate insulating film 12 interposed therebetween. Generally, the overetch that occurs when the contact hole is opened proceeds along the edge of the semiconductor thin film 4. In order to prevent this, the protection member 2F is disposed below the semiconductor thin film 4, and the progress of the overetch is stopped at the step of the protection member 2F.

FIG. 4 is a sectional view taken along the line Y2-Y2 shown in FIG. On a substrate 1 made of glass or the like,
A drain region of the semiconductor thin film 4, an intermediate wiring 3 a of the same material as the signal wiring 3, and a pixel electrode 10 are formed in this order from the bottom. The intermediate wiring 3a is electrically connected to the drain region of the semiconductor thin film 4 via a contact hole COND opened in the interlayer insulating film 14. The pixel electrode 10 is electrically connected to the lower intermediate wiring 3a via a contact hole CONP opened in the upper interlayer insulating film 90. Unlike the conventional structure shown in FIG. 9, COND and CONP are separated from each other. Further, COND is disposed at a portion farther from the TFT than CONP. Since both contact holes COND and CONP are formed by etching in a flat portion, processing accuracy can be improved.

FIG. 5 is a sectional view taken along the line X3-X3 shown in FIG. As shown, the signal wiring 3
Is a contact hole CON opened in the interlayer insulating film 14.
It is electrically connected to the lower semiconductor thin film 4 via S. In this case, the portion of the semiconductor thin film 4 located below the signal wiring 3 extends outward with a width W of at least 5 μm from the inner diameter of the contact hole CONS. Thus, by providing the semiconductor thin film 4 with a margin below the signal wiring 3, it is possible to prevent the adverse effect of the overetch.
In addition, errors in mask alignment can be absorbed, and disconnection defects and shape defects of the signal wiring 3 can be suppressed.

FIG. 6 is a sectional view taken along the line Y4-Y4 shown in FIG. In the figure, a TFT portion and a gate wiring 2 portion are shown. In the TFT portion, the semiconductor thin film 4 is disposed on the gate electrode 5 via the gate insulating film 12. As is clear from the figure, the thickness of the gate electrode 5 is set smaller than that of the gate wiring 2. Thus, the amount of heat radiation when the semiconductor thin film 4 is irradiated with the laser light can be reduced, and the energy of the laser light can be efficiently used for crystallization of the semiconductor thin film 4. In the present embodiment, both the gate electrode 5 and the gate wiring 2 have a layered structure,
Is smaller than the number of layers forming the gate wiring 2. In the present embodiment, particularly, the gate electrode 5 is
L, and the gate wiring 2 has a surface layer S
It has a multilayer structure in which an inner layer IL is superimposed below L. Specifically, the inner layer IL is made of a metal having a lower electric resistance than the surface layer SL, and the surface layer SL is made of a metal having a higher melting point than the inner layer IL to protect the inner layer IL. For example, the inner layer IL is made of a metal mainly composed of aluminum, and the surface layer SL is made of a metal selected from molybdenum, tantalum, tungsten and chromium. As the inner layer IL, a pure metal of aluminum or an alloy obtained by adding aluminum to silicon until saturation is used. Thus, the inner layer IL having a low electric resistance
By using a multilayer structure in which a surface layer SL made of a refractory metal or the like is superposed on the gate wiring 2, it is possible to prevent an increase in wiring resistance and to cope with a large screen.

FIG. 7 is a schematic perspective view showing an example of an active matrix type liquid crystal display device assembled using the thin film semiconductor device according to the present invention. As illustrated, the display device has a panel structure including a pair of insulating substrates 101 and 102 and an electro-optical material 103 held between the pair of insulating substrates 101 and 102. A liquid crystal material is used as the electro-optic material 103. On the lower insulating substrate 101, a pixel array section 104 and a drive circuit section are integrally formed. The drive circuit section is divided into a vertical drive circuit 105 and a horizontal drive circuit 106. A terminal 107 for external connection is formed at the upper end of the peripheral portion of the insulating substrate 101. The terminal portion 107 is connected to a vertical drive circuit 105 and a horizontal drive circuit 106 via a wiring 108. A row-shaped gate wiring 109 and a column-shaped signal wiring 110 are formed in the pixel array unit 104. A pixel electrode 111 and a thin film transistor 112 for driving the pixel electrode 111 are formed at the intersection of the two wires. The gate electrode of the thin film transistor 112 is extended from the corresponding gate wiring 109, the drain region is connected to the corresponding pixel electrode 111, and the source region is connected to the corresponding signal wiring 110. The gate wiring 109 is connected to the vertical driving circuit 105, while the signal wiring 110 is connected to the horizontal driving circuit 106. The thin film transistor 112 for switching and driving the pixel electrode 111 and the thin film transistors included in the vertical drive circuit 105 and the horizontal drive circuit 106 are formed according to the present invention.
A counter electrode (not shown) is formed on the inner surface of the upper substrate 102.

FIG. 8 is a schematic partial sectional view showing another embodiment of the display device according to the present invention. In this embodiment, an organic electroluminescent element OLED is used as a pixel. OLED has anode A, organic layer 210 and cathode K
In order. The anode A is separated for each pixel, and is made of, for example, chromium and is basically light-reflective. The cathode K is commonly connected between the pixels, for example, the metal layer 21
1 and a transparent conductive layer 212, and is basically light transmissive. When a forward voltage (about 10 V) is applied between the anode A and the cathode K of the OLED having such a configuration, carriers such as electrons and holes are injected, and light emission is observed. The operation of the OLED is considered to be light emission by excitons formed by holes injected from the anode A and electrons injected from the cathode K.

On the other hand, a thin-film transistor TFT for driving an OLED has a gate electrode 5 formed on a substrate 1 made of glass or the like, a gate insulating film 12 overlaid on the upper surface thereof, and And a semiconductor thin film 4 overlying the gate electrode 5. The semiconductor thin film 4 is made of, for example, a silicon thin film polycrystallized by laser annealing. Thin film transistor TFT is OLE
A source region S, a channel region Ch, and a drain region D that serve as a path for a current supplied to D are provided. The channel region Ch is located just above the gate electrode 5. The thin film transistor TFT having the bottom gate structure is covered with an interlayer insulating film 14, on which the signal wiring 3 and the intermediate wiring 3a are formed. On these, the OLED described above is formed via another interlayer insulating film 91. The anode A of the OLED is electrically connected to the thin film transistor TFT via the intermediate wiring 3a.

[0024]

As described above, according to the first aspect of the present invention, a semiconductor thin film is extended along a signal wiring, and a contact hole for electrically connecting the semiconductor thin film and the signal wiring is formed.
The distance to the channel area has been increased. According to the second aspect of the present invention, a floating protection member made of the same material as the gate electrode is provided along the edge of the semiconductor thin film located between the contact hole and the channel region. According to the third aspect of the present invention, a contact hole connecting the drain region of the TFT and the intermediate wiring and a contact hole connecting the pixel electrode and the intermediate wiring are separated from each other, and the former is farther from the TFT than the latter. We arrange in position. Further, according to the fourth aspect of the present invention, the portion of the semiconductor thin film located below the signal wiring with the contact hole interposed therebetween extends outward with a width of at least 5 μm from the inner diameter of the contact hole. In addition, according to the fifth aspect of the present invention, the gate electrode of the TFT is thinner than the gate wiring. By combining these structures comprehensively, it is possible to prevent a short circuit between the semiconductor thin film and the gate electrode, thereby preventing a point defect of the display device. Further, a short circuit between the signal wiring and the gate electrode can be prevented, and a line defect of the display device can be prevented.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a thin film semiconductor device according to the present invention.

FIG. 2 is a sectional view taken along the line X1-X1 shown in FIG.

FIG. 3 is a sectional view taken along line Y1-Y1 shown in FIG.

FIG. 4 is a sectional view taken along the line Y2-Y2 shown in FIG.

FIG. 5 is a sectional view taken along line X3-X3 shown in FIG.

FIG. 6 is a sectional view taken along line Y4-Y4 shown in FIG.

FIG. 7 is a schematic perspective view showing one example of a liquid crystal display device according to the present invention.

FIG. 8 is a cross-sectional view showing one example of an electroluminescent display device according to the present invention.

FIG. 9 is a schematic plan view showing an example of a conventional thin film semiconductor device.

FIG. 10 is a schematic sectional view showing an example of a conventional thin film semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Gate wiring, 3 ... Signal wiring, 3a ... Intermediate wiring, 4 ... Semiconductor thin film, 5 ...
・ Gate electrode, 10: pixel electrode, 2F: protective member

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masahiro Fujino 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Hiroshi Komatsu 50 Ogawakamifunagi, Higashiura-cho, Chita-gun, Aichi Prefecture d. Sty Elcidi Co., Ltd. (72) Inventor Masaki Munakata 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F-term (reference) 2H092 JA26 JA29 JA38 JA40 JA42 JA44 JA46 JB13 JB23 JB32 JB57 JB51 JB57 JB63 JB69 KA04 KA07 KA16 KA18 MA05 MA08 MA13 MA17 MA30 NA13 NA15 PA07 5C094 AA21 BA03 BA27 BA43 CA19 CA24 DA14 DA15 DB04 EA04 EA07 EB02 FB12 FB14 FB15 5F110 AA26 BB01 CC08 EE04 EE23 NG03 NN23 EE03 GG03 NN23 GG03

Claims (36)

[Claims] A circuit is formed by forming a signal wiring, a gate wiring, and a thin film transistor on an insulating substrate, and the thin film transistor has a source region and a drain region formed with a channel region therebetween. A laminated structure including a semiconductor thin film and a gate electrode overlapping a channel region of the semiconductor thin film via a gate insulating film, wherein the gate wiring is connected to the gate electrode, and the signal wiring is an interlayer insulating film. A thin film semiconductor device formed above the semiconductor thin film through a contact hole and connected to at least one of a source region and a drain region formed in the semiconductor thin film through a contact hole opened in the interlayer insulating film; Alternatively, a portion of the semiconductor thin film on which the drain region is formed is extended along the signal wiring, and the source or drain region and the signal wiring are extended. From the contact hole for connecting the thin film semiconductor device characterized by expanded the distance to the channel region overlapping the gate electrode. 2. The thin film semiconductor according to claim 1, wherein the thin film transistor has a bottom gate type laminated structure in which the gate electrode overlaps a channel region of the semiconductor thin film from a substrate side via a gate insulating film. apparatus. 3. The thin film semiconductor device according to claim 2, wherein said gate electrode has a smaller thickness than a gate wiring. 4. A circuit is formed by forming a signal wiring, a gate wiring, and a thin film transistor on an insulating substrate, and the thin film transistor has a source region and a drain region formed with a channel region therebetween. A bottom gate type laminated structure including a semiconductor thin film and a gate electrode overlapping a channel region of the semiconductor thin film via a gate insulating film from the substrate side, wherein the gate wiring is connected to the gate electrode; The wiring is formed above the semiconductor thin film via an interlayer insulating film, and is connected to at least one of a source region and a drain region formed in the semiconductor thin film via a contact hole opened in the interlayer insulating film. In the thin film semiconductor device, the source region or the drain region connected to the signal wiring through a contact hole may be used to form the chip overlapping the gate electrode. The lower along the edges of the semiconductor thin film located between the up channel region, a thin film semiconductor device characterized by disposing a protective member in and floating potential is formed of the same material as the gate electrode. 5. The thin film semiconductor device according to claim 4, wherein said gate electrode has a smaller thickness than a gate wiring. 6. A circuit is formed by forming a signal wiring, a gate wiring, a thin film transistor, and an electrode driven by the thin film transistor on an insulating substrate. A stacked structure including a semiconductor thin film in which a region and a drain region are formed, and a gate electrode overlapping a channel region of the semiconductor thin film with a gate insulating film interposed therebetween, wherein the gate wiring is connected to the gate electrode; The signal wiring is disposed above the semiconductor thin film via the first interlayer insulating film, and is connected to a source region formed in the semiconductor thin film via a contact hole opened in the first interlayer insulating film, A thin film semiconductor device in which the electrode is disposed above the signal wiring via a second interlayer insulating film and is connected to the drain region via an intermediate wiring formed of the same material as the signal wiring; Wherein the intermediate wiring is connected to the drain region via a first contact hole opened in a first interlayer insulating film, and the electrode is connected via a second contact hole opened in a second interlayer insulating film. A thin-film semiconductor device connected to the intermediate wiring, wherein the first contact hole and the second contact hole are separated so that their positions do not overlap with each other. 7. The device according to claim 6, wherein the first contact hole for connection to the drain region is located farther from the channel region overlapping the gate electrode than the second contact hole for connection to the electrode. Thin film semiconductor device. 8. The thin-film semiconductor according to claim 6, wherein the thin-film transistor has a bottom-gate stacked structure in which the gate electrode overlaps a channel region of the semiconductor thin film from a substrate side via a gate insulating film. apparatus. 9. The thin film semiconductor device according to claim 8, wherein said gate electrode has a smaller thickness than a gate wiring. 10. A circuit is formed by forming a signal wiring, a gate wiring, and a thin film transistor on an insulating substrate, and the thin film transistor has a source region and a drain region formed with a channel region therebetween. A laminated structure including a semiconductor thin film and a gate electrode overlapping a channel region of the semiconductor thin film via a gate insulating film, wherein the gate wiring is connected to the gate electrode, and the signal wiring is an interlayer insulating film. A thin film semiconductor device that is formed in a layer above the semiconductor thin film through a contact hole and is connected to at least one of a source region and a drain region formed in the semiconductor thin film through a contact hole opened in the interlayer insulating film; The portion of the semiconductor thin film located below the signal wiring with the contact hole therebetween is at least 5 μm wider than the inner diameter of the contact hole. A thin-film semiconductor device characterized by being extended to a side. 11. The thin film semiconductor according to claim 10, wherein said thin film transistor has a bottom gate type laminated structure in which said gate electrode overlaps a channel region of said semiconductor thin film from a substrate side via a gate insulating film. apparatus. 12. The thin film semiconductor device according to claim 11, wherein said gate electrode has a smaller thickness than a gate wiring. 13. A pair of substrates facing each other are joined to each other, and a liquid crystal is disposed in a gap between the two substrates. A signal wiring, a gate wiring, a thin film transistor, and a pixel electrode are formed on one substrate, and the other substrate is formed. Has a panel structure in which a counter electrode is formed, and the thin film transistor overlaps a semiconductor thin film in which a source region and a drain region are formed with a channel region therebetween and a channel region of the semiconductor thin film via a gate insulating film A gate wiring, the gate wiring being connected to the gate electrode, the signal wiring being formed above the semiconductor thin film via an interlayer insulating film, and having an opening in the interlayer insulating film; A liquid crystal display device connected to a source region formed in the semiconductor thin film via a contact hole, and the pixel electrode connected to a drain region formed in the semiconductor thin film Extending a portion of the semiconductor thin film on which the source region is formed along the signal wiring, and increasing a distance from a contact hole connecting the source region and the signal wiring to the channel region overlapping the gate electrode. A liquid crystal display device characterized by being made into a liquid crystal display. 14. The liquid crystal display according to claim 13, wherein the thin film transistor has a bottom gate type laminated structure in which the gate electrode overlaps a channel region of the semiconductor thin film via a gate insulating film from the substrate side. apparatus. 15. The liquid crystal display device according to claim 14, wherein the gate electrode has a smaller thickness than a gate wiring. 16. A pair of substrates facing each other are joined to each other, and a liquid crystal is arranged in a gap between the substrates. A signal wiring, a gate wiring, a thin film transistor, and a pixel electrode are formed on one substrate, and the other substrate is formed. Has a panel structure in which a counter electrode is formed. The thin film transistor has a semiconductor thin film in which a source region and a drain region are formed with a channel region therebetween, and a substrate in a channel region of the semiconductor thin film via a gate insulating film. A bottom gate type laminated structure including a gate electrode overlapping from the side, the gate wiring is connected to the gate electrode, and the signal wiring is formed above the semiconductor thin film via an interlayer insulating film; The pixel electrode is connected to a source region formed in the semiconductor thin film through a contact hole opened in the interlayer insulating film, and the pixel electrode is connected to a drain region formed in the semiconductor thin film. In the liquid crystal display device, the same as the gate electrode, the lower side along the edge of the semiconductor thin film located from the source region connected to the signal wiring through the contact hole to the channel region overlapping the gate electrode A liquid crystal display device comprising a protective member formed of a material and having a floating potential. 17. The liquid crystal display device according to claim 16, wherein the gate electrode has a smaller thickness than a gate wiring. 18. A pair of substrates facing each other are joined to each other, and liquid crystal is arranged in a gap between the two substrates. A signal wiring, a gate wiring, a thin film transistor, and a pixel electrode are formed on one substrate, and the other substrate is formed. Has a panel structure in which a counter electrode is formed, and the thin film transistor overlaps a semiconductor thin film in which a source region and a drain region are formed with a channel region therebetween and a channel region of the semiconductor thin film via a gate insulating film A gate wiring, the gate wiring being connected to the gate electrode, the signal wiring being disposed above the semiconductor thin film via a first interlayer insulating film, The pixel electrode is connected to a source region formed in the semiconductor thin film via a contact hole opened in the inter-insulation film, the pixel electrode is disposed above the signal wiring via a second interlayer insulation film, and is connected to the signal wiring. In a liquid crystal display device connected to the drain region through an intermediate wiring formed of one material, the intermediate wiring is connected to the drain region through a first contact hole opened in a first interlayer insulating film. The pixel electrode is connected to the intermediate wiring via a second contact hole opened in the second interlayer insulating film, and the first contact hole and the second contact hole are separated so that their positions do not overlap with each other. A liquid crystal display device comprising: 19. The method according to claim 18, wherein the first contact hole for connecting to the drain region is located farther from the channel region overlapping the gate electrode than the second contact hole for connecting to the pixel electrode.
The liquid crystal display device according to the above. 20. The liquid crystal display according to claim 18, wherein the thin film transistor has a bottom gate type laminated structure in which the gate electrode overlaps a channel region of the semiconductor thin film via a gate insulating film from a substrate side. apparatus. 21. The liquid crystal display device according to claim 20, wherein the gate electrode has a smaller thickness than a gate wiring. 22. A pair of substrates facing each other, which are joined to each other, and a liquid crystal is arranged in a gap between the two substrates. A signal wiring, a gate wiring, a thin film transistor, and a pixel electrode are formed on one substrate, and the other substrate is formed. Has a panel structure in which a counter electrode is formed, and the thin film transistor overlaps a semiconductor thin film in which a source region and a drain region are formed with a channel region therebetween and a channel region of the semiconductor thin film via a gate insulating film A gate wiring, the gate wiring being connected to the gate electrode, the signal wiring being formed above the semiconductor thin film via an interlayer insulating film, and having an opening in the interlayer insulating film; In a liquid crystal display device connected to a source region formed in the semiconductor thin film through a contact hole and the pixel electrode is connected to a drain region formed in the semiconductor thin film. , Portions of the semiconductor thin film which is located below the signals between the contact hole wiring liquid crystal display device characterized in that it extends outwardly of at least 5μm in width than the inner diameter of the contact hole. 23. The liquid crystal display according to claim 22, wherein the thin film transistor has a bottom gate type laminated structure in which the gate electrode overlaps a channel region of the semiconductor thin film from a substrate side via a gate insulating film. apparatus. 24. The liquid crystal display device according to claim 23, wherein the gate electrode has a smaller thickness than a gate wiring. 25. A circuit is formed by forming a signal wiring, a gate wiring, a thin film transistor, and an electroluminescence element driven thereby on an insulating substrate, wherein the thin film transistor has a channel region therebetween. A stacked structure including a semiconductor thin film on which a source region and a drain region are formed, and a gate electrode overlapping a channel region of the semiconductor thin film via a gate insulating film, wherein the gate wiring is connected to the gate electrode. The signal wiring is formed above the semiconductor thin film via an interlayer insulating film, and is connected to a source region formed in the semiconductor thin film via a contact hole opened in the interlayer insulating film; The luminescent element is an electroluminescent display device connected to a drain region formed in the semiconductor thin film, The portion of the semiconductor thin film on which the source region is formed is extended along the signal wiring, and the distance from the contact hole connecting the source region and the signal wiring to the channel region overlapping the gate electrode is increased. An electroluminescent display device, characterized in that: 26. The electroluminescence according to claim 25, wherein the thin film transistor has a bottom gate type laminated structure in which the gate electrode overlaps a channel region of the semiconductor thin film from a substrate side via a gate insulating film. Display device. 27. The electroluminescent display device according to claim 26, wherein the gate electrode has a smaller thickness than a gate wiring. 28. A circuit is formed by forming a signal wiring, a gate wiring, a thin film transistor, and an electroluminescent element driven by the thin film transistor on an insulating substrate, wherein the thin film transistor has a channel region therebetween. And a gate electrode that overlaps a channel region of the semiconductor thin film via a gate insulating film from the substrate side with a bottom gate type stacked structure, wherein the gate wiring is The signal wiring is formed in a layer above the semiconductor thin film via an interlayer insulating film, and is connected to a source region formed in the semiconductor thin film via a contact hole opened in the interlayer insulating film. The electroluminescent device is connected to a drain region formed in the semiconductor thin film. In the display device, the same material as the gate electrode is formed on the lower side along the edge of the semiconductor thin film located between the source region connected to the signal wiring through the contact hole and the channel region overlapping the gate electrode. An electroluminescent display device comprising a protective member formed and at a floating potential. 29. The electroluminescent display device according to claim 28, wherein the gate electrode has a smaller thickness than a gate wiring. 30. A circuit is formed by forming a signal wiring, a gate wiring, a thin film transistor, and an electroluminescence element driven by the signal wiring on an insulating substrate, wherein the thin film transistor has a channel region therebetween. A stacked structure including a semiconductor thin film on which a source region and a drain region are formed, and a gate electrode overlapping a channel region of the semiconductor thin film via a gate insulating film, wherein the gate wiring is connected to the gate electrode. The signal wiring is disposed above the semiconductor thin film via a first interlayer insulating film, and is connected to a source region formed in the semiconductor thin film via a contact hole opened in the first interlayer insulating film. The electroluminescent element is disposed above the signal wiring via a second interlayer insulating film, and is formed of an intermediate wiring formed of the same material as the signal wiring. In the electroluminescence display device connected to the drain region via the first wiring, the intermediate wiring is connected to the drain region via a first contact hole opened in a first interlayer insulating film, An electrode connected to the intermediate wiring through a second contact hole opened in the second interlayer insulating film, wherein the first contact hole and the second contact hole are separated so that their positions do not overlap with each other. Luminescence display device. 31. The device according to claim 30, wherein the first contact hole for connection to the drain region is located farther from the channel region overlapping the gate electrode than the second contact hole for connection to the pixel electrode.
An electroluminescent display device according to claim 1. 32. The electroluminescence device according to claim 30, wherein the thin film transistor has a bottom gate type laminated structure in which the gate electrode overlaps a channel region of the semiconductor thin film via a gate insulating film from a substrate side. Display device. 33. The electroluminescent display device according to claim 32, wherein the gate electrode has a smaller thickness than a gate wiring. 34. A circuit is formed by forming a signal wiring, a gate wiring, a thin film transistor, and an electroluminescence element driven by the thin film transistor on an insulating substrate, wherein the thin film transistor has a channel region interposed therebetween. A stacked structure including a semiconductor thin film on which a source region and a drain region are formed, and a gate electrode overlapping a channel region of the semiconductor thin film via a gate insulating film, wherein the gate wiring is connected to the gate electrode. The signal wiring is formed above the semiconductor thin film via an interlayer insulating film, and connected to a source region formed in the semiconductor thin film via a contact hole opened in the interlayer insulating film; Is an electroluminescent display device connected to a drain region formed in the semiconductor thin film; Parts of the semiconductor thin film which is located below the to the signal line between the Kutohoru is electroluminescent display device, characterized in that it extends outside the width of at least 5μm than the inner diameter of the contact hole. 35. The electroluminescence device according to claim 34, wherein the thin film transistor has a bottom gate type laminated structure in which the gate electrode overlaps a channel region of the semiconductor thin film via a gate insulating film from the substrate side. Display device. 36. The electroluminescent display device according to claim 35, wherein the gate electrode has a smaller thickness than a gate wiring.