JP3508295B2 - Method for manufacturing thin film transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor, and more particularly, to an LDD (Lightly Do
The present invention relates to a method of manufacturing an inverted stagger type thin film transistor having a ped drain structure.

[0002]

2. Description of the Related Art In recent years, active matrix LCDs
Higher definition of (AM-LCD) is more and more advanced. Along with this, miniaturization of thin film transistors (TFTs) used as switching elements in AM-LCDs has progressed, and when the channel length has become shorter, the electric field strength, especially the electric field strength near the drain, becomes extremely large. A high electric field lowers the channel mobility μ and also lowers the transconductance of the transistor. In addition, when the electric field is high like this,
Impact ionization near the drain
n) occurs, electron-hole pairs (hot carriers) are generated, which causes a short channel effect including fluctuations in the threshold voltage Vth, which has a significant influence on the reliability of the device. As a countermeasure against this, an LDD (lightly doped drain) structure is adopted for the thin film transistor to reduce the electric field strength near the drain.
By the way, when it is desired to increase the impurity concentration of the source / drain, the LDD region (low impurity concentration region) is overlapped with the gate electrode (in the region of the semiconductor layer facing the gate electrode).
Is being formed.

Conventionally, a method shown in FIG. 13 is known as a method of manufacturing a thin film transistor having such a structure. In this method, first, a conductive film of chromium (Cr) or the like is formed on a glass substrate 1, and the conductive film is patterned to form a gate electrode 2. Then, after depositing the gate insulating film 3 on the gate electrode 2 and the glass substrate 1, the semiconductor thin film 4 is deposited on the gate insulating film 3. Then, as shown in FIG. 13A, a first resist 5 having a length shorter than the length of the gate electrode 2 (gate length) is formed on the semiconductor thin film 4 above the gate electrode 2 by a photolithography technique. Is used for patterning, and phosphorus (P) is ion-implanted under a low concentration condition using the first resist 5 as a mask to form a low impurity concentration region 4A in the semiconductor thin film 4.

Next, after the first resist 5 is peeled off, a second resist 6 is applied on the semiconductor thin film 4 and the back surface of the glass substrate 1 is irradiated with exposure light using the gate electrode 2 as a mask. Expose. After that, development is performed to pattern the second resist 6 on the gate electrode 2 in a self-aligned manner as shown in FIG. Further, using the second resist 6 as a mask, phosphorus (P) is ion-implanted under a high concentration condition to form a high impurity concentration region 4B in the semiconductor thin film 4. By performing such a method, the gate electrode 2
The low impurity concentration region 4 in the semiconductor thin film 4 facing the
A and 4A are formed, and high impurity concentration regions (source / drain regions) are formed so as to be adjacent to the low impurity concentration regions 4A on the outer side in the gate length direction.
A thin film transistor having a structure can be formed.

[0005]

However, in such a conventional method of manufacturing a thin film transistor, since the first resist 5 cannot be patterned in a self-aligned manner, the exposure mask (reticle) is accurately aligned. Otherwise, there is a problem that a gap is generated between the gate electrode 2. When such a deviation occurs, problems occur such that the length of the low impurity concentration region 4A in the gate length direction is significantly different on both sides, or one of the low impurity concentration regions 4A disappears. This problem becomes remarkable especially when the element size is small or when the substrate has a large area. Further, in the conventional manufacturing method, even if the back surface exposure is performed, it is necessary to perform the ion implantation step twice, so that the steps are complicated.

According to the present invention, the LD which surely comprises the low concentration impurity region and the high concentration impurity region in one ion implantation step is used.
It is an object to provide a method for manufacturing a thin film transistor having a D structure.

[0007]

[0008]

The invention according to claim 1 is
A step of forming a gate electrode on the surface side of a light-transmitting insulating substrate; a step of forming a light-transmitting gate insulating film on the gate electrode and the insulating substrate; Forming a light-transmitting semiconductor thin film thereon, forming a light-transmitting impurity injection controlling thin film on the semiconductor thin film, and forming a first photoresist on the impurity injection controlling thin film. And then performing a first exposure, and patterning so that both side edges of the first photoresist in the gate length direction are positioned outside the both side edges of the gate electrode in the gate length direction by a predetermined dimension. Patterning the impurity implantation control thin film in a self-aligned manner with the first photoresist, and a positive second photoresist on the impurity implantation control thin film and the semiconductor thin film. A second exposure step of applying a strike, irradiating light from the back surface side of the insulating substrate using the gate electrode as a mask, and patterning the second photoresist on the gate electrode in a self-aligned manner; Second
A step of implanting impurity ions into the semiconductor thin film using the photoresist and the impurity implantation control thin film as a mask to form source / drain regions and low impurity concentration regions.

According to a second aspect of the present invention, a step of forming a gate electrode on the surface side of an insulating substrate having a light transmitting property, and a gate insulating film having a light transmitting property on the gate electrode and the insulating substrate. A step of forming a light-transmissive semiconductor thin film on the gate insulating film, a step of forming a light-transmissive impurity implantation control thin film on the semiconductor thin film, and the impurity After applying a positive type first photoresist on the implantation control thin film, a first exposure is performed from the back surface side of the insulating substrate so that both side edges in the gate length direction of the first photoresist are A step of patterning the gate electrode so as to be located within a predetermined dimension from both side edges of the gate electrode in the gate length direction; and a step of patterning the impurity implantation controlling thin film in a self-aligned manner with the first photoresist, The second positive photoresist was coated on the impurity implanted control thin film and the semiconductor thin film,
A second exposure is performed from the back surface side of the insulating substrate using the gate electrode as a mask so that both side edges of the second photoresist in the gate length direction are both side edges of the impurity implantation control thin film in the gate length direction. A step of patterning so as to be positioned inside a predetermined dimension, and depositing a metal thin film of a predetermined thickness on the second photoresist, the impurity implantation control thin film, and the semiconductor thin film, and from the top of the metal thin film Ion implantation to implant impurity ions into the semiconductor thin film to form source / drain regions and low impurity concentration regions.

According to a third aspect of the present invention, the metal thin film is selected from chromium, tungsten, molybdenum, titanium, tantalum, nickel and palladium, and silicide is formed at the interface between the semiconductor thin film and the metal thin film by the ion implantation. It is characterized by forming.

[0011]

[0012]

According to the first aspect of the present invention, the patterning is performed so that both side edges of the first photoresist in the gate length direction are positioned outside the both side edges of the gate electrode in the gate length direction by a predetermined dimension. The impurity implantation control thin film which is anisotropically etched by using the mask as a mask is also patterned so that both side edges in the gate length direction are located outside the both side edges in the gate length direction by a predetermined size. Also,
The positive type second photoresist is irradiated with exposure light from the back surface side of the insulating substrate to be patterned in a self-aligned manner on the gate electrode. Then, by using this second photoresist and the impurity implantation control thin film as a mask, it becomes possible to form the source / drain region and the low impurity concentration region by one-time ion implantation.

According to the second aspect of the present invention, by the first exposure having a large total exposure amount, both side edges of the first photoresist in the gate length direction are inwardly arranged by a predetermined dimension from both side edges of the gate electrode in the gate length direction. It can be patterned to be located. Similarly, the impurity implantation control thin film that is anisotropically etched using the first photoresist as a mask is also formed such that both side edge portions thereof are located inside the gate electrode in the gate length direction by a predetermined dimension. . By the exposure of the second photoresist, it is possible to perform patterning such that both side edges of the second photoresist in the gate length direction are located inside a predetermined dimension from both side edges of the impurity implantation controlling thin film in the gate length direction. In a state where a metal thin film is deposited on the impurity implantation control thin film and the second photoresist, both side edges of the gate electrode in the gate length direction and the surface of the metal thin film attached to the sidewall of the impurity implantation control thin film,
If the thickness of the metal thin film is set so that the positions of the metal thin film coincide with each other and ion implantation is performed, the semiconductor thin film has source / drain regions on the outside and low impurities on the inside with the positions of both side edges of the gate electrode as boundaries. It is possible to form a concentration region.
If the metal thin film is made of a refractory metal such as chromium, tungsten, molybdenum, titanium, tantalum, nickel, or palladium, a silicide layer is formed at a contact portion between the metal thin film and the semiconductor thin film due to implantation energy during ion implantation. Is formed, and this silicide layer can simultaneously function as an ohmic layer and a barrier metal layer. Further, by patterning this metal thin film, it becomes possible to use it as a source / drain electrode.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the method of manufacturing a thin film transistor according to the present invention will be described below with reference to the embodiments shown in the drawings. (Embodiment 1) FIGS. 1 to 3 show a method of manufacturing an inverted stagger type thin film transistor.
4A to 4C are process cross-sectional views showing Example 1 of the method. In this embodiment,
As shown in FIG. 1A, a chromium (Cr) film, for example, is formed on the surface of a light-transmitting insulating substrate 11 such as glass, and the chromium film is formed by using a photolithography technique and an etching technique. The gate electrode 12 is formed by processing. After that, the gate insulating film 1 made of SiO ₂ is formed on the entire surface.
3 is deposited using the CVD method. Then, a semiconductor thin film 14 made of intrinsic amorphous silicon is deposited on the gate insulating film 13 by the same CVD method. Further, an impurity implantation control thin film 15 made of silicon nitride is deposited on the semiconductor thin film 14 by the same CVD method. The gate insulating film 13, the semiconductor thin film 14, and the impurity implantation control thin film 15 each have optical transparency.
Further, these film formations can be performed in-situ using, for example, a multi-chamber system.

Next, as shown in FIG. 1A, a positive first photoresist 16 is applied on the impurity implantation control thin film 15, and then the normal condition is applied from the back surface side of the insulating substrate 11. Back surface (back surface) exposure as the first exposure is performed (for example, a light source; a mercury lamp 200 W, an exposure energy; 200 mJ / cm ² ). At this time, the gate electrode 12 serves as an exposure mask, and the first electrode is self-aligned with the gate electrode 12.
The photoresist 16 is exposed. In this embodiment, the first photoresist 16 is, for example, a phenol resin as an alkali-soluble polymer compound and o-naphthoquinonediazide as a photosensitizer. By such back surface exposure, as shown in FIG. 1A, a portion of the first photoresist 16 facing (facing) the gate electrode 12 becomes an unexposed portion 16A, and a portion not facing the gate electrode 12 is exposed. Light arrives and exposure unit 16
It becomes B. In the exposed portion 16B, the photochemical reaction converts o-naphthoquinonediazide into indenecarboxylic acid, which becomes soluble in the alkaline aqueous solution (developing solution). As a result, when the development is performed, as shown in FIG. 1B, the first pattern having the same plane size as the gate electrode 12 is formed.
The photoresist (unexposed portion 16A) 16 remains.

Next, using this first photoresist 16 as a mask, anisotropic etching such as RIE (reactive ion etching) is performed to form an impurity implantation control thin film 15 as shown in FIG. 2 (A). Pattern. afterwards,
The first photoresist 16 is peeled off, and the second photoresist 17 of the same type is applied again. Then, the same figure (A)
As shown in, the backside exposure is performed as the second exposure. The exposure conditions for the backside exposure are such that the total exposure amount is larger than that of the first exposure described above. Specifically, for example, a high-pressure mercury lamp of 1600 W is used as a light source, and the exposure energy is 8
00 mJ / cm ² . In this embodiment, both the output of the light source and the exposure time may be increased in order to increase the total exposure amount, and the output of the light source has the same exposure energy per unit time and only the exposure time is lengthened. You can
Further, the exposure time may be the same and the exposure energy per unit time may be changed. The graph of FIG. 12 shows the relationship between the exposure energy and the thinning (receding) dimension of the photoresist pattern with respect to the gate width in the back surface exposure. As can be seen from this graph, as the exposure energy increases, the photoresist pattern becomes thinner in proportion thereto. By utilizing this relationship, the first and second exposures of this embodiment can be performed. When such backside exposure as the second exposure is performed, as shown in FIG. 2A, the unexposed portion 17A is exposed to the resist 1 by the first exposure.
The width of 6 A, that is, the width in the gate length direction is narrower than that of the gate electrode 12. That is, in this second exposure, the total exposure amount is larger than that in the first exposure. The agent is affected by the exposure light, and the exposed portion 17B enters the shadowed region of the gate electrode 12. This second
When the photoresist 17 is developed, the second photoresist (unexposed portion 17A) 1 is formed into a shape as shown in FIG.
7 remains.

Next, as shown in FIG. 2B, the impurity implantation controlling thin film 15 and the second photoresist 17 (17).
Ions are implanted into the semiconductor thin film 14 using A) as a mask. In this embodiment, phosphorus (P), which is an n-type impurity, is ion-implanted under a high concentration condition. When this ion implantation is performed,
As shown in FIG. 2B, a high impurity concentration region 14A is formed because phosphorus ions are directly implanted into the exposed region of the semiconductor thin film 14 which is not covered with the impurity implantation control thin film 15. Since the impurity implantation controlling thin film 15 is formed in the gate electrode 12 in a self-aligned manner, the high impurity concentration region 14A is also formed in the gate electrode 12 in a self-aligned manner. The high impurity concentration regions 14A formed on both sides of the gate electrode 12 are source / drain regions. On the other hand, in the portion of the semiconductor thin film 14 which is covered only with the impurity implantation control thin film 15, since the impurity implantation control thin film 15 does not reach all of the incident ions, the concentration of implanted impurities decreases. Therefore, in this portion, the low impurity concentration region 1 joined to the high impurity concentration region 14A is formed.
4B is formed. This low impurity concentration region 14B is L
It becomes the DD area. By adjusting the film thickness of the impurity implantation control thin film 15, the impurity concentration of the low impurity concentration region 14B can be set appropriately. In addition, the semiconductor thin film 14 immediately below the second photoresist 17 (17A) remains as an intrinsic semiconductor because phosphorus ions cannot reach at all due to the blocking action of the second photoresist 17.

Next, after the second photoresist 17 is peeled off, a chromium (Cr) thin film 18 is deposited by the sputtering method as shown in FIG. Then, annealing is performed in a non-oxidizing atmosphere to react the chromium with the underlying silicon to form the chromium silicide layer 19 in a self-aligned manner.

Then, as shown in FIG. 3B, element isolation (patterning that leaves elements in an island shape) is performed by using a photolithography technique and a dry etching technique.
Then, only the chromium thin film 18 is selectively removed by wet etching. Then, after depositing an Al-Ti alloy film on the entire surface, a photolithography technique and R
The Al-Ti alloy film is processed using a dry etching technique such as IE to form the source / drain electrodes 20 as shown in FIG. 3 (C). In this way, the high impurity concentration region 14A is formed in self-alignment with the gate electrode 12, and the low impurity concentration region 14B is formed in the high impurity concentration region 14A.
The fabrication of the thin film transistor having the LDD structure, which is bonded to the inside of the, is completed.

In this embodiment, the semiconductor thin film 14 has a high impurity concentration region 14A and a low impurity concentration region 14B.
It can be formed by performing ion implantation once. Further, when patterning the impurity implantation control thin film 15 and the second photoresist 17 which serve as ion implantation masks, backside exposure can be performed using the gate electrode 12 as an exposure mask, so that an exposure mask (reticle, photomask, etc.) is separately provided. The patterning can be simplified because it is not necessary to use. Further, in such back surface exposure, patterning can be performed using the same mask (gate electrode 12) by simply changing the total exposure amount of the first exposure and the second exposure, and impurity implantation control can be performed. Of the thin film 15 for gates in the gate length direction and the second photoresist 17 (17
The distance from the edge of A) can be set. This distance corresponds to the length of the low impurity concentration region 14B in the gate length direction. In the second exposure, both side edges of the unexposed portion 17A of the second photoresist 17 in the gate length direction may be positioned inside by an equal distance from both side edges of the impurity implantation control thin film 15 in the gate length direction. Therefore, there is no room for the problem that the size and position of the low impurity concentration region is changed due to the misalignment of the mask as in the conventional case. As described above, in this embodiment, since the problem of alignment can be avoided in manufacturing, it is possible to surely form an inverted stagger type thin film transistor having an LDD structure even when a fine element or a substrate has a large area. Become.

In the present embodiment, the total exposure amount of the first exposure and the second exposure is set to be different with the exposure output and the exposure time as parameters. However, in order to recede the pattern edge portion of the unexposed portion 17A of the second photoresist 17 by a predetermined distance from both side edge portions of the impurity implantation control thin film 15, the total exposure amount is changed as in the first embodiment. In addition to the method, a method of diffracting the light wave so as to wrap around the geometric shadow portion of the gate electrode 12 can be adopted. Specifically, the degree of diffraction may be adjusted by changing the wavelength of light according to the size and shape of the gate electrode 12. The resist pattern width may be reduced by mixing fine particles that cause light scattering in the photoresist and adjusting the mixing ratio. In the present embodiment, the chromium thin film 18 on the semiconductor thin film 14 is removed after element isolation, but the invention is not limited to this, and the chromium thin film 18 after silicidation may be removed and then element isolation may be performed.

(Embodiment 2) FIGS. 4 to 6 are sectional views showing steps in Embodiment 2. This embodiment is an embodiment of a method of manufacturing an inverted staggered thin film transistor according to the invention of claim 1 , and has a so-called offset LDD structure in which a gate electrode and a low impurity concentration region do not overlap each other when seen in a plan view. The present invention relates to a method of manufacturing a thin film transistor. In the description of this embodiment,
The same members as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. First, in this embodiment, as shown in FIG. 4 (A), the insulating substrate 11 is manufactured by the same method as in the first embodiment.
A gate electrode 12, a gate insulating film 13, a semiconductor thin film 14, and an impurity implantation control thin film 15 are formed on top. And
A positive first photoresist 16 is applied on the impurity implantation control thin film 15, and a photomask 21 having a projection pattern having a longer length in the gate length direction than the gate electrode 12 is arranged above the gate electrode 12. Then, the first exposure is performed. In the figure, 16A is an unexposed area and 16B is an exposed area. Both side edges of the unexposed portion 16A in the gate length direction are set to be located outside the both side edges of the gate electrode 12 in the gate length direction by a predetermined dimension. Although the first photoresist is a positive type in this embodiment, a negative type photoresist may be used. When a negative photoresist is used, the projection pattern of the photomask is the reverse pattern of the projection pattern of the photomask 21.

Next, development is performed to form a pattern of the first photoresist 16 (unexposed portion 16A) as shown in FIG. 4 (B). Then, the first photoresist 16
Is used as a mask to anisotropically etch the impurity implantation control thin film 15. FIG. 5A shows a state where the first photoresist 16 is peeled off after anisotropically etching the impurity implantation control thin film 15. After that, FIG. 5 (B)
As shown in FIG.
Is applied, and a second exposure with a normal exposure amount is performed. This second
The so-called back exposure is performed by irradiating the back surface (back surface) of the insulating substrate 11 with exposure light. By this exposure, as shown in FIG. 5B, the second photoresist 17 is exposed to the gate electrode 12 in a self-aligned manner, so that the gate electrode 12 is exposed.
An unexposed portion 17A is formed in a region facing with, and exposed portions 17B are formed on both outer sides thereof.

Thereafter, as shown in FIG. 6A, development is performed to form a pattern of the second photoresist 17 (unexposed portion 17A). Next, phosphorus (P) is ion-implanted under a high concentration condition using the second photoresist 17 and the impurity implantation control thin film 15 as a mask. As a result, phosphorus is implanted into the exposed region of the semiconductor thin film 14 under a high concentration condition to form a high impurity concentration region 14A. Since the high impurity concentration region 14A is formed outside the edge portion of the impurity implantation control thin film 15 having a width wider than that of the gate electrode 12, it is naturally formed outside the gate electrode 12 in the gate length direction. In addition, since phosphorus ions do not reach the semiconductor thin film 14 immediately below the second photoresist 17 due to the blocking action of the second photoresist 17, it remains an intrinsic semiconductor. Further, some of the irradiation ions reach the semiconductor thin film 14 directly below the impurity implantation control thin film 15 in the portion which is not covered with the second photoresist 17 and thus become the low impurity concentration region 14B. The high impurity concentration region 14A becomes a source / drain region, and the low impurity concentration region 14B becomes an LDD region. In this embodiment, the low impurity concentration region 14B is formed outside the second photoresist 17 which is patterned in a self-aligned manner with the gate electrode 12. That is, the low impurity concentration region 14B
Has a so-called offset LDD structure formed outside the gate electrode 12.

Next, after the second photoresist 17 is peeled off, the chromium silicide layer 19 is formed on the surface of the high impurity concentration region 14A, the element isolation step, and the source / drain electrodes 20 by the same method as in the first embodiment. By performing the forming process of (1) and the like, the manufacturing of the thin film transistor as shown in FIG. 6B is completed.

Also in this embodiment, the high impurity concentration region 14A to be the source / drain region is formed as in the first embodiment.
And the low impurity concentration region 14B to be the LDD region can be formed by one-time ion implantation, and the number of ion implantation steps can be reduced. Further, since the back surface exposure is performed once in the step of forming the ion implantation mask, it is possible to reduce the number of exposure masks by one as compared with the conventional case. Note that FIG. 7 is a cross-sectional view of a so-called double-gate type photo sensor formed by using the manufacturing method of this embodiment. To manufacture this photosensor, after forming the structure shown in FIG.
The impurity implantation control thin film 15 is removed by, for example, wet etching, and then an upper gate insulating film 22 made of, for example, silicon nitride is deposited by a CVD method as shown in FIG. A conductive film is formed, and the conductive film is patterned to form the upper gate electrode 23. Since the photosensor formed in this manner has the low impurity concentration regions 14B on both sides of the intrinsic semiconductor portion which will be the photoelectric conversion semiconductor layer, when the device is miniaturized, the gate electrode 12 and the semiconductor thin film 14 are formed. (Inverse staggered type) thin film transistor configured to have a short channel effect is suppressed. Therefore, it is possible to prevent the threshold voltage Vth from changing when the sense current is detected.

(Third Embodiment) FIGS. 8 to 11 are sectional views showing steps in a third embodiment.
This embodiment is an embodiment of a method of manufacturing an inverted stagger type thin film transistor according to the invention of claim 2 . First, in this embodiment, for example, a chromium (Cr) film is formed on the insulating substrate 31 made of glass, and the chromium film is processed by using the photolithography technique and the etching technique to form the gate electrode 32. . After that, a gate insulating film 33 made of, for example, SiO ₂ is deposited on the entire surface by using the CVD method. Then, a semiconductor thin film 34 made of intrinsic amorphous silicon is similarly deposited on the gate insulating film 33 by the CVD method. Furthermore, the semiconductor thin film 34
An impurity implantation control thin film 15 made of, for example, silicon nitride is also deposited thereon by the CVD method. Thereafter, the impurity implantation control thin film 35 and the semiconductor thin film 34 are subjected to element isolation processing into islands by using a photolithography technique and an anisotropic etching technique.

After that, as shown in FIG. 8A, a positive type first photoresist 36 is applied to the entire surface, and then exposure light is irradiated from the back surface side of the insulating substrate 31 to perform the first exposure. To do. The first exposure is performed under a condition that is larger than the total exposure amount of normal self-alignment exposure. Specifically, for example, a 1800 W high-pressure mercury lamp is used as a light source, and the exposure energy is set to 900 mJ / cm ² . In addition, in the present embodiment, the first photoresist 16 is a resist using, for example, a phenol resin as an alkali-soluble polymer compound and o-naphthoquinonediazide as a photosensitizer. As a result of the first exposure, as shown in FIG. 8A, the unexposed portion 36 is formed on the first photoresist 36.
A and the exposed portion 36B are formed. The exposed portion 36B has a predetermined distance L1 at the geometrically shaded portion of the gate electrode 32.
Only the advanced shape. Then, when the first photoresist 36 is developed, a pattern as shown in FIG. 8B is formed. Both side edges of the first photoresist 36 in the gate length direction are naturally located inside the both side edges of the gate electrode 32 in the gate length direction by a predetermined distance L1.

Next, as shown in FIG. 9A, the impurity implantation controlling thin film 35 is anisotropically etched using the first photoresist 36 as a mask. As a result, both side edges of the impurity implantation control thin film 35 in the gate length direction are also separated by a predetermined distance L1 from both side edges of the gate electrode 32 in the gate length direction.
It will be located only inside.

After the first photoresist 36 is peeled off, a positive type second photoresist 37 is applied to the entire surface. After that, the second exposure is performed by irradiating the exposure light from the back surface side of the insulating substrate 31. The second exposure is performed under the condition that the total exposure amount is larger than that of the first exposure described above. Specifically, for example, a 1800 W high-pressure mercury lamp is used as a light source,
The exposure energy is 1000 mJ / cm ² . As a result, an unexposed portion 37A and an exposed portion 37B are formed on the second photoresist 37. In this second exposure, since the total exposure amount is larger than that in the first exposure, the photosensitive agent is affected up to the region inside the geometrically shaded portion of the gate electrode 32, and the gate length of the unexposed portion 37A is increased. Both side edges in the direction are located inside the both side edges of the gate electrode 32 by a predetermined distance L2 (L2> L1). Second photoresist 37
When developed, as shown in FIG.
A is the pattern that remains.

Next, as shown in FIG. 10B, a tungsten thin film 38 is deposited on the entire surface by, eg, sputtering so that the film thickness becomes approximately (L2-L1). As a result, the outer surface of the tungsten thin film 38 attached to the side wall of the impurity implantation control thin film 35 coincides with the position of the edge portion of the gate electrode 32 in the gate length direction when seen in the substrate plane. Then, phosphorus (P), which is an n-type impurity, is added to the semiconductor thin film 34.
By using a high-energy ion implanter, the high-impurity concentration region 34A and the low-impurity concentration region 34B are formed. High impurity concentration region 34
A has a high impurity concentration because phosphorus ions that have passed through the tungsten thin film 38 are implanted and most of the ions that have entered the surface of the tungsten thin film 38 are implanted into the semiconductor thin film 34. Then, at the interface between the high impurity concentration region 34A and the tungsten thin film 38,
Ion implantation energy causes a reaction between silicon (Si) and tungsten (W) to form a tungsten silicide layer 39. In addition, the low impurity concentration region 34
B is, in plan view, the outer surface of the tungsten thin film 38 attached to the side wall of the impurity implantation control thin film 35 and the tungsten thin film 38 attached to the side wall of the second photoresist 37.
The semiconductor thin film 34 substantially corresponding to the area between the outer surface of the
Formed inside. Phosphorus ions are implanted into the low impurity concentration region 34B through the impurity implantation control thin film 35 and the tungsten thin film 38 rising along the side wall thereof, so that the number of implanted ions that can reach the semiconductor thin film 34 is small and the impurity concentration is low. In addition, this low impurity concentration region 3
Although the tungsten silicide layer 39A is also formed on the upper surface of 4B, the energy for silicidation is small because the number of implanted ions that reach it is small, and the layer becomes an extremely thin layer. Since the silicide layer on the low impurity concentration region 34B is thin as described above, the characteristics of the thin film transistor are not adversely affected. Furthermore, the phosphorus ions that have entered the second photoresist 37 never reach the semiconductor thin film 37 due to the injection blocking action of the photoresist, and the semiconductor thin film 3
4 remains an intrinsic semiconductor. In this embodiment, the high impurity concentration region 34A to be the source / drain region and the low impurity concentration region 3 to be the LDD region are formed by one ion implantation step.
4B can be collectively formed.

Next, although not shown, the tungsten thin film 38 in the portions to be the source / drain electrodes is covered with photoresist and etched to remove the unreacted tungsten thin film 38 other than the portions to be the source / drain electrodes. , A source / drain electrode 38 as shown in FIG.
A can be formed. After that, when the second photoresist 37 is peeled off, the manufacture of the thin film transistor of this embodiment is completed. In the step of forming the source / drain electrodes 38A, the second photoresist 37 is peeled off after etching the tungsten thin film 38, but etching may be performed after removing the second photoresist 37 using the lift-off method. . The thin film transistor thus formed has the gate electrode 32 and the low impurity concentration region 3
4B and the gate insulating film 33 are overlapped with each other via a gate insulating film 33, which is a so-called gate overlap LDD structure.

In this embodiment, the tungsten thin film 38 is deposited by the sputtering method. However, for example, an adhesion layer such as titanium nitride (TiN) or titanium tungsten (TiW) is deposited as a base by the sputtering method, and then, A blanket tungsten thin film may be formed by performing blanket W-CVD using tungsten hexafluoride (WF6) and hydrogen (H2) as source gases using a cold water type CVD apparatus. In this case, it is possible to form a tungsten film having a uniform film thickness and good step coverage. In this embodiment, the tungsten thin film 38 is used as the source / drain electrode 38A, but after the silicidation, all the tungsten thin film 38 is removed, and then the metal to be the source / drain electrode is deposited and patterned to form the source / drain electrode. May be. Therefore, the source / drain electrodes may be made of metal such as Al.
Although the first to third embodiments have been described above, the present invention is not limited to these, and various design changes associated with the gist of the configuration can be made. For example, in each of the above embodiments, phosphorus was ion-implanted into the semiconductor thin film to manufacture the n-type thin film transistor, but arsenic (As) of the same conductivity type may be ion-implanted. In the case of manufacturing a p-type thin film transistor, boron (B) may be ion-implanted as an impurity. In each of the above embodiments, chromium (C) is used to form the silicide layer.
Although r) and tungsten (W) are used, molybdenum, titanium, tantalum, nickel, palladium, or the like may be used instead. Further, although amorphous silicon is used as the semiconductor layer in each of the above embodiments, polysilicon may be applied. Furthermore, the photoresist can be variously changed according to the conditions of the exposure means and the like.

As is apparent from the above description, according to the present invention, the source / drain region and the low impurity concentration region serving as the LDD region can be simultaneously formed in one ion implantation step. . Further, according to the present invention, it is not necessary to use an ion implantation mask, or to reduce the number of times of using the ion implantation mask, there is an effect that it is possible to simplify the manufacturing process of a thin film transistor having an LDD structure . In particular, according to the first aspect of the invention, the pattern width can be arbitrarily set only by changing the exposure condition, so that the positional deviation of the pattern does not occur, and the element is miniaturized or the substrate is enlarged. If it does, it will be advantageous. Further, according to the invention of claim 2 ,
The ion implantation has an effect that a silicide layer functioning as an ohmic contact layer can be simultaneously formed.

[Brief description of drawings]

1A and 1B are process cross-sectional views showing a manufacturing process of a first embodiment of the present invention.

2A and 2B are process cross-sectional views showing the manufacturing process of Embodiment 1 of the present invention.

3A to 3C are process cross-sectional views showing the manufacturing process of Embodiment 1 of the present invention.

4A and 4B are process cross-sectional views showing a manufacturing process of a second embodiment of the present invention.

5A and 5B are process cross-sectional views showing a manufacturing process according to a second embodiment of the present invention.

6A and 6B are process cross-sectional views showing a manufacturing process of a second embodiment of the present invention.

FIG. 7 is a cross-sectional view of a photo sensor manufactured using Example 2.

8A and 8B are process cross-sectional views showing a manufacturing process of a third embodiment of the present invention.

9A and 9B are process cross-sectional views showing the manufacturing process of the third embodiment of the present invention.

10A and 10B are process sectional views showing a manufacturing process of a third embodiment of the present invention.

FIG. 11 is a process sectional view showing a manufacturing process of a third embodiment of the present invention.

FIG. 12 is a graph showing the relationship between exposure energy and pattern thinning when back surface exposure is performed.

13A and 13B are process cross-sectional views showing a manufacturing process of a conventional thin film transistor.

[Explanation of symbols]

11 Insulating substrate 12 Gate electrode 14 Semiconductor thin film 14A High impurity concentration region 14B Low impurity concentration region 15 Thin film for controlling impurity implantation 16 First photoresist 17 Second photoresist 38 Tungsten thin film 39 Tungsten silicide layer

Claims (3)

(57) [Claims] 1. A step of forming a gate electrode on the surface side of an insulating substrate having a light-transmitting property, and a step of forming a gate insulating film having a light-transmitting property on the gate electrode and the insulating substrate. Forming a light-transmitting semiconductor thin film on the gate insulating film; forming a light-transmitting impurity injection control thin film on the semiconductor thin film; and forming an impurity injection control thin film on the semiconductor thin film. After the first photoresist is applied to the first photoresist, a first exposure is performed so that both side edges of the first photoresist in the gate length direction are positioned outside a predetermined dimension from both side edges of the gate electrode in the gate length direction. Patterning the impurity implantation control thin film in a self-aligned manner with the first photoresist, and positively on the impurity implantation control thin film and the semiconductor thin film. Pattern second photoresist is applied, and second exposure is performed by irradiating light from the back side of the insulating substrate using the gate electrode as a mask, and the second photoresist is patterned in self-alignment with the gate electrode. And a step of implanting impurity ions into the semiconductor thin film using the second photoresist and the impurity implantation control thin film as a mask to form a source / drain region and a low impurity concentration region. And a method for manufacturing a thin film transistor. 2. A step of forming a gate electrode on the front surface side of an insulating substrate having a light-transmitting property, and a step of forming a gate insulating film having a light-transmitting property on the gate electrode and the insulating substrate. Forming a light-transmitting semiconductor thin film on the gate insulating film; forming a light-transmitting impurity injection control thin film on the semiconductor thin film; and forming an impurity injection control thin film on the semiconductor thin film. After coating a positive type first photoresist on the first substrate, a first photoresist is applied from the back side of the insulating substrate.
And exposing the first photoresist so that both side edges of the first photoresist in the gate length direction are located within a predetermined dimension from both side edges of the gate electrode in the gate length direction, and the first photoresist. Patterning the impurity injection control thin film in a self-aligned manner with the above, and applying a positive second photoresist on the impurity injection control thin film and the semiconductor thin film, and using the gate electrode as a mask to form the insulating film. A second exposure is performed from the back surface side of the substrate so that both side edges of the second photoresist in the gate length direction are located inside a predetermined dimension from both side edges of the impurity implantation control thin film in the gate length direction. Patterning, and depositing a metal thin film of a predetermined thickness on the second photoresist, the impurity implantation control thin film, and the semiconductor thin film. And implanting impurity ions into the semiconductor thin film by ion implantation from the top of the metal thin film, and forming source and drain regions and a low impurity concentration region,
A method of manufacturing a thin film transistor, comprising: 3. The metal thin film is selected from chromium, tungsten, molybdenum, titanium, tantalum, nickel and palladium, and silicide is formed at the interface of the semiconductor thin film with the metal thin film by the ion implantation. The method of manufacturing a thin film transistor according to claim 2, wherein