JP3505328B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with a high-performance LSI for achieving sophisticated electronic equipment such as multimedia equipment and portable equipment, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the trend toward higher functionality of electronic devices has tended to become stronger and stronger. Along with this tendency, the characteristics required for LSIs mounted on electronic devices are also becoming more sophisticated.

However, if all the functions required for an LSI are integrated into one chip, there are major problems such as a long development period and an increase in development cost. Therefore, as one means for solving these problems, different types of LSI
There has been proposed a technique of stacking and integrating the semiconductor chips having the formed therein.

Different LSIs will be described below with reference to the drawings.
A conventional semiconductor device will be described in which semiconductor chips having the above are stacked.

FIG. 19 shows a cross-sectional structure of a conventional semiconductor device. As shown in FIG.
The first and second semiconductor chips 12 have a first aluminum electrode 13 formed on the first semiconductor chip 11 and a second aluminum electrode 14 formed on the second semiconductor chip 12 via bumps 15. By being joined together, they are electrically connected. In this case, the first and second aluminum electrodes 13,
The bumps 15 and 14 are metallicly joined together. As the joining structure between the first and second aluminum electrodes 13 and 14 and the bumps 15, the following two structures are known.

The first joining structure is, as shown in FIG.
For example, Ti on the aluminum electrode 22 of the semiconductor chip 21
-Barrier metal 2 made of Pd-Au or TiW-Au
3 is formed, and then Au is deposited on the barrier metal 23 by electrolytic plating to form the bump 24 made of Au.

The second joint structure, as shown in FIG.
The bumps 2 are selectively pre-selected on the substrate 25 by the electrolytic plating method.
4 is formed, and the bumps 24 are attached to the aluminum electrodes 22 of the semiconductor chip 21 by using the heated pressurizing / heating tool 26.
In this method, the bumps 24 are thermally transferred to the aluminum electrodes 22 by applying pressure to the aluminum electrodes 22.

In any of the first and second methods described above, the step of forming the bumps 24 on the aluminum electrodes 22 of the semiconductor chip 21 requires a large number of complicated processes. In addition, in the process of forming the bumps 24 on the aluminum electrodes 22 of the semiconductor chip 21, the non-defective semiconductor chip 21 may become defective, which causes a problem of increasing the manufacturing cost of the semiconductor device as a whole.

Therefore, recently, a method of forming the bumps 24 by electroless plating has been proposed. This electrolytic plating method can be performed by a process as shown in FIG. That is, the aluminum electrode 22 is subjected to light etching using a NaOH solution or a phosphoric acid solution,
After removing the natural oxide film on the surface of the aluminum electrode 22, a zincate treatment is applied to the surface of the aluminum electrode 22 in order to prevent the surface of the aluminum electrode 22 from being oxidized again.
A Zn layer is formed on the surface of the aluminum electrode 22. After that, the semiconductor chip 21 is immersed in an electroless Ni plating solution, and Z
A substitution reaction between n and Ni is caused to deposit Ni on the surface of the aluminum electrode 22. After depositing Ni with a predetermined film thickness, the semiconductor chip 21 is immersed in an electroless plating solution of Au, and the surface of the deposited Ni is thinly plated with Au. According to the method using the electroless plating, the semiconductor chip 2
Simply immersing 1 into the electroless plating solution, the aluminum electrode 22
Since the bumps 24 can be directly and selectively formed on the substrate, there is a great cost merit.

[0010]

However, the conventional semiconductor device has various problems as described below.

First, in a semiconductor device manufacturing process, a semiconductor chip is normally probed before the bump formation process after the diffusion process is completed. At this time, the probe terminal of the prober is made of aluminum. Since it is necessary to contact the electrode, the area of the aluminum electrode cannot be reduced below a predetermined value. Since hundreds to thousands of aluminum electrodes are provided, there is a problem in that miniaturization of a semiconductor chip, and thus a semiconductor device in which semiconductor chips are stacked, is restricted.

Further, when the probe inspection is performed, the metal prober comes into contact with the surface of the aluminum electrode and scribes, so that the surface of the aluminum electrode is damaged. If electroless plating in the subsequent step is performed in this state, Ni will be deposited in a state where the surface shape of the aluminum electrode is reflected as it is, and the final shape of the bump becomes distorted. As a result, the heights of many bumps formed on the semiconductor chip vary, so that when the first semiconductor chip and the second semiconductor chip are stacked, the first aluminum electrode of the first semiconductor chip is stacked. There is a problem that electrical connection may not be established between the second aluminum electrode and the second aluminum electrode of the second semiconductor chip.

Further, when aluminum electrodes having different areas are formed on the semiconductor chip, if, for example, Ni is deposited by electroless plating to form bumps, the bumps formed on the aluminum electrodes having a large area become aluminum electrodes having a small area. The height is higher than that of the formed bump. Therefore, the first
When the semiconductor chip and the second semiconductor chip are stacked, the aluminum electrode having a large area is easily electrically connected to the opposing aluminum electrode, but the aluminum electrode having a small area is electrically connected to the opposing aluminum electrode. There is a problem that it becomes difficult to produce defective products.

In view of the above, the present invention aims at downsizing of a semiconductor device in which a first semiconductor chip and a second semiconductor chip are laminated, and at the same time, the first semiconductor chip and the second semiconductor chip are The purpose is to ensure electrical conduction.

[0015]

In order to achieve the above-mentioned object, the present invention provides a connection electrode for electrically connecting electrodes formed on the first and second semiconductor chips and a probe test. It is formed separately from the inspection electrode used, and the connection electrode has a small area within the range where electrical connection can be made.
The area of the inspection electrode is set so that the probe terminal can contact it.

A semiconductor device according to the present invention is formed on a first semiconductor chip having a first functional element, a second semiconductor chip having a second functional element, and a main surface of the first semiconductor chip. And a first inspection electrode for inspecting the electrical characteristics of the first functional element and an area formed on the main surface of the first semiconductor chip, the area being smaller than that of the first inspection electrode. A first connection electrode that is provided and is electrically connected to the first functional element, and an electrical characteristic of the second functional element that is formed on the main surface of the second semiconductor chip and is inspected. And a second inspection electrode, which is formed on the main surface of the second semiconductor chip, has an area smaller than that of the second inspection electrode, and is electrically connected to the second functional element. Second connecting electrode, the first connecting electrode and the second connecting electrode A bump formed on at least one of the connection electrodes, and the first semiconductor chip and the second semiconductor chip are interposed between the two in a state where their main surfaces face each other. The first functional element and the second functional element are integrated by an insulating resin, and the first connection electrode and the second connection electrode are bonded to each other through the bump. By doing so , they are electrically connected .

According to the semiconductor device of the present invention, the electrode formed on the main surface of the first semiconductor chip is provided with a first inspection electrode for inspecting the electrical characteristics of the first functional element,
The electrode formed on the main surface of the second semiconductor chip is formed separately from the first functional element and the first connection electrode electrically connected to the second functional element. Since the second inspection electrode for inspecting the characteristics and the second connection electrode electrically connected to the second functional element are separately formed, the first and second connection electrodes are formed. Since it is not necessary to contact the probe terminals for probe inspection, scratches do not adhere to the first and second connection electrodes in the probe inspection process.

[0018]

[0019]

[0020]

[0021]

In the method of manufacturing a semiconductor device according to the present invention, a first inspection for inspecting the electrical characteristics of the first functional element is performed on the main surface of the first semiconductor chip having the first functional element. Forming a first connection electrode having an area smaller than that of the test electrode and the first inspection electrode and electrically connected to the first functional element, and having a second functional element The main surface of the second semiconductor chip has a second inspection electrode for inspecting the electrical characteristics of the second functional element, and an area smaller than the second inspection electrode and the second inspection electrode. A step of forming a second connection electrode electrically connected to the functional element, and forming a bump on at least one of the first connection electrode and the second connection electrode. A bump forming step of forming the first connecting electrode and the second connecting electrode; A bonding step of bonding the connection electrode via the bump, wherein the first semiconductor chip and the second
A semiconductor chip, a configuration in which each of the main surface and a integration step of integrating an insulating resin interposed therebetween in a state of facing.

According to the method of manufacturing a semiconductor device according to the present invention
And a first inspection electrode for inspecting the electrical characteristics of the first functional element and the first inspection electrode on the main surface of the first semiconductor chip.
And a first connecting electrode electrically connected to the functional element of the second functional element are formed on the main surface of the second semiconductor chip for inspecting the electrical characteristic of the second functional element. Since the second inspection electrode and the second connection electrode electrically connected to the second functional element are formed, the first and second inspection electrodes are used for probe inspection, It is not necessary to contact the probe terminals with the first and second connection electrodes.

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

DETAILED DESCRIPTION OF THE INVENTION

(First Embodiment) A semiconductor device according to a first embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows a sectional structure of the semiconductor device according to the first embodiment. Although not shown, the first functional element is formed in the first semiconductor chip 110, and A second functional element is formed in the second semiconductor chip 120.

As shown in FIG. 1, the first semiconductor chip 1
On the main surface of 10, the first inspection electrode 111 made of aluminum for inspecting the electrical characteristics of the first functional element is provided.
And a first connection electrode 112 made of aluminum and having an area smaller than that of the first inspection electrode 111 and electrically connected to the first functional element. In addition, a second surface is formed on the main surface of the first semiconductor chip 120.
Second inspection electrode 121 made of aluminum for inspecting the electrical characteristics of the functional element, and has an area smaller than that of the second inspection electrode 121 and is electrically connected to the second functional element. The second connection electrode 122 made of aluminum is formed. In this case, the first connection electrode 112 and the second connection electrode 122 are formed at positions facing each other.

A first bump 113 is formed on the first connection electrode 112, and a second bump 114 is formed on the first inspection electrode 111. First bump 1 on main surface of semiconductor chip 110
A first protective film 115 is formed in a region where 13 and the second bump 114 are not formed. A third bump 123 is formed on the second connection electrode 122, and a fourth bump is formed on the second inspection electrode 121.
Bumps 124 are formed on the main surface of the second semiconductor chip 120, and the second protective film 1 is formed on a region of the main surface of the second semiconductor chip 120 where the third bumps 123 and the fourth bumps 124 are not formed.
25 are formed. In this case, the first, second, third and fourth bumps 113, 114, 123 and 124 each have a three-layer structure including a Zn layer, a Ni layer and an Au layer formed by electroless plating. ing.

The first connection electrode 112 and the first inspection electrode 111 are connected to each other by a first metal wiring (not shown), and the second connection electrode 122 and the second inspection electrode 121 are connected to each other. Are connected by a second metal wiring 126. As a result, the first inspection electrode 111 is electrically connected to the first functional element via the first connection electrode 112, and the second inspection electrode 121 is the second connection electrode. It is electrically connected to the second functional element via 122. The first inspection electrode 111 may be directly connected to the first functional element without the first connection electrode 112, or the second inspection electrode 12 may be connected.
1 may be directly connected to the second functional element without passing through the second connection electrode 122.

The first bump 113 and the third bump 123
By joining and, the first connection electrode 112 and the second connection electrode 122 are electrically connected. In addition, the first semiconductor chip 110 and the second semiconductor chip 1
20 is integrated by an insulating resin 130 interposed between the two with their main surfaces facing each other.

According to the semiconductor device of the first embodiment, the first semiconductor chip 110 is provided with the first connection electrode 112 and the first inspection electrode 111, and the second semiconductor chip 120 is provided. Has the second connection electrode 122 and the second inspection electrode 121,
While the probe terminals are in contact with the first and second inspection electrodes 111 and 121, the first and second connection electrodes 112,
The probe inspection can be performed without contacting the probe terminal with 122. For this reason, it is possible to avoid a situation in which scratches are attached to the first and second connection electrodes 112 and 122 in the probe inspection process, and a good shape is formed on the first and second connection electrodes 112 and 122. It is possible to form the first and third bumps 113 and 123 having a uniform height and having a uniform height, which ensures the bonding between the first bump 113 and the second bump 123.

Further, the first and second inspection electrodes 111, which require a predetermined size for connecting the probe terminals,
The number of 121 can be reduced to the limit required for probe inspection. Also, the first and second connection electrodes 112, 1
The area of 22 can be made small enough to be bonded via the first and third bumps 113 and 123, and the first and second connection electrodes 112 and 122 are small in area, so that there is no restriction on the place where they are arranged. , The first and second semiconductor chips 110 and 120 can be provided in a small area on the main surface. Therefore, it is possible to downsize the first and second semiconductor chips 110 and 120.

Further, since the first, second, third and fourth bumps 113, 114, 123 and 124 are formed by the electroless plating method, the first and second inspection electrodes 111 and 1 are formed.
The first, second, third, and fourth bumps 113, 114, 123, and 124 are selectively formed only by immersing 21 and the first and second connection electrodes 112 and 122 in an electroless plating solution. Therefore, the manufacturing cost can be reduced.

The second semiconductor chip 120 is larger than the first semiconductor chip 110, and the second inspection electrode 121 faces the first semiconductor chip 110 in the peripheral portion of the second semiconductor chip 120. Since it is formed in a non-exposed region, a probe terminal is brought into contact with the second inspection electrode 121, and a semiconductor device in which the first semiconductor chip 110 and the second semiconductor chip 120 are integrated is formed. A probe test can be performed.

The method of manufacturing the semiconductor device according to the first embodiment will be described below with reference to FIGS.

First, after forming the first inspection electrode 111 and the first connection electrode 112 on the main surface of the first semiconductor chip 110 on which the first functional element is formed, as shown in FIG. , A first protective film 115 is deposited on a region of the main surface of the first semiconductor chip 110 where the first bump 113 and the second bump 114 are not formed, and thereafter, the first inspection electrode 111 and the first inspection film 111 are formed. The connection electrode 112 is degreased and light-etched so that the first protective film 115 of the natural oxide film 116 formed on the surfaces of the first inspection electrode 111 and the first connection electrode 112 is removed. Remove exposed parts.

Next, in order to prevent reoxidation of the first inspection electrode 111 and the first connection electrode 112, electroless N 2
As a pretreatment step for i plating, the first inspection electrode 111 is used.
Then, the surface of the first connection electrode 112 and the surface of the first connection electrode 112 are subjected to Zn substitution treatment, and as shown in FIG.
11 and the Zn layer 117 on the surface of the first connection electrode 112.
To form. In the pretreatment process, a Pd layer or a Ni layer may be formed instead of forming the Zn layer 117.

Next, the first inspecting electrode 111 and the first connecting electrode 112 are immersed in an electroless Ni plating solution, and as shown in FIG. 4, the first and second bumps 113 and 114 are formed.
Forming a Ni thickening layer 118 to be the core of.

Next, the first inspection electrode 111 and the first connection electrode 112 are immersed in an electroless Au plating solution, and the Au layer 1 is formed on the surface of the Ni thickening layer 118 as shown in FIG.
19 is formed. Thereby, the Zn layer, the Ni layer and the Au layer are formed.
First and second bumps 113, 1 having a three-layer structure of layers
14 is formed.

Although not shown, the second semiconductor chip 120 on which the second functional element is formed has a second surface on the main surface.
After forming the inspection electrode 121 and the second connection electrode 122, the third electrode on the main surface of the second semiconductor chip 120 is formed.
First protective film 125 is deposited on the regions where the bumps 123 and the fourth bumps 124 are not formed, and then Z is formed on the surfaces of the second inspection electrode 121 and the second connection electrode 122.
Third and fourth bumps 123, 124 made of an n layer, a Ni layer and an Au layer are formed.

Hereinafter, the first and second inspection electrodes 111,
121, first and second connection electrodes 112 and 122, and first to fourth bumps 113, 114, 123, and 124.
The dimensions and the specific manufacturing method will be described.

In the first embodiment, the first and second
The inspection electrodes 111 and 121 have dimensions of 92 × 92 μm,
The pitch is 150 μm, the dimensions of the first and second connection electrodes 112 and 122 are 15 μmφ, and the pitch is 30 μm.
m. In addition, the first and second inspection electrodes 111, 1
21 and the first and second connection electrodes 112, 122
Is formed by a sputtering method, has a thickness of about 1 μm, and is made of Al-1% Si-0.5% Cu.

The first and second protective films 115 and 125 are Si ₃ N ₄ films having a thickness of 1 μm.

First and second inspection electrodes 111 and 121
As the light etching process for the first and second connection electrodes 112 and 122, the first and second inspection electrodes 111 and 121 and the first and second connection electrodes 112 and 122 are treated with a phosphoric acid solution or The surface of each electrode is removed by about 0.1 μm by immersing in a NaOH solution.

First and second inspection electrodes 111 and 121
Also, as the Zn substitution treatment for the first and second connection electrodes 112 and 122, Z having a film thickness of about 50 nm is used.
The n-layer 117 is formed.

As the step of forming the Ni thickening layer 118,
An electroless Ni plating solution containing nickel sulfate as a main component is used and immersed in an electroless Ni plating solution at 90 ° C. for 10 minutes to deposit a Ni thickening layer 118 having a thickness of about 4 μm.

The step of forming the Au layer 119 is carried out by using a cyan-based electroless Au plating solution and immersing it in the electroless Au plating solution at 90 ° C. for 30 minutes to obtain a thickness of 0.1 to 0.1. An Au layer 119 of about 0.3 μm is formed. When a thick Au layer is formed instead of the Au layer 119 having a normal thickness, the surface of the Au layer 119 is plated with Au for thickening. In this case, the Au layer having a thickness of about 2 μm is formed by immersing it in a cyan plating solution at 73 ° C. for about 20 minutes.

The process of stacking and integrating the first semiconductor chip 110 and the second semiconductor chip 120 will be described below.

First, as shown in FIG. 6, with the back surface of the first semiconductor chip 110 held by the pressing tool 132, the first bumps 113 and the second semiconductor chips of the first semiconductor chip 110 are held. 120 third bump 12
Align 3 with.

Next, as shown in FIG. 7, the third bump 1
After the photo-curable insulating resin 130 is applied over the entire surface of 23, the pressure tool 132 is lowered to move the first semiconductor chip 110 to the second semiconductor chip 120 as shown in FIG. By pressing against the first bump 1
13 and the third bump 123 are joined. In this step, when the first semiconductor chip 110 is pressed against the second semiconductor chip 120, the insulating resin 130 is extruded to the periphery from between the first bump 113 and the third bump 123, and between them. Practically does not remain.

Next, as shown in FIG. 9, the insulating resin 130 existing between the first semiconductor chip 110 and the second semiconductor chip 120 is irradiated with ultraviolet rays from the ultraviolet ray irradiation device 133 to be insulated. By curing the resin 130, the first semiconductor chip 110 and the second semiconductor chip 120 are integrated.

Next, as shown in FIG. 10, the pressure tool 1
The semiconductor device according to the first embodiment is obtained by raising 32 to release the pressure applied to the back surface of the first semiconductor chip 110.

(Second Embodiment) The second embodiment of the present invention will be described below.
The semiconductor device according to the embodiment will be described with reference to FIG.

In the second embodiment, the same members as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

A feature of the second embodiment is that the first bump 113 or the third bump 123 has a tip end portion made of a soft metal that absorbs the variation in the gap between the first bump 113 and the second bump 123. The gap adjusting bump 135 is integrally formed. Therefore, even if the gap between the first bump 113 and the third bump 123 varies due to the difference in area of the first or second connection electrode 112, 122, the first bump 113 And the third bump 1
Since it is possible to surely bond 23 to 23, it is possible to reliably connect the first connection electrode 112 and the second connection electrode 122.

The method of manufacturing the semiconductor device according to the second embodiment will be described below with reference to FIGS.

First, similarly to the method of manufacturing the semiconductor device according to the first embodiment, the first inspection electrode 11 is formed on the main surface of the first semiconductor chip 110 on which the first functional element is formed.
After forming the first and first connection electrodes 112, a first protective film 115 is deposited on a region of the main surface of the first semiconductor chip 110 where the first bumps 113 and the second bumps 114 are not formed ( (See FIG. 11). Then, after removing a portion of the natural oxide film formed on the surfaces of the first inspection electrode 111 and the first connection electrode 112 from the first protective film 115, the first inspection electrode 111 is removed. Then, the second bump 114 and the first bump 113 are formed on the first connection electrode 112, respectively.

Next, as shown in FIG. 12, a gap adjusting bump 135 made of a soft metal such as indium or indium-tin alloy is formed on the substrate 136 at a position corresponding to the first bump 113 by electrolytic plating. To form. The gap adjusting bump 135 has a diameter of about 10 to 20 μmφ,
The height is about 5 to 10 μm. After that, the first semiconductor chip 110 is pressed from the back surface thereof with the pressing / heating tool 13
The first bump 113 of the first semiconductor chip 110 and the gap adjusting bump 135 on the substrate 136 are aligned with each other while being held by 7. Then, the pressure / heating tool 137 is lowered to thermally transfer the gap adjusting bumps 135 to the first bumps 113, and then the pressure / heating tool 137 is raised as shown in FIG. In this case, pressurization
The temperature of the heating tool 137 is about 150 ° C. to 250 ° C., and the pressing force is about 1 to 10 g per one first connecting electrode 112. When thermal transfer is performed with such a pressing force, the gap adjusting bumps 135 made of soft metal are deformed, and the tip surface of the gap adjusting bumps 135 thermally transferred to the first bumps 113 is the main surface of the first semiconductor chip 110. The height from is even.

As a method of forming the gap adjusting bumps 135, instead of the thermal transfer method, the tip end portions of the first bumps 113 are dipped in a melt of soft metal to dip the tip end portions of the first bumps 113. Alternatively, the gap adjusting bumps 135 may be integrally formed.

Then, similarly to the method of manufacturing the semiconductor device according to the first embodiment, the second inspection electrode 12 is formed on the main surface of the second semiconductor chip 120 on which the second functional element is formed.
After forming the first and second connection electrodes 122, the second protective film 125 is deposited on the area of the main surface of the second semiconductor chip 120 where the third bump 123 and the fourth bump 124 are not formed ( (See FIG. 11). Then, after removing a portion of the natural oxide film formed on the surfaces of the second inspection electrode 121 and the second connection electrode 122 exposed from the second protective film 125, the second inspection electrode 121 is removed. A fourth bump 124 and a third bump 123 are formed on the second connection electrode 122 and the second connection electrode 122, respectively.

Next, as shown in FIG. 14, with the first semiconductor chip 110 held from the rear surface thereof by the pressing / heating tool 137, the first semiconductor chip 110 is removed from the first semiconductor chip 110.
And the third bump 123 of the second semiconductor chip 120 are aligned with each other.

Next, as shown in FIG. 15, a photo-curable insulating resin 130 is formed over the entire surface of the third bump 123.
After applying, the pressing / heating tool 137 is lowered to press the first semiconductor chip 110 against the second semiconductor chip 120, as shown in FIG.
The bump 113 and the third bump 123 are joined together. The insulating resin 130 is used for the first bump 113 and the third bump 1.
It is pushed out to the periphery from 23 and it does not substantially remain between both.

Next, as shown in FIG. 17, the insulating resin 130 existing between the first semiconductor chip 110 and the second semiconductor chip 120 is irradiated with ultraviolet rays from the ultraviolet ray irradiation device 133 to be insulated. By curing the resin 130, the first semiconductor chip 110 and the second semiconductor chip 120 are integrated.

Next, as shown in FIG. 18, the pressurizing / heating tool 137 is raised to release the pressing force applied to the back surface of the first semiconductor chip 110, and the semiconductor according to the second embodiment. The device is obtained.

Incidentally, in the first and second embodiments,
The second bump 114 is formed on the first inspection electrode 111 and the fourth bump 124 is formed on the second inspection electrode 121.
The second bump 114 and the fourth bump 1 are formed.
24 may not be formed.

In the first and second embodiments, the first bump 113 is formed on the first connection electrode 112, and the third bump 123 is formed on the second connection electrode 122. However, one of the first bump 113 and the third bump 123 may be omitted. In this case, the first connecting electrode 122 and the second connecting electrode 122 are the first bump 113 or the third bump 123.
Are joined through.

[0071]

According to the semiconductor device of the present invention , the first
Since it is not necessary to contact the probe terminal for probe inspection with the second and second connection electrodes, scratches do not adhere to the first and second connection electrodes during the probe inspection process.
Alternatively, it is possible to avoid a situation in which the shape of the bump formed on the second connection electrode becomes distorted or the height of the bump varies, and thus the first connection electrode and the second connection electrode can be prevented. The electrode for use is securely bonded via the bump.

[0072] Also, conventionally, because it was provided with one electrode which also serves as the inspection and connection, but the area of all electrodes was increased enough to be contact probe pin and the
According to the invention , since the electrodes are divided into those for connection and those for inspection,
It is possible to reduce the number of the first and second inspection electrodes having a large area which the probe terminals can contact to the minimum number required for the probe inspection, and to reduce the area of the first and second connection electrodes by the probe terminals. Since they do not come into contact with each other, they can be made small enough to be bonded via bumps, and therefore the size of the first and second semiconductor chips can be made small, so that the semiconductor device in which both are integrated can be downsized. Thus, the present onset
According to bright, it is possible to achieve the stability and reliability as well as miniaturization of a semiconductor device in which a semiconductor chips different LSI are formed are laminated.

[0073]

[0074]

[0075]

[0076]

According to the method of manufacturing a semiconductor device of the present invention , the first inspection electrode and the first connection electrode are formed on the main surface of the first semiconductor chip, and the main surface of the second semiconductor chip is formed. Since the method includes the step of forming the second inspection electrode and the second connection electrode on the first and second inspection electrodes, the first and second inspection electrodes are used for probe inspection, while the first and second connection electrodes are used. Since it is not necessary to contact the probe terminal with
It is possible to avoid a situation where the shape of the bump formed on the first or second connection electrode becomes distorted or the height of the bump varies, and thus the first connection electrode and the second connection electrode can be prevented. It is possible to surely bond the connection electrode with the connection electrode via the bump.

[0078]

[0079]

[0080]

[0081]

[0082]

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a light etching step in the method for manufacturing a semiconductor device according to the first embodiment.

FIG. 3 is a cross-sectional view showing a pretreatment step of electroless Ni plating in the method for manufacturing a semiconductor device according to the first embodiment.

FIG. 4 is a cross-sectional view showing an electroless Ni plating treatment step in the method for manufacturing a semiconductor device according to the first embodiment.

FIG. 5 is a cross-sectional view showing an electroless Au plating treatment step in the method for manufacturing a semiconductor device according to the first embodiment.

FIG. 6 is a cross-sectional view showing a step of aligning bumps with each other in the method of manufacturing a semiconductor device according to the first embodiment.

FIG. 7 is a cross-sectional view showing a step of applying an insulating resin in the method for manufacturing a semiconductor device according to the first embodiment.

FIG. 8 is a cross-sectional view showing a step of joining bumps to each other in the method for manufacturing a semiconductor device according to the first embodiment.

FIG. 9 is a cross-sectional view showing a step of curing an insulating resin in the method of manufacturing the semiconductor device according to the first embodiment.

FIG. 10 is a cross-sectional view showing a pressure release step in the method for manufacturing a semiconductor device according to the first embodiment.

FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a step of aligning the first bump and the gap adjusting bump in the method of manufacturing the semiconductor device according to the second embodiment.

FIG. 13 is a cross-sectional view showing a thermal transfer process of the gap adjusting bump in the method of manufacturing the semiconductor device according to the second embodiment.

FIG. 14 is a cross-sectional view showing a step of aligning the first bump and the gap adjusting bump in the method of manufacturing the semiconductor device according to the second embodiment.

FIG. 15 is a cross-sectional view showing a step of curing an insulating resin in the method for manufacturing a semiconductor device according to the second embodiment.

FIG. 16 is a cross-sectional view showing a step of joining bumps to each other in the method of manufacturing a semiconductor device according to the second embodiment.

FIG. 17 is a cross-sectional view showing a step of curing an insulating resin in the method for manufacturing a semiconductor device according to the second embodiment.

FIG. 18 is a cross-sectional view showing a pressurizing force releasing step in the method for manufacturing a semiconductor device according to the second embodiment.

FIG. 19 is a cross-sectional view of a conventional semiconductor device.

FIG. 20 is a cross-sectional view showing a first bonding structure of an aluminum electrode and a bump in a conventional method for manufacturing a semiconductor device.

FIG. 21 is a cross-sectional view showing a second bonding structure between an aluminum electrode and a bump in a conventional method for manufacturing a semiconductor device.

FIG. 22 is a flow chart showing a step of forming bumps by electroless plating in a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

110 First semiconductor chip 111 First inspection electrode 112 First connection electrode 113 First bump 114 Second bump 115 First protective film 117 Zn layer 118 Ni thickening layer 119 Au layer 120 Second semiconductor chip 121 Second inspection electrode 122 Second Connection Electrode 123 Third bump 124 Fourth bump 125 Second protective film 130 Insulating resin 132 Pressure tool 133 UV irradiation device 135 Gap adjustment bump 136 substrate 137 Pressurizing / heating tool

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Ichiro Yamane               1-1, Saiwaicho, Takatsuki City, Osaka Prefecture Matsushita Electronics               Business                (56) References JP-A-59-117252 (JP, A)                 JP-A-5-206383 (JP, A)                 JP 4-169790 (JP, A)                 JP-A-7-169790 (JP, A)                 JP-A-6-232136 (JP, A)                 JP-A-4-234126 (JP, A)                 JP-A-3-84929 (JP, A)

Claims (2)

(57) [Claims] 1. A first semiconductor chip having a first functional element, a second semiconductor chip larger than the first semiconductor chip and having a second functional element, and a first semiconductor chip comprising: A first inspection electrode formed on the main surface for inspecting the electrical characteristics of the first functional element; and a first inspection electrode formed on the main surface of the first semiconductor chip. And a first connecting electrode having a small area and electrically connected to the first functional element, and an electrical connection of the second functional element formed on the main surface of the second semiconductor chip. A second inspection electrode for inspecting a static characteristic; and a second functional element formed on the main surface of the second semiconductor chip, having an area smaller than that of the second inspection electrode. A second connection electrode electrically connected to the first connection electrode; A first bump formed on a pole, a second bump formed on the first inspection electrode, a third bump formed on the second connection electrode, the second inspection A fourth bump formed on the electrode for use, wherein the first semiconductor chip and the second semiconductor chip are integrally formed by an insulating resin interposed between the first semiconductor chip and the second semiconductor chip with their main surfaces facing each other. The second inspection electrode is formed in a region that does not face the first semiconductor chip, and the first functional element and the second functional element are the first bumps. And the third bump are joined to electrically connect to each other, and the first bump, the second bump, and the third bump are connected.
And the fourth bump are formed by electroless plating.
Semiconductor device characterized by being 2. A first inspection electrode for inspecting the electrical characteristics of the first functional element on the main surface of a first semiconductor chip having the first functional element, and the first inspection electrode. Forming a first connection electrode having an area smaller than that of the electrode and electrically connected to the first functional element;
A second inspection electrode for inspecting electrical characteristics of the second functional element, which is larger than the first semiconductor chip and is provided on a main surface of a second semiconductor chip having a second functional element, and An electrode forming step of forming a second connecting electrode having an area smaller than that of the second inspection electrode and electrically connected to the second functional element ; A first bump is formed on the first connection electrode, a second bump is formed on the first inspection electrode, a third bump is formed on the second connection electrode, and a second bump is formed on the second connection electrode. A bump forming step of forming a fourth bump on the inspection electrode, a joining step of joining the first bump and the third bump, and the first semiconductor chip and the second semiconductor chip. So that the second inspection electrode faces the first semiconductor chip. No method of manufacturing a semiconductor device, each of the main surfaces, characterized in that and a unifying step of integrating an insulating resin interposed therebetween in a state of facing.