JP2830734B2 - Wiring board and its manufacturing method - Google Patents
Wiring board and its manufacturing methodInfo
- Publication number
- JP2830734B2 JP2830734B2 JP6578594A JP6578594A JP2830734B2 JP 2830734 B2 JP2830734 B2 JP 2830734B2 JP 6578594 A JP6578594 A JP 6578594A JP 6578594 A JP6578594 A JP 6578594A JP 2830734 B2 JP2830734 B2 JP 2830734B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- fine powder
- plating
- plating layer
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
【0001】[0001]
【産業上の利用分野】本発明は、基板上に半導体素子を
樹脂製接着剤で接着した配線基板とその製造方法に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board in which a semiconductor element is bonded on a board with a resin adhesive, and a method of manufacturing the same.
【0002】[0002]
【従来の技術】図3において1はガラス基板で2、3、
10、11は電極を構成する金属層でそれぞれCr、C
u、Ni、Auよりなる。12は半導体IC、13は半
導体ICのAlからなる配線、14は半導体IC12に
Auによって形成されたバンプである。15および16
は紫外線硬化樹脂である。2. Description of the Related Art In FIG.
Reference numerals 10 and 11 denote metal layers constituting the electrodes, respectively Cr and C
u, Ni, and Au. 12 denotes a semiconductor IC, 13 denotes a wiring made of Al of the semiconductor IC, and 14 denotes a bump formed on the semiconductor IC 12 by Au. 15 and 16
Is an ultraviolet curable resin.
【0003】上記構成において半導体IC12の実装は
次のようにして行われる。先ずガラス基板1上に紫外線
硬化樹脂15を塗布し、次に半導体IC12表面の配線
13上に形成されたバンプ14とガラス基板1上のAu
11/Ni10/Cu3/Cr2によって構成された電
極とを位置合わせし、半導体IC12をガラス基板1に
押しつけるように加圧しながら紫外線を照射することに
よって、半導体IC12とガラス基板1との間の紫外線
硬化樹脂15を硬化する。このとき、硬化によって紫外
線硬化樹脂15は収縮する。この収縮力によって半導体
IC12はガラス基板1に常時押しつけられる。これに
よってバンプ14とガラス基板1の電極とが圧接され、
電気的に接続される。In the above configuration, the mounting of the semiconductor IC 12 is performed as follows. First, an ultraviolet curable resin 15 is applied on the glass substrate 1, and then the bump 14 formed on the wiring 13 on the surface of the semiconductor IC 12 and the Au on the glass substrate 1
11 / Ni10 / Cu3 / Cr2 is aligned with the electrode and irradiated with ultraviolet light while pressing the semiconductor IC 12 against the glass substrate 1 to cure the ultraviolet light between the semiconductor IC 12 and the glass substrate 1. The resin 15 is cured. At this time, the ultraviolet curing resin 15 contracts due to the curing. The semiconductor IC 12 is constantly pressed against the glass substrate 1 by this contraction force. As a result, the bump 14 and the electrode of the glass substrate 1 are pressed against each other,
Electrically connected.
【0004】[0004]
【発明が解決しようとする課題】上記従来の構成では、
ガラス基板1上の電極表面は、ガラス基板1の表面の良
好な平面度に影響されて鏡面になる。このため、紫外線
硬化樹脂15の硬化作業前に、この鏡面となった電極上
で半導体IC12のバンプ14に滑りが生じると、半導
体IC12のバンプ14とガラス基板1の電極との間に
形成される微小な隙間に紫外線硬化樹脂15が入り込
み、この入り込んだ紫外線硬化樹脂16によってバンプ
14と電極との密着性が悪化して、電気的接続の信頼性
を悪くするという問題点を有していた。In the above-mentioned conventional configuration,
The surface of the electrode on the glass substrate 1 becomes a mirror surface due to the good flatness of the surface of the glass substrate 1. Therefore, if the bumps 14 of the semiconductor IC 12 slide on the mirror-finished electrodes before the ultraviolet curing resin 15 is cured, the bumps 14 are formed between the bumps 14 of the semiconductor IC 12 and the electrodes of the glass substrate 1. The ultraviolet curable resin 15 enters into the minute gap, and the adhesiveness between the bump 14 and the electrode is deteriorated by the penetrated ultraviolet curable resin 16, and thus the reliability of the electrical connection is deteriorated.
【0005】本発明は上記従来の問題点を解決するもの
で、電気的接続の信頼性の高い配線基板とその製造方法
を提供するものである。The present invention solves the above-mentioned conventional problems, and provides a wiring board having high reliability of electrical connection and a method of manufacturing the same.
【0006】[0006]
【課題を解決するための手段】上記問題点を解決するた
めに本発明の配線基板は、基板と、前記基板上に積層し
た電極と、前記電極上に積層したメッキ層と、前記基板
上に樹脂製接着剤にて接着されるとともに、前記電極上
に積層した前記メッキ層上にバンプを介して電気的接続
をされた半導体素子とを備え、前記メッキ層は絶縁物か
らなる微粉末を有し、かつ前記微粉末の一部を前記メッ
キ層上に突出させた構成とした。In order to solve the above problems, a wiring board according to the present invention comprises a substrate, an electrode laminated on the substrate, a plating layer laminated on the electrode, together are bonded by a resin adhesive, e Bei a semiconductor element electrically connected via the bumps on the plating layer which is laminated on the electrode, the plating layer or insulator
And a portion of the fine powder protruding above the plating layer.
【0007】また、その製造方法は、基板に電極を薄膜
形成する第1工程と、絶縁物からなる微粉末を混入した
メッキ液に電極を薄膜形成した前記基板を浸し、前記基
板の電極上に微粉末を含んだメッキ層を形成する第2工
程と、メッキ層を形成した前記基板と半導体素子とを前
記メッキ層上にバンプを介することにより電気的に接続
する第3工程と、前記基板と前記半導体素子とを樹脂製
接着剤により接着する第4工程とを有した構成とした。Further, the manufacturing method includes a first step of forming a thin film of an electrode on a substrate, and immersing the substrate having a thin film of an electrode in a plating solution mixed with a fine powder of an insulator, and forming the thin film on the electrode of the substrate. A second step of forming a plating layer containing fine powder, a third step of electrically connecting the substrate on which the plating layer has been formed and the semiconductor element to each other by interposing bumps on the plating layer; And a fourth step of bonding the semiconductor element with a resin adhesive.
【0008】[0008]
【作用】上記構成により、表面の平面度が良好な基板を
用いて、電極を積層し電極表面が基板の表面に影響され
て鏡面になっても、電極上に形成するメッキ層が微粉末
を有し、かつ微粉末の一部がメッキ層上に突出している
ので、メッキ層の表面が粗面化されるとともに、このメ
ッキ層上に突出した微粉末の一部がバンプに食い込むの
で、電極上に形成したメッキ層と半導体素子のバンプと
の接触部における滑りを防止することができる。これに
より、電極と半導体素子のバンプとの間に微小な隙間を
生じることもなく、樹脂の流入もなく、電気的接続を良
好にすることができる。According to the above-mentioned structure, the electrode is laminated on a substrate having good surface flatness, and even if the electrode surface is mirror-finished due to the influence of the substrate surface, the plating layer formed on the electrode removes the fine powder. Since a part of the fine powder protrudes on the plating layer, the surface of the plating layer is roughened, and a part of the fine powder protruding on the plating layer digs into the bumps. It is possible to prevent slippage at a contact portion between the plating layer formed thereon and the bump of the semiconductor element. Thus, a fine gap is not generated between the electrode and the bump of the semiconductor element, and no resin flows, so that the electrical connection can be improved.
【0009】[0009]
(実施例1)以下、本発明の第1の実施例について図面
を参照しながら説明する。Embodiment 1 Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
【0010】図1は、第1の実施例における配線基板の
断面図である。図1に示すように、第1の実施例におけ
る配線基板は、ガラス基板1と、このガラス基板1上に
ガラス基板1側から順にCr層2、Cu層3を積層、薄
膜形成してなる電極16と、この電極16上に電極16
側から順にNi層10、Au層11を積層、薄膜形成し
てなるメッキ層17と、紫外線硬化樹脂15によりガラ
ス基板1と接着されたAl配線13を備えた半導体素子
12とを有している。また、半導体素子12のAl配線
13と電極16とを電気的に接続するように、Al配線
13と電極16上に形成したメッキ層17とを、Al配
線13上のバンプ14を介して電気的接続をしている。
さらに、メッキ層17はアルミナ微粉末9を有し、かつ
アルミナ微粉末9の一部をメッキ層17上に突出させて
いる。このとき、アルミナ微粉末9はメッキ層17中の
Ni層10中に含有され、Au層11を貫通して突出し
た構成である。FIG. 1 is a sectional view of a wiring board according to the first embodiment. As shown in FIG. 1, the wiring substrate according to the first embodiment is an electrode formed by laminating a Cr layer 2 and a Cu layer 3 on the glass substrate 1 in this order from the glass substrate 1 side to form a thin film. 16 and an electrode 16 on the electrode 16
It has a plating layer 17 formed by laminating and thinning a Ni layer 10 and an Au layer 11 in this order from the side, and a semiconductor element 12 having an Al wiring 13 bonded to the glass substrate 1 by an ultraviolet curing resin 15. . Further, the Al wiring 13 and the plating layer 17 formed on the electrode 16 are electrically connected via the bumps 14 on the Al wiring 13 so as to electrically connect the Al wiring 13 and the electrode 16 of the semiconductor element 12. Connecting.
Further, the plating layer 17 has the alumina fine powder 9, and a part of the alumina fine powder 9 is projected on the plating layer 17. At this time, the alumina fine powder 9 is contained in the Ni layer 10 in the plating layer 17 and protrudes through the Au layer 11.
【0011】上記構成について、以下その特性について
説明する。表面の平面度が良好なガラス基板1を用い
て、電極16を薄膜形成する。電極16表面はガラス基
板1の表面に影響されて鏡面になる。しかし、電極16
を形成するメッキ層17がアルミナ微粉末9を有し、か
つアルミナ微粉末9の一部がメッキ層17上に突出して
いるので、電極16表面が粗面化される。The characteristics of the above configuration will be described below. The electrode 16 is formed as a thin film using the glass substrate 1 having a good surface flatness. The surface of the electrode 16 is mirrored by the surface of the glass substrate 1. However, the electrode 16
Since the plating layer 17 forming the fine particles has the alumina fine powder 9 and a part of the alumina fine powder 9 protrudes above the plating layer 17, the surface of the electrode 16 is roughened.
【0012】また、バンプ14と電極16とを圧接して
接触させる際、メッキ層17上に突出したアルミナ微粉
末9の一部がバンプ14に食い込むので、電極16表面
と半導体素子12のバンプ14との接触部における滑り
を防止することができる。これにより、電極16と半導
体素子12のバンプ14との間に微小な隙間を生じるこ
ともなく、紫外線硬化樹脂15の流入もなく、電気的接
続を良好にすることができる。When the bumps 14 and the electrodes 16 are brought into pressure contact with each other, a part of the alumina fine powder 9 projecting on the plating layer 17 bites into the bumps 14. Can be prevented from slipping at the contacting portion. Accordingly, a fine gap is not formed between the electrode 16 and the bump 14 of the semiconductor element 12, and the ultraviolet curable resin 15 does not flow, so that the electrical connection can be improved.
【0013】さらに、薄膜形成してなるメッキ層17は
ガラス基板1側から順にCr層2、Cu層3、Ni層1
0、Au層11を積層してなり、特にNi層10はCu
層3、Au層11との間に積層しているので、反応防止
層として効果がある。Further, the plating layer 17 formed by forming a thin film includes a Cr layer 2, a Cu layer 3, and a Ni layer 1 in this order from the glass substrate 1 side.
0, the Au layer 11 is laminated, and especially the Ni layer 10
Since it is laminated between the layer 3 and the Au layer 11, it is effective as a reaction preventing layer.
【0014】このように本実施例によれば、電極16を
形成するメッキ層17がアルミナ微粉末9を有し、かつ
アルミナ微粉末9の一部がメッキ層上に突出しているの
で、電極16表面が粗面化されるとともに、アルミナ微
粉末9がバンプ14に食い込むので、両者間で滑りは生
じず、その結果として紫外線硬化樹脂15の流入もな
く、電気的接続を良好にすることができる。As described above, according to this embodiment, since the plating layer 17 forming the electrode 16 has the alumina fine powder 9 and a part of the alumina fine powder 9 protrudes above the plating layer, Since the surface is roughened and the alumina fine powder 9 bites into the bumps 14, slippage does not occur between the two, and as a result, there is no inflow of the ultraviolet curable resin 15 and the electrical connection can be improved. .
【0015】なお、薄膜形成してなるメッキ層17はガ
ラス基板1側から順にCr層2、Cu層3、Ni層1
0、Au層11を積層してなるが、Ni層10に変えて
Al、Cu、Cr等の金属でもよい。The plating layer 17 formed by forming a thin film includes a Cr layer 2, a Cu layer 3, and a Ni layer 1 in this order from the glass substrate 1 side.
Although the Au layer 11 is laminated, a metal such as Al, Cu, or Cr may be used instead of the Ni layer 10.
【0016】また、本実施例では微粉末としてアルミナ
を用いたが、Ta205などの金属酸化物やガラス、ポ
リエチレンなどの樹脂、窒化ホウ素等の絶縁物でもよ
い。特に、金属酸化物は紫外線硬化樹脂との接着力がよ
く、絶縁物は樹脂全般との接着力がよい。In this embodiment, alumina is used as the fine powder. However, metal oxide such as Ta205, glass, resin such as polyethylene, and insulator such as boron nitride may be used. In particular, metal oxides have good adhesion to ultraviolet-curable resins, and insulators have good adhesion to resins in general.
【0017】(実施例2)以下、本発明の第2の実施例
について図面を参照しながら説明する。(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
【0018】図2(a)〜(e)は、第1の実施例で述
べた本発明における配線基板の製造工程を示す工程図で
ある。FIGS. 2A to 2E are process diagrams showing the steps of manufacturing the wiring board according to the present invention described in the first embodiment.
【0019】図2(a)に示すように、ガラス基板1に
スパッタや電子ビーム蒸着によってCr層2を0.05
μm、Cu層3を1μm順次薄膜形成して、次に図2
(b)のごとくCr層2およびCu層3をフォトエッチ
ングにより所望のパターンに形成する。As shown in FIG. 2A, a Cr layer 2 is formed on a glass substrate 1 by sputtering or electron beam evaporation to a thickness of 0.05%.
2 μm and a Cu layer 3 are sequentially formed as a 1 μm thin film.
As shown in (b), the Cr layer 2 and the Cu layer 3 are formed in a desired pattern by photoetching.
【0020】次に、図2(c)に示すように、粒径1μ
m程度のアルミナ微粉末9を混入したNiメッキ液8に
電極16を積層したガラス基板1を浸す。その後、前記
Niメッキ液8中に空気、窒素またはアルゴン等のガス
を導入管5から流入して、穴6より噴出させて泡7を形
成する。そして、この泡7によって、Niメッキ液8を
攪拌しながら、ガラス基板1の電極16上にアルミナ微
粉末9を含んだNi層10をメッキ形成する。このと
き、アルミナ微粉末9は1リットルのNiメッキ液8に
対して10〜150g含有させるのが望ましい。また、
アルミナ微粉末9の粒径は0.1μm〜3μm程度が望
ましい。Next, as shown in FIG.
The glass substrate 1 on which the electrodes 16 are laminated is immersed in a Ni plating liquid 8 mixed with about m of alumina fine powder 9. Thereafter, a gas such as air, nitrogen or argon flows into the Ni plating liquid 8 from the introduction pipe 5 and is ejected from the hole 6 to form a bubble 7. Then, the Ni layer 10 containing the alumina fine powder 9 is formed by plating on the electrode 16 of the glass substrate 1 while stirring the Ni plating solution 8 by the bubbles 7. At this time, it is desirable that the alumina fine powder 9 be contained in an amount of 10 to 150 g per liter of the Ni plating solution 8. Also,
The particle size of the alumina fine powder 9 is desirably about 0.1 μm to 3 μm.
【0021】その後、メッキ形成したNi層10上に、
Au層11等の金属を無電解メッキ等によって0.1μ
m程度形成する。このときAu層11の厚さはNi層1
0中に含有するアルミナ微粉末9の一部がメッキ形成し
たAu層11上に突出する程度の厚さである。Then, on the Ni layer 10 formed by plating,
0.1 μm of metal such as Au layer 11 is formed by electroless plating or the like.
m. At this time, the thickness of the Au layer 11 is
The thickness is such that a part of the alumina fine powder 9 contained in the metal layer 0 protrudes on the Au layer 11 formed by plating.
【0022】このようにして、図2(d)に示すよう
に、ガラス基板1上にCr層2及びCu層3からなる電
極16を、この電極16上にアルミナ微粉末9を含有し
たNi層10を、このNi層10上にAu層11をそれ
ぞれ積層し、かつNi層10に含有したアルミナ微粉末
9の一部はAu層11を介して突出させている。In this manner, as shown in FIG. 2D, an electrode 16 composed of the Cr layer 2 and the Cu layer 3 is provided on the glass substrate 1, and a Ni layer containing the alumina fine powder 9 is provided on the electrode 16. The Au layer 11 is laminated on the Ni layer 10, and a part of the alumina fine powder 9 contained in the Ni layer 10 is projected through the Au layer 11.
【0023】この後、図2(e)に示すように、メッキ
層17を形成したガラス基板1と、Al配線13を備え
た半導体素子12のバンプ14とを電気的に接続する。Thereafter, as shown in FIG. 2E, the glass substrate 1 on which the plating layer 17 is formed is electrically connected to the bumps 14 of the semiconductor element 12 having the Al wiring 13.
【0024】そして、ガラス基板1に紫外線硬化樹脂1
5を塗布し、バンプ14と電極16上のメッキ層17と
を位置合わせして、Al配線13を備えた半導体素子1
2をガラス基板1に押しつけるように加圧しながら紫外
線を照射する。これにより、塗布された紫外線硬化樹脂
15は硬化しつつ収縮して、この収縮力によって、半導
体素子12はガラス基板1に常時押しつけられ、ガラス
基板1と半導体素子12とが接着される。Then, the ultraviolet curable resin 1 is applied to the glass substrate 1.
5, the bump 14 and the plating layer 17 on the electrode 16 are aligned, and the semiconductor device 1 having the Al wiring 13 is coated.
Irradiation of ultraviolet rays is performed while pressurizing the glass substrate 2 against the glass substrate 1. As a result, the applied ultraviolet curable resin 15 contracts while curing, and the semiconductor element 12 is constantly pressed against the glass substrate 1 by this contraction force, and the glass substrate 1 and the semiconductor element 12 are bonded.
【0025】上記構成によって、Ni層10に含有した
アルミナ微粉末9の一部がメッキ層17上に突出してい
るので、バンプ14に食い込み、良好な接続を行うこと
のできる配線基板を得ることができる。According to the above configuration, since a part of the alumina fine powder 9 contained in the Ni layer 10 protrudes on the plating layer 17, it is possible to obtain a wiring board that can bite into the bump 14 and make good connection. it can.
【0026】また、アルミナ微粉末9は1リットルのN
iメッキ液8中に10〜150g含有させるのが望まし
い。これは、Niメッキ液8中のアルミナ微粉末9の量
が少ない場合は、アルミナ微粉末9の一部がメッキ層1
7上に突出する割合は少なくなり、メッキ層17とバン
プ14との滑りが生じやすくなるからである。一方、N
iメッキ液8中のアルミナ微粉末9の量が多すぎる場合
は、アルミナ微粉末9の一部がメッキ層17上に突出す
る割合は多くなり、絶縁物であるアルミナによってメッ
キ層17とバンプ14間における接続抵抗が大きくなる
からである。The alumina fine powder 9 contains 1 liter of N
It is desirable that the i-plating liquid 8 contains 10 to 150 g. This is because when the amount of the alumina fine powder 9 in the Ni plating solution 8 is small, a part of the alumina fine powder 9
The reason for this is that the ratio of the protrusions on the upper surface 7 decreases, and the slip between the plating layer 17 and the bumps 14 easily occurs. On the other hand, N
When the amount of the alumina fine powder 9 in the i-plating solution 8 is too large, the proportion of a part of the alumina fine powder 9 protruding on the plating layer 17 increases, and the alumina, which is an insulator, causes the plating layer 17 and the bumps 14 to protrude. This is because the connection resistance between them increases.
【0027】さらに、アルミナ微粉末9の粒径は、0.
1μm〜3μmが望ましい。これは、アルミナ微粉末9
はその粒径が0.1μmより小さい場合、アルミナの活
性度が上がりメッキ液の分解が促進され寿命が極端に短
くなり、3μmより大きい場合、メッキ層17上に突出
するアルミナ微粉末9のサイズが大きくなりすぎ、接続
抵抗が大きくなるからである。Further, the particle size of the alumina fine powder 9 is set to 0.1.
1 μm to 3 μm is desirable. This is alumina fine powder 9
When the particle size is smaller than 0.1 μm, the activity of alumina increases and the decomposition of the plating solution is accelerated, and the life is extremely shortened. When the particle size is larger than 3 μm, the size of the alumina fine powder 9 protruding on the plating layer 17 is reduced. Is too large, and the connection resistance becomes large.
【0028】また、空気や窒素等のガスによる攪拌はN
iメッキ液8中のNiがアルミナに付着することによる
メッキ液の劣化を防止する効果がある。In addition, stirring with a gas such as air or nitrogen is N
This has the effect of preventing the deterioration of the plating solution due to the Ni in the i-plating solution 8 adhering to the alumina.
【0029】なお、本実施例では、電極16を形成する
金属として、Cu/Crを用いたが、Al、Au、N
i、Cu/Ni、Au/Pd/Au等の蒸着プロセスや
スパッタによって形成できる材料であれば、特にその層
数や材料とその組合せについて制約がなく、あるいはそ
れらの厚さについても限定するものではない。In this embodiment, Cu / Cr is used as the metal forming the electrode 16, but Al, Au, N
As long as it is a material that can be formed by a vapor deposition process or sputtering, such as i, Cu / Ni, Au / Pd / Au, there is no particular limitation on the number of layers, the materials and their combinations, or the thicknesses thereof are not limited. Absent.
【0030】このように本実施例によれば、実施例1に
おける配線基板の製造方法を提供できるものである。As described above, according to the present embodiment, it is possible to provide the method for manufacturing the wiring board according to the first embodiment.
【0031】[0031]
【発明の効果】以上のように本発明によれば、表面の平
面度が良好な基板を用いて、電極を積層し電極表面が基
板の表面に影響されて鏡面になっても、電極上に形成す
るメッキ層が微粉末を有し、かつ微粉末の一部がメッキ
層上に突出しているので、メッキ層の表面が粗面化され
るとともに、メッキ層上に突出した微粉末の一部がバン
プに食い込むので、電極上に形成したメッキ層と半導体
素子のバンプとの接触部における滑りを防止することが
できる。これにより、電極と半導体素子との間に微小な
隙間を生じることもなく、樹脂の流入もなく、電気的接
続を良好にすることもできるものである。As described above, according to the present invention, electrodes are laminated using a substrate having a good surface flatness, and even if the electrode surface is mirror-finished due to the influence of the surface of the substrate, it can be formed on the electrodes. Since the plating layer to be formed has fine powder and a part of the fine powder protrudes on the plating layer, the surface of the plating layer is roughened and a part of the fine powder protruding on the plating layer is formed. Penetrates into the bumps, so that it is possible to prevent slippage at the contact portions between the plating layers formed on the electrodes and the bumps of the semiconductor element. Thus, a fine gap is not generated between the electrode and the semiconductor element, no resin flows, and the electrical connection can be improved.
【図1】本発明の配線基板の断面図FIG. 1 is a cross-sectional view of a wiring board of the present invention.
【図2】本発明の配線基板の製造工程を示す工程図FIG. 2 is a process diagram showing a manufacturing process of the wiring board of the present invention.
【図3】従来の配線基板の断面図FIG. 3 is a cross-sectional view of a conventional wiring board.
1 ガラス基板 2 Cr層 3 Cu層 9 アルミナ微粉末 10 Ni層 11 Au層 12 半導体素子 13 Al配線 14 バンプ 15 紫外線硬化樹脂 16 電極 17 メッキ層 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Cr layer 3 Cu layer 9 Alumina fine powder 10 Ni layer 11 Au layer 12 Semiconductor element 13 Al wiring 14 Bump 15 Ultraviolet curing resin 16 Electrode 17 Plating layer
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 21/60 311 H01L 21/92──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/60 311 H01L 21/92
Claims (7)
前記電極上に積層したメッキ層と、前記基板上に樹脂製
接着剤にて接着されるとともに、前記電極上に積層した
前記メッキ層上にバンプを介して電気的接続をされた半
導体素子とを備え、前記メッキ層は絶縁物からなる微粉
末を有し、かつ前記微粉末の一部を前記メッキ層上に突
出させた配線基板。1. A substrate, an electrode laminated on the substrate,
A plating layer laminated on the electrode, and a semiconductor element bonded to the substrate with a resin adhesive and electrically connected via bumps on the plating layer laminated on the electrode. Bei example, the plating layer wiring board which projects a fine powder made of an insulating material, and a portion of powder the pulverized on the plating layer.
配線基板。2. The wiring board according to claim 1, wherein the fine powder is alumina.
をNiからなるメッキ層、上層をAuからなるメッキ層
とした請求項1または請求項2記載の配線基板。3. The wiring board according to claim 1, wherein the plating layer is an upper layer and a lower layer, the lower layer is a Ni plating layer, and the upper layer is a Au plating layer.
物からなる微粉末を混入したメッキ液に電極を積層した
前記基板を浸し、前記基板の電極上に微粉末を含んだメ
ッキ層を形成する第2工程と、前記電極上に形成した前
記メッキ層と半導体素子とを前記メッキ層上にバンプを
介することにより電気的に接続する第3工程と、前記基
板と前記半導体素子とを樹脂製接着剤により接着する第
4工程とを有した配線基板の製造方法。4. A first step of stacking an electrode on the substrate, an insulating
A second step of immersing the substrate on which the electrodes are laminated in a plating solution mixed with a fine powder of an object to form a plating layer containing the fine powder on the electrodes of the substrate; and forming the plating layer on the electrodes. A third step of electrically connecting the semiconductor element to the semiconductor element by interposing a bump on the plating layer; and a fourth step of bonding the substrate and the semiconductor element with a resin adhesive. Production method.
に電極を積層した基板を浸した後、前記メッキ液中にガ
スを流入させて、前記メッキ液を攪拌しながら、前記基
板の電極上に微粉末を含んだメッキ層を形成する工程と
した請求項4記載の配線基板の製造方法。5. The method according to claim 5, further comprising: immersing the substrate on which the electrodes are laminated in a plating solution mixed with fine powder, flowing a gas into the plating solution, and stirring the plating solution while stirring the plating solution. 5. The method according to claim 4, wherein a step of forming a plating layer containing fine powder on the electrode is performed.
メッキ液に混入した微粉末をアルミナとした請求項4ま
たは請求項5記載の配線基板の製造方法。6. The method according to claim 4, wherein the plating solution is a Ni plating solution, and the fine powder mixed in the plating solution is alumina.
なる微粉末の重量を、Niメッキ液1リットルに対して
10〜150gとした請求項6記載の配線基板の製造方
法。7. The method of manufacturing a wiring board according to claim 6, wherein the weight of the fine alumina powder mixed into the Ni plating solution is 10 to 150 g per liter of the Ni plating solution.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6578594A JP2830734B2 (en) | 1994-04-04 | 1994-04-04 | Wiring board and its manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6578594A JP2830734B2 (en) | 1994-04-04 | 1994-04-04 | Wiring board and its manufacturing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07283268A JPH07283268A (en) | 1995-10-27 |
JP2830734B2 true JP2830734B2 (en) | 1998-12-02 |
Family
ID=13297043
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6578594A Expired - Fee Related JP2830734B2 (en) | 1994-04-04 | 1994-04-04 | Wiring board and its manufacturing method |
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Country | Link |
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JP (1) | JP2830734B2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001052317A1 (en) * | 2000-01-14 | 2001-07-19 | Toray Engineering Co., Ltd. | Method and device for chip mounting |
US6815252B2 (en) * | 2000-03-10 | 2004-11-09 | Chippac, Inc. | Method of forming flip chip interconnection structure |
US10388626B2 (en) | 2000-03-10 | 2019-08-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming flipchip interconnect structure |
-
1994
- 1994-04-04 JP JP6578594A patent/JP2830734B2/en not_active Expired - Fee Related
Also Published As
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JPH07283268A (en) | 1995-10-27 |
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