JP3503229B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3503229B2 JP3503229B2 JP31045494A JP31045494A JP3503229B2 JP 3503229 B2 JP3503229 B2 JP 3503229B2 JP 31045494 A JP31045494 A JP 31045494A JP 31045494 A JP31045494 A JP 31045494A JP 3503229 B2 JP3503229 B2 JP 3503229B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- external connection
- connection terminal
- insulating layer
- connection terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は狭ピッチ、多ピン化され
た半導体装置の実装に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to mounting a semiconductor device having a narrow pitch and a large number of pins.
【０００２】[0002]
【従来の技術】高密度化された半導体集積回路（以下チ
ップと称する。）を搭載する半導体装置をプリント配線
板に実装する方法として、外部接続端子が多数本一方向
に出ている半導体装置が用いられて来た。たとえば、ボ
ール・グリッド・アレイ（以下ＢＧＡと称する。）等が
代表的なものである。それは接合部にはんだボールを用
いているものであり、半導体装置１を基板に実装した状
態を図１に断面説明図として概略的に示す。2. Description of the Related Art As a method of mounting a semiconductor device having a highly integrated semiconductor integrated circuit (hereinafter referred to as a chip) on a printed wiring board, a semiconductor device having a large number of external connection terminals in one direction is known. It has been used. For example, a ball grid array (hereinafter referred to as BGA) is typical. It uses solder balls in the joints, and a state in which the semiconductor device 1 is mounted on a substrate is schematically shown in FIG. 1 as a cross-sectional explanatory view.
【０００３】図１によれば、半導体装置１の半導体装置
のパッド４がハンダボール５によりプリント配線板側の
パッド６と電気的に接続されている。According to FIG. 1, a pad 4 of the semiconductor device of the semiconductor device 1 is electrically connected to a pad 6 on the printed wiring board side by a solder ball 5.
【０００４】昨今、このような半導体装置の高密度化、
高機能化といった要求に伴い、チップの入出力端子も年
々増加し、それに従い接続端子数も増加させる必要に迫
られている。In recent years, the density of such semiconductor devices has been increased,
With the demand for higher functionality, the number of chip input / output terminals is increasing year by year, and it is necessary to increase the number of connecting terminals accordingly.
【０００５】そのため、外部接続端子をマトリックス状
に配列をするなどの手段を取っても、ピッチを狭く、ま
た接続端子数の増加による半導体装置の実装上の問題が
各種生じている。Therefore, even if the external connection terminals are arranged in a matrix, the pitch is narrowed and the number of connection terminals increases, which causes various problems in mounting the semiconductor device.
【０００６】[0006]
【発明が解決しようとする課題】前記各種の問題の代表
的なものとして、はんだ量のバラツキによるボールの高
さがばらつき、図２、３に示すように、未はんだ部や隣
接する外部接続端子との接触による不良が発生してしま
う。例えば６００μｍピッチ以下ではほとんど対応でき
ない。As typical ones of the above-mentioned various problems, the heights of the balls vary due to variations in the amount of solder, and as shown in FIGS. Defects will occur due to contact with. For example, a pitch of 600 μm or less cannot be applied.
【０００７】また、外部接続端子が球形で高さがかせげ
ないため、熱膨張率の違いにより応力が発生した場合、
これを緩和できずに外部接続部にクラックが発生してし
まう可能性があり、接続の信頼性が十分とは言えない。
（以下これらをあわせて接触不良と称することとす
る。）Further, since the external connection terminal is spherical and the height cannot be increased, when stress is generated due to a difference in thermal expansion coefficient,
This cannot be alleviated, and a crack may occur in the external connection portion, and the reliability of the connection cannot be said to be sufficient.
(Hereinafter, these are collectively referred to as poor contact.)
【０００８】こういった接触不良の原因は、ピッチが狭
く接続端子数が増加するにつれて、一層顕著となってく
る。The cause of such contact failure becomes more remarkable as the pitch is narrow and the number of connection terminals is increased.
【０００９】本発明は、ピッチが狭く外部接続端子数が
増加しつつも接触不良が無く実装でき、温度差があって
も熱膨張率の違いによるズレを吸収できる信頼性の高い
接続部分とその製造方法を提供することを目的とする。The present invention provides a highly reliable connection portion which can be mounted without a contact failure even if the pitch is narrow and the number of external connection terminals is increased, and can absorb a deviation due to a difference in coefficient of thermal expansion even if there is a temperature difference and its connection. It is intended to provide a manufacturing method.
【００１０】[0010]
【課題を解決するための手段】本発明は、上記課題を解
決するため、外部接続端子が多数本一方向に出ている半
導体装置において、該半導体装置の外部接続面に前記外
部接続端子部の少なくとも１つ以上が融点５００℃以上
の金属によって高さを一定とした中空の円筒状に形成さ
れており、円筒内が導電物質で充ちていることを特徴と
する半導体装置を提供するものである。The present invention SUMMARY OF] In order to solve the above problems, a semiconductor device which the external connection terminals are on the large number of one-way, the outside of the external connection surface of the semiconductor device
At least one of the part connection terminal parts is formed in a hollow cylindrical shape having a constant height by a metal having a melting point of 500 ° C. or more, and the inside of the cylinder is filled with a conductive material. It is provided.
【００１１】[0011]
【００１２】[0012]
【００１３】請求項２では、前記導電物質が、はんだ若
しくは導電ペーストである事を特徴とする請求項１記載
の半導体装置を提供するものである。According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the conductive material is solder or a conductive paste.
【００１４】請求項３では、筒状の部分がＮｉまたはＣ
ｒであることを特徴とする請求項１または２に記載の半
導体装置を提供するものである。In the third aspect , the tubular portion is Ni or C.
4. The semiconductor device according to claim 1 , wherein the semiconductor device is r.
【００１５】請求項４では、円筒の直径が２００〜１０
００μｍ、長さが２００〜２０００μｍである請求項１
〜３何れかに記載の半導体装置を提供するものである。[0015] According to claim 4, the diameter of the cylinder 200 to 10
00Myuemu, claim 1 and a length of 200~2000μm
3 to 3 are provided.
【００１６】請求項５では、円筒状の外部接続端子の外
側に球状のハンダを形成したことを特徴とする請求項１
〜４何れかに記載の半導体装置を提供するものである。[0016] According to claim 5, characterized in that the formation of the solder sphere on the outside of the cylindrical external connection terminal according to claim 1
To 4 are provided.
【００１７】 請求項６では、外部接続端子が多数本一
方向に出ている半導体装置において、前記接続端子部の
少なくとも１つ以上が円筒状であり、該半導体装置のプ
リント配線板上に接続される部分を絶縁層で覆い、絶縁
層の所定の位置にホールを形成しその側面にスパッタ、
蒸着、メッキにより金属を形成しその後絶縁層を剥離す
ることにより筒状の部分を形成することを特徴とする半
導体装置の製造方法を提供するものである。In claim 6 , a large number of external connection terminals are provided.
In the semiconductor device projecting in the direction,
At least one or more is cylindrical, a portion of the semiconductor device connected to the printed wiring board is covered with an insulating layer, a hole is formed at a predetermined position of the insulating layer, and a side surface thereof is sputtered.
A half is characterized by forming a cylindrical portion by forming a metal by vapor deposition and plating and then peeling off the insulating layer.
A method for manufacturing a conductor device is provided.
【００１８】[0018]
【作用】本発明は半導体装置とプリント配線板の接続部
分にＮｉ等の硬質の金属を円筒状に形成して外部接続端
子としたのでハンダなどで接続した場合に、円筒の先端
で止まるため、高さが均一になることを特徴とする。According to the present invention, since a hard metal such as Ni is formed into a cylindrical shape at the connecting portion between the semiconductor device and the printed wiring board to serve as an external connection terminal, it stops at the tip of the cylinder when connected by soldering or the like. The height is uniform.
【００１９】 また、外部接続端子が円筒状のため、そ
れよりハンダがはみ出して隣り合う外部接続端子と接触
する心配がない。Further, since the external connection terminal is cylindrical, there is no concern that the solder will stick out from it and come into contact with the adjacent external connection terminal.
【００２０】さらに、外部接続端子の幅に比べて高さを
十分に高くすることができるので、他の半導体装置のリ
ードやピンに相当する機能を持たせることができる。そ
のため熱膨張の差を外部接続端子の変形によって吸収す
ることができる。Furthermore, since the height can be made sufficiently higher than the width of the external connection terminal, it is possible to provide a function corresponding to the lead or pin of another semiconductor device. Therefore, the difference in thermal expansion can be absorbed by the deformation of the external connection terminal.
【００２１】 外部接続端子の製造にあっては、絶縁層
の所定の位置にホールを形成しその側面にスパッタ、蒸
着、メッキにより金属を形成し、その後絶縁層を剥離す
ることにより円筒状の部分を形成することを特徴とす
る。なお、本発明で述べる外部接続端子が多数本一方向
に出ている半導体装置とは、該半導体装置に形成された
外部接続面上に円筒状の外部接続端子が設けられてなる
ものである。 In manufacturing the external connection terminal, a hole is formed at a predetermined position of the insulating layer, a metal is formed on the side surface by sputtering, vapor deposition, or plating, and then the insulating layer is peeled off to form a cylindrical portion. Is formed. In addition, many external connection terminals described in the present invention are unidirectional.
The semiconductor device shown in is the semiconductor device formed on the semiconductor device.
A cylindrical external connection terminal is provided on the external connection surface.
It is a thing.
【００２２】[0022]
〈実施例１〉半導体装置の導電配線回路はフォトエッチ
ング法により形成した。これは以下のような工程で行っ
た。フォトレジストとして、東京応化製のＰＭＥＲを用
いて、これを塗布及びプリベーク後にＵＶ露光機により
所望のパターンを焼き付けして、専用のアルカリ性現像
液にてパターンを形成する。ポストベークを行った後に
ウエットエッチング法により導電層の不要の部分を除去
した後、レジストを水酸化ナトリウム水溶液で剥膜する
ことによって所望の導電配線回路を形成した。エッチン
グ液には塩化第二鉄を用いた。パターン形成後の半導体
装置の外部接続部分に、厚さが２００〜８００μｍのシ
リコン系のゴム７を貼り合わせる。外部接続端子上にあ
たるシリコンゴム表面にＣＯ2 レーザ（ＹＡＧレーザ等
でも良い。）を用いて、径が３００〜８００μｍのホー
ル８を形成する（図４参照）。これを無電解メッキ槽に
浸漬することでＮｉメッキをホールの側面に２０〜３０
μｍ形成した。メッキの工程においてパラジウムを付け
た後にシリコンゴム表面に低圧水銀ランプを照射するこ
とにより、ここにはメッキが形成されなくなる。その後
シリコンゴムのみを剥膜することにより外部接続面に円
筒状の物を形成した（図５参照）。Example 1 A conductive wiring circuit of a semiconductor device was formed by photoetching. This was performed in the following steps. As a photoresist, PMER manufactured by Tokyo Ohka Co., Ltd. is used, and after coating and prebaking, a desired pattern is baked by a UV exposure machine, and a pattern is formed by a dedicated alkaline developing solution. After performing post-baking, an unnecessary portion of the conductive layer was removed by a wet etching method, and then the resist was stripped with an aqueous sodium hydroxide solution to form a desired conductive wiring circuit. Ferric chloride was used as the etching liquid. Silicon-based rubber 7 having a thickness of 200 to 800 μm is attached to the external connection portion of the semiconductor device after the pattern formation. A hole 8 having a diameter of 300 to 800 μm is formed on the surface of silicon rubber corresponding to the external connection terminal by using a CO 2 laser (YAG laser or the like may be used) (see FIG. 4). By immersing this in an electroless plating bath, Ni plating is applied to the side surface of the hole for 20 to 30
μm formed. By irradiating the surface of the silicon rubber with a low pressure mercury lamp after applying palladium in the plating step, plating is not formed here. Then, only the silicon rubber was peeled off to form a cylindrical object on the external connection surface (see FIG. 5).
【００２３】〈実施例２〉前処理を行った半導体装置の
外部部分にエポキシフィルムをラミネーターにより数枚
重ねて厚さを２００〜８００μｍにする。その後所定の
位置に実施例１同様レーザを用いて径が３００〜８００
μｍのホールを形成した（図４参照）。次いでこれを無
電解メッキ槽に浸漬し、後に電気メッキを行うことでＮ
ｉメッキをホールの側面に２０〜３０μｍ形成した。そ
の後、研磨によりエポキシフィルムの表面のＮｉを除去
し、溶剤（ヒドラジン水和物）を用いてエポキシフィル
ムを剥膜して外部接続部に円筒状の物を形成した。<Embodiment 2> A plurality of epoxy films are laminated by a laminator on the outer portion of the pretreated semiconductor device to have a thickness of 200 to 800 μm. After that, a laser having a diameter of 300 to 800 is used at a predetermined position by using the laser as in the first embodiment.
A μm hole was formed (see FIG. 4). Then, this is immersed in an electroless plating bath, and electroplating is performed later to obtain N
i-plating was formed on the side surface of the hole in an amount of 20 to 30 μm. After that, Ni on the surface of the epoxy film was removed by polishing, and the epoxy film was peeled off using a solvent (hydrazine hydrate) to form a cylindrical object at the external connection portion.
【００２４】尚、何れの場合でも注意すべき点は筒状の
部分の高さを一定にすることである。In any case, a point to be noted is to keep the height of the cylindrical portion constant.
【００２５】また、本発明は上記の実施例に限るもので
はなく、主旨を逸脱いない範囲内で適宜に変更しても良
いことは言うまでもない。例えば、外部接続端子の配列
はマトリックス配列である必要はなく、図６の様なマト
リックスや、その他ランダムパターンと思われる様な配
列等であっても良い。Further, it is needless to say that the present invention is not limited to the above-mentioned embodiment, and may be appropriately modified within a range not departing from the gist. For example, the arrangement of the external connection terminals does not have to be a matrix arrangement, but may be a matrix as shown in FIG.
【００２６】[0026]
【発明の効果】ピッチが狭く接続端子数が増加しつつも
接触不良が無く実装でき、温度差があっても熱膨張率の
違いによるズレを吸収できる信頼性の高い接続部分を形
成することができた。EFFECTS OF THE INVENTION It is possible to form a highly reliable connection part which can be mounted without a contact failure even when the pitch is narrow and the number of connection terminals is increased, and which can absorb a deviation due to a difference in thermal expansion coefficient even if there is a temperature difference. did it.
【００２７】[0027]
【図１】従来の半導体装置をプリント基板上に接続した
状態を示す断面説明図FIG. 1 is an explanatory cross-sectional view showing a state in which a conventional semiconductor device is connected to a printed circuit board.
【図２】従来のＢＧＡで未ハンダを示す断面説明図FIG. 2 is a cross-sectional explanatory view showing a non-soldered state in a conventional BGA.
【図３】従来のＢＧＡで接触不良を示す断面説明図FIG. 3 is an explanatory sectional view showing a contact failure in a conventional BGA.
【図４】本発明の実施例を製造途中の状態を示す斜視図FIG. 4 is a perspective view showing a state in which an embodiment of the present invention is being manufactured.
【図５】本発明の実施例を示す斜視図FIG. 5 is a perspective view showing an embodiment of the present invention.
【図６】本発明の別な外部接続端子の配列例を示す底面
図FIG. 6 is a bottom view showing another arrangement example of the external connection terminals of the present invention.
１…半導体装置 ２…半導体集積回路 ３…半導体装置のベース基板 ４…半導体装置のパッド ５…ハンダボール ６…パッド ７…メッキレジスト（シリコンゴム等） ８…凹部 ９…外部接続端子 1 ... Semiconductor device 2. Semiconductor integrated circuit 3 ... Base substrate of semiconductor device 4 ... Pad of semiconductor device 5 ... Solder ball 6 ... Pad 7 ... Plating resist (silicon rubber, etc.) 8 ... Recess 9 ... External connection terminal
───────────────────────────────────────────────────── フロントページの続き (72)発明者 秋本 聡 東京都台東区台東１丁目５番１号 凸版 印刷株式会社内 (56)参考文献 特開 平７−335780（ＪＰ，Ａ) 特開 平２−178957（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 21/60 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoshi Akimoto 1-5-1, Taito, Taito-ku, Tokyo Toppan Printing Co., Ltd. (56) Reference JP-A-7-335780 (JP, A) JP-A-2 −178957 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23/12 H01L 21/60
Claims (6)
導体装置において、該半導体装置の外部接続面に前記外
部接続端子部の少なくとも１つ以上が融点５００℃以上
の金属によって高さを一定とした中空の円筒状に形成さ
れており、円筒内が導電物質で充ちていることを特徴と
する半導体装置。1. A semiconductor device which the external connection terminals are on the large number of one-way, the outside of the external connection surface of the semiconductor device
A semiconductor device, wherein at least one of the part connection terminal parts is formed of a metal having a melting point of 500 ° C. or more in a hollow cylindrical shape having a constant height, and the inside of the cylinder is filled with a conductive material.
ストである事を特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the conductive material is solder or conductive paste.
特徴とする請求項１または２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the tubular portion is made of Ni or Cr.
が２００〜２０００μｍである請求項１〜３何れかに記
載の半導体装置。4. The semiconductor device according to claim 1, wherein the cylinder has a diameter of 200 to 1000 μm and a length of 200 to 2000 μm.
ダを形成したことを特徴とする請求項１〜４何れかに記
載の半導体装置。5. The semiconductor device according to claim 1, wherein a spherical solder is formed on the outside of the cylindrical external connection terminal.
導体装置において、前記接続端子部の少なくとも１つ以
上が円筒状であり、該半導体装置のプリント配線板上に
接続される部分を絶縁層で覆い、絶縁層の所定の位置に
ホールを形成しその側面にスパッタ、蒸着、メッキによ
り金属を形成しその後絶縁層を剥離することにより筒状
の部分を形成することを特徴とする半導体装置の製造方
法。6. A plurality of external connection terminals protruding in one direction
In a conductor device, at least one of the connection terminal portions
The upper part has a cylindrical shape, a portion of the semiconductor device to be connected to the printed wiring board is covered with an insulating layer, a hole is formed at a predetermined position of the insulating layer, and a metal is formed on the side surface by sputtering, vapor deposition, or plating. After that, the insulating layer is peeled off to form a tubular portion, which is a method for manufacturing a semiconductor device .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31045494A JP3503229B2 (en) | 1994-12-14 | 1994-12-14 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31045494A JP3503229B2 (en) | 1994-12-14 | 1994-12-14 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08167673A JPH08167673A (en) | 1996-06-25 |
| JP3503229B2 true JP3503229B2 (en) | 2004-03-02 |
Family
ID=18005448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31045494A Expired - Fee Related JP3503229B2 (en) | 1994-12-14 | 1994-12-14 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3503229B2 (en) |
-
1994
- 1994-12-14 JP JP31045494A patent/JP3503229B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08167673A (en) | 1996-06-25 |
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