JP3502817B2 - PSK receiver - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a PSK (Phase Shi
ft Keying) receiver, especially suitable for mobile communication AGC (Autom
atic gain control) circuit.

[0002]

2. Description of the Related Art FIG. 2 shows a PS used for mobile communication and the like.
The partial circuit of a K receiver is shown.

In the circuit preceding the circuit shown in the figure,
Processing such as reception of a radio signal, amplification of the reception signal, and down conversion of the reception signal from a radio frequency (RF) to an intermediate frequency (IF) is executed.
The received signal of is input. The quadrature demodulator 10
The input signal is quadrature demodulated and the resulting I (in-phas
e), Q (quadrature phase) The baseband signal of each channel is supplied to the AGC circuit 12 (described later) and LP for removing unnecessary components.
It is supplied to the sampling circuit 16 via F14.

The sampling circuit 16 samples this baseband signal, and the digital baseband signal obtained as a result is passed through a DC offset level correction circuit 18, a frequency correction circuit 20 and a phase correction circuit 22 to a circuit in the subsequent stage. For example, it is supplied to the decoder. The DC offset level correction circuit 18, the frequency correction circuit 20, and the phase correction circuit 22 constitute a circuit that performs error correction on the baseband signal so that a decoder (not shown) can accurately decode the code value from the digital baseband signal. is doing. Since the A / D conversion is performed by the sampling circuit 16 as described above, the circuits after the sampling circuit 16 including the circuits in the subsequent stages (not shown) include a DSP (Digital Sig).
nal Processor) and other devices for digital signal processing.

Errors that may appear in the baseband output signal in the figure include DC offset, frequency error, phase error,
There is a clock error.

First, as an example of the PSK modulation system, O-Q
Assume PSK. The signal points on the phase plane when there are no various errors are the vertices of the square in FIG. 3, that is, the points where the absolute value of the amplitude is a predetermined value and the phase is nπ / 2 + π / 4 (where n is an integer). . The DC offset is a shift of the signal arrangement center point (the intersection point of the square diagonal lines in FIG. 3) with respect to the origin of the phase plane. Here, if the output of the sampling circuit 16 is only noise, those having a positive amplitude and those having a negative amplitude should appear at the same frequency in the output. Further, even when a meaningful signal is received, if the output frequency of the sampling circuit 16 is observed for a sufficiently long period (that is, over a sufficiently large number of samples) and the appearance frequency is examined, it is between the positive amplitude and the negative amplitude. There should be no significant difference in the frequency of appearance. Therefore, the DC offset level correction circuit 18 averages the code SGN (A) of the output A of the sampling circuit 16 over, for example, the past 128 symbols at any time, and if the obtained average value indicates "negative", it indicates "positive". On the "" side, shift to the "negative" side to indicate "positive" D
The C offset level correction is applied to the output of the sampling circuit 16 and output. Note that SGN (•) is a function that takes a value of +1 when the argument is positive and −1 when the argument is negative.

Next, the phase error is the shift of the phase of the actual signal point from the ideal signal point, and is caused by the phase uncertainty in the fading propagation path. In the example shown in FIG. 3, the points B and C have a phase error with respect to the ideal signal point A. The frequency error is a phase error that changes with the passage of time, and is caused by an error in the local oscillation frequency of the receiver with respect to the local oscillation frequency of the transmitter. In the example shown in FIG. 3, if there is a phenomenon in which the signal points gradually change, such as point A → point B → point C → ..., a frequency error appears. The frequency error detection circuit 26 detects the rotation of the signal point or the rotation of the square (the example of FIG. 3) on the phase plane, and the frequency correction circuit 20.
Corrects the baseband signal after DC offset level correction based on the result (frequency error correction). The phase error detection circuit 24 detects the deviation of the signal points on the phase plane or the inclination of the square (example in FIG. 3), and the phase correction circuit 22 corrects the baseband signal after the frequency error correction based on the result. Apply (phase error correction). The output of the phase correction circuit 22 (“baseband output signal” in FIG. 2) is supplied to the decoder.

Further, the clock error is the deviation of the sampling timing by the sampling circuit 16 with respect to the symbol peak of the received signal (corresponding to the signal point in FIG. 3). The clock recovery circuit 28 samples not only the sample values (A _i-1 , A _i ) near the symbol peak, that is, the timing of the eye pattern opening, by sampling the baseband signal at a frequency twice the symbol frequency. A sample value (B _i ) near the zero crossing point of the signal is also obtained. If there is a clock error, as shown in FIG. 4 (a) and (b), the sampling points of the B _i relative to zero-cross point is shifted to the deviation either sampling point A _i-1 and A _i. Paying attention to this deviation, the clock recovery circuit 28
Detects the clock error ET by the calculation of ET = B _i [SGN (A _i ) −SGN (A _i−1 )]. The sign of the clock error ET indicates the direction of deviation. The clock regenerator circuit 28 adjusts the sampling circuit 1 according to the result of the detection so that the absolute value of the clock error ET becomes small.
The sampling timing in 6 is corrected. In addition,
FIG. 4C is a diagram showing a state where there is no zero-cross point because A _i-1 = A _i .

For the various corrections described above, refer to Japanese Patent Application Laid-Open No. 11-346248, if necessary.

The circuit shown in FIG. 2 has an AGC circuit 12. Although the AGC circuit 12 may be placed in a stage before the quadrature demodulator 10, for example, in the IF stage, in this figure, it is placed between the quadrature demodulator 10 and the sampling circuit 16, that is, in an analog baseband circuit. ing. The AGC circuit 12 includes an amplifier for variable gain amplifying the output of the quadrature demodulator 10 and a circuit for changing the gain so that the amplitude variation appearing in the output of the quadrature demodulator 10 is suppressed, and the amplitude variation is smaller. The signal is supplied to the sampling circuit 16 via the LPF 14. Thus AG
One of the reasons for placing the C circuit 12 before the sampling circuit 16 is to enable data to be stably decoded without error regardless of the characteristics of the propagation path and its variations.

First, the propagation path characteristics in wireless transmission are often influenced by weather conditions, geographical conditions, and the like. In addition, particularly when a signal is received on a moving body, the propagation path characteristics change drastically due to the movement of the moving body on which the receiver is mounted. The propagation path characteristic and its change bring about amplitude fluctuation and phase fluctuation in the received signal. If a received signal with a large amplitude variation exceeding the dynamic range of the sampling circuit 16 is supplied to the sampling circuit 16 as it is, an underflow or overflow occurs in the sampling circuit 16 and a part of the signal is damaged, resulting in a decoder. Decryption can be difficult or impossible. To solve this problem, the dynamic range of the sampling circuit 16 should be sufficiently widened, but for that purpose the number of bits of the A / D converter in the sampling circuit 16 must be increased, leading to higher costs. I will leave. Further, if the number of bits is increased, the load of digital signal processing in the circuits of the next stage and thereafter also increases.

Therefore, in order to be able to use an A / D converter having a relatively small number of bits, an AGC circuit 12 is usually provided in a stage preceding the sampling circuit 16 and an amplitude fluctuation in a signal input to the sampling circuit 16 is usually provided. The circuit configuration that suppresses is adopted. Sampling circuit 16
The dynamic range of the sampling circuit 16 may be narrow as long as the amplitude fluctuation in the input signal to the sampling circuit 16 is small. Therefore, the number of bits of the A / D converter constituting the sampling circuit 16 can be small. As a result, it is possible to obtain a receiver that is low in cost, light in processing load, and less likely to cause signal damage in the sampling circuit 16.

[0013]

However, this A
The following problems occur in connection with setting the response speed of the GC circuit. First, from the original purpose of suppressing the amplitude fluctuation in the input to the sampling circuit,
An AGC circuit that sensitively follows the amplitude fluctuation appearing in the received signal and changes its gain, that is, an AGC circuit having a sufficiently high response speed is desirable. However, if the response speed is too high, even a relatively low frequency change due to the data (PSK modulation component) carried by the received signal, that is, the received signal change that should originally be stored should be “removed” by the AGC circuit. It is suppressed as "amplitude fluctuation". This results in a data error at the decoder output. Therefore, when designing the circuit, it is necessary to set the response speed of the AGC circuit not too high or too low, and it has been a burden on the circuit designer to make such a delicate setting. what if,
If the response speed setting by the circuit designer is inappropriate, unstable operation such as signal corruption in the sampling circuit or data error in the decoder output will occur.

The present invention has been made to solve the above problems, and by improving the gain control in the PSK receiver, signal corruption in the sampling circuit and data error in the decoder output are less likely to occur. Therefore, P that operates stably even in a fading environment that causes large amplitude fluctuations and phase fluctuations in the received signal
One of the purposes is to provide an SK receiver.

[0015]

In order to achieve such an object, the PSK receiver according to the present invention is (1) orthogonal recovery.
A sampling circuit for outputting the tone to digital baseband signals samples the analog baseband signal, the dynamic range, the sampling circuit is configured to cover the amplitude variation due to fading, (2) is input to the sampling circuit
Digitally suppresses fluctuations in the amplitude of the baseband signal
The amplitude of the symbol peak obtained from the baseband signal of
Analog that is input to the sampling circuit at a constant become gain
A for amplifying or attenuating the baseband signal of
And GC circuit, off at the output of (3) a sampling circuit
Characterized in that it comprises a second AGC circuit for or attenuate amplifying the output of the amplitude or gain sampling circuit which varies depending on the time average value of the symbol peak output of the sampling circuit in order to suppress the amplitude variation due to Ejingu And Furthermore, the first AGC circuit is
Variable analog baseband signal provided in front of the road
A variable amplification circuit that amplifies, and a sampling circuit
Input level detection to detect amplitude of eclipsed symbol peak
And a circuit for receiving information from the input level detection circuit.
And controlling the variable amplifier circuit.

As described above, the present invention is characterized by the AG provided so as to extend across the sampling circuit.
C circuit (first AGC circuit), AGC circuit (second AGC circuit) provided after the sampling circuit, response speeds of the first and second AGC circuits and dynamic range setting of the sampling circuit, and 2 is each point of the gain control operation based on the symbol peak amplitude in the AGC circuit of No. 2.

The first AGC circuit is an AGC circuit having a relatively low response speed, and among the amplitude fluctuations appearing in the received signal,
It suppresses and compensates for amplitude fluctuations caused by movement of the PSK receiver or the PSK transmitter that is the communication partner. Therefore, the PSK modulation component is not smoothed and lost in the first AGC circuit, but the amplitude fluctuation due to fading remains in the input to the sampling circuit. Since the dynamic range of the sampling circuit is set to cover the amplitude fluctuation associated with fading, and the response speed of the second AGC circuit is set to be relatively high so as to follow the amplitude fluctuation associated with fading, The amplitude fluctuation remaining at the input to the sampling circuit, especially the amplitude fluctuation due to fading, passes through the sampling circuit and becomes a second value.
Appearing during the input to the AGC circuit of 1) and are suppressed and compensated by the second AGC circuit. The second AGC circuit is a kind of circuit that processes a digital received signal,
Therefore, it can be realized as an AGC circuit that changes the gain according to the symbol peak amplitude of a digital received signal or its average value over time (unlike an analog AGC circuit with integration / smoothing), and with such a second AGC circuit. What is detected is a change in the positive or negative symbol peak level itself, and since a PSK modulation component such as a change from a positive symbol peak to a negative symbol peak is not detected, the PSK modulation component is a sampling circuit. Although it is input to the second AGC circuit via the, it is not subject to suppression / compensation in the second AGC circuit, and is supplied to a circuit in a subsequent stage, for example, a decoder.

Therefore, according to the present invention, since the PSK modulation component is supplied to the circuit in the subsequent stage without being smoothed, it is possible to expect a more reliable and stable operation than the conventional one. Further, a relatively low-speed amplitude fluctuation, for example, an amplitude fluctuation due to the movement of the transmitter or the receiver can be suppressed by the first AGC circuit, and a relatively high-speed amplitude fluctuation, for example, an amplitude fluctuation due to fading can be suppressed by the second AGC circuit. Therefore, also in that respect, more reliable and stable operation can be expected than in the past. The response speeds of the first and second AGC circuits may be set in relation to amplitude fluctuations due to movement of the transmitter or receiver and amplitude fluctuations due to fading, which have significantly different speeds from each other. Is not necessary. As a result, it is possible to obtain a PSK receiver that operates more stably than before under a fading environment that causes large amplitude fluctuations and phase fluctuations in a received signal at a relatively low cost.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. The same or corresponding components as those of the conventional technique shown in FIG. 2 are designated by the same reference numerals, and a duplicate description will be omitted.

FIG. 1 shows a PSK according to an embodiment of the present invention.
3 shows a receiver, in particular a part corresponding to the part shown in FIG.
As is clear from this figure, one of the features of the present embodiment is that instead of the conventional AGC circuit 12, a variable amplifier circuit 12A is provided between the quadrature demodulator 10 and the LPF 14, and a DC offset level correction circuit. An input level detection circuit 12B is provided between the frequency correction circuit 18 and the frequency correction circuit 20,
The variable amplifier circuit 12A and the input level detection circuit 12
This is because B is the first AGC circuit. Another one of the features of this embodiment is that the second AGC circuit 30 is provided between the input level detection circuit 12B and the frequency correction circuit 20 as is also apparent from this figure.
The remaining characteristic points of this embodiment are the operation contents and settings of these two types of AGC circuit and sampling circuit 16.

For example, assume that the received signal is subject to Rayleigh fading. When this type of fading is occurring, the received signal power has a probability of 99.9% of -30.
It exists in the range of -10 dB. The average received signal power is set to 0 dB here. In the present embodiment, the number of bits of the A / D converter in the sampling circuit 16 is determined so that the dynamic range of the sampling circuit 16 substantially covers this range. Therefore, if
If the amplitude variation in the received signal is only due to Rayleigh fading, and if the amplitude variation is not removed and suppressed in the circuit prior to the sampling circuit 16, the amplitude variation passes through the sampling circuit 16 and becomes a digital received signal. It is supplied as a part to the latter stage.

However, in reality, in addition to fading, there are causes of amplitude fluctuations such as movement of the PSK receiver. If, in addition to the amplitude fluctuation due to fading, the amplitude fluctuation due to the movement of the PSK receiver is included in the input to the sampling circuit 16, a part of the received signal is affected by the latter amplitude fluctuation. It will be out of the dynamic range of 16 and will be damaged. Therefore, in order to allow the amplitude fluctuation due to fading to pass through the sampling circuit 16, the amplitude fluctuation due to the movement of the PSK receiver (or the movement of the PSK transmitter as the communication partner) or the like is suppressed in a stage before the sampling circuit 16. There is a need.

The first AGC circuit composed of the variable amplification circuit 12A and the input level detection circuit 12B is PSK.
The sampling circuit 16 measures the amplitude fluctuation due to the movement of the receiver.
It is a circuit provided to suppress the received signal before input to the. The input level detection circuit 12B detects the amplitude of the received signal from the output of the DC offset level correction circuit 18. Further, the reception level is obtained by averaging the results over a relatively long period of time, for example, for 128 symbols, and the amplitude variation in the reception level remains due to the movement of the PSK receiver or the like (the gain of the variable amplification circuit 12A is reduced). Control error). Then, by changing the gain of the variable amplifier circuit 12A according to the result, the amplitude fluctuation due to the movement of the PSK receiver at the input to the sampling circuit 16 is suppressed. The variable amplifier circuit 12A
1 is provided after the quadrature demodulator 10 in FIG. 1, but may be provided before the quadrature demodulator 10. Since the circuits after the sampling circuit 16 can be realized by a DSP or the like, the detection by the input level detecting circuit 12B can be realized by detecting and averaging the symbol peak level.

Further, the amplitude fluctuation due to fading that has passed through the sampling circuit 16 is passed through the DC offset level correction circuit 18 and the input level detection circuit 12B to the second level.
Is input to the AGC circuit 30 of. The AGC circuit 30 is an AGC circuit whose response speed is higher than that of the first AGC circuit. If the first AGC circuit is a circuit that changes the gain according to the average value of 128 symbols as in the above example, the second AGC circuit 30 changes the gain according to the average value of 8 symbols. . With such a high response speed, amplitude fluctuations that have passed through the first AGC circuit and sampling circuit 16, especially amplitude fluctuations due to fading, can be substantially suppressed. Further, the second AGC circuit 3
Reference numeral 0 is a circuit for handling a digital received signal, which can be realized by using a circuit for detecting a symbol peak level similarly to the input level detecting circuit 12B described above. Therefore, the low frequency fluctuation due to the data, that is, the PSK modulation component is stored and supplied to a decoder (not shown).

As described above, in this embodiment, two kinds of AGC circuits having different roles and different response speeds, circuit configurations, and positions are combined accordingly, and the dynamic range of the sampling circuit 16 is determined accordingly. Therefore, it is difficult to cause signal damage in the sampling circuit 16 and data decoding error in the decoder, and stable reception demodulation can be performed even in a PSK receiver moving in a fading environment. Further, in order to realize this, the circuit designer or the like is not burdened with an excessive burden in setting the response speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main configuration of a PSK receiver according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a main configuration of a PSK receiver according to a conventional technique.

FIG. 3 is a phase plan view showing a signal point arrangement in O-QPSK.

4A to 4C are diagrams showing the principle of detecting a clock error.

[Explanation of symbols]

10 quadrature demodulator, 12A variable amplification circuit, 12B input level detection circuit, 14 LPF, 16 sampling circuit, 30 AGC circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-7-321733 (JP, A) JP-A-8-274558 (JP, A) JP-A-11-331300 (JP, A) JP-A-8- 340268 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 27/00-27/30 H04B ⁷ /24-7/26

Claims (2)

(57) [Claims] 1. A sampling circuit samples the baseband <br/> signal of the quadrature demodulated analog outputs baseband signal of the digital, setting as its dynamic range, which covers the amplitude variation due to fading Sampling circuit and the digital baseband signal to suppress the amplitude fluctuation of the baseband signal input to the sampling circuit.
A first AGC circuit which amplifies or attenuates the analog baseband signal amplitude symbols peaks are input to the sampling circuit with a gain which is a constant which is obtained, <br/> vibration due to fading in the output of the sampling circuit PSK, characterized in that it comprises a second AGC circuit for or attenuate amplifying the output of the amplitude or gain sampling circuit which varies depending on the time average value of the symbol peak output of the sampling circuit in order to suppress the width fluctuation Receiving machine. 2. The PSK receiver according to claim 1.
Te, the first AGC circuit, baseband analog provided before the sampling circuit
A variable amplifier circuit that variably amplifies the signal and a symbol peak that is installed after the sampling circuit.
An input level detection circuit for detecting a width, and the variable amplification according to information from the input level detection circuit.
A PSK receiver characterized by controlling a circuit.