JP7060069B2 - DC component fluctuation suppression device, DC component fluctuation suppression method, program - Google Patents

Description

The present invention relates to a receiving technique, and more particularly to a DC component fluctuation suppressing device, a DC component fluctuation suppressing method, and a program for shortening the time until the output stabilizes even when an unnecessary DC component of a signal suddenly fluctuates .

The direct conversion FM (Frequency Modulation) receiver changes the RF signal to a baseband signal by orthogonal detection, and then amplifies the baseband signal with an amplifier. Since the unnecessary DC component is output by the amplifier, the FM receiver reduces the DC component contained in the baseband signal by the coupling capacitor. Further, the FM receiver FM-detects a baseband signal having a reduced DC component (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 3-16349

In the direct conversion system, for example, a strong disturbing wave is distorted to generate an unnecessary DC component in the baseband signal, which is superimposed on the baseband signal of the desired wave to deteriorate the demodulated signal. When an interfering wave appears or stops, unnecessary DC components fluctuate rapidly. When the DC (Direct Current) offset is reduced by the coupling capacitor, if an unnecessary direct current component fluctuates abruptly, the fluctuation of the direct current component is output from the coupling capacitor, so that it takes a long time to stabilize.

The present invention has been made in view of such a situation, and an object of the present invention is to provide a technique for shortening the time until the output stabilizes even when an unnecessary DC component suddenly fluctuates.

In order to solve the above problems, the DC component fluctuation suppressing device according to an embodiment of the present invention includes an orthogonal detector that performs orthogonal detection of a received signal and outputs orthogonal I-phase and Q-phase baseband signals. It includes a high-pass filter that reduces the DC component of the baseband signal and a distribution detector that detects the bias of the distribution of the baseband signal with the reduced DC component. The distribution detector changes the state of the high-pass filter when it detects that the distribution is biased.

Another aspect of the present invention is a method for suppressing fluctuations in DC components . In this method , the received signal is orthogonally detected and the orthogonal I-phase and Q-phase baseband signals are output , the DC component of the baseband signal is reduced by a high-pass filter, and the DC It includes a step of detecting a bias in the distribution of the baseband signal with reduced components, and a step of changing the state of the high-pass filter when it is detected that the distribution is biased.

It should be noted that any combination of the above components and the conversion of the expression of the present invention between methods, devices, systems, recording media, computer programs and the like are also effective as aspects of the present invention.

According to the present invention, it is possible to shorten the time until the output stabilizes even when an unnecessary DC component suddenly fluctuates.

It is a figure which shows the structure of the receiving apparatus which concerns on Example 1. FIG. It is a figure which shows the structure of the distribution detection part of FIG. It is a figure which shows the plurality of quadrants defined in the quadrant determination part of FIG. It is a figure which shows another structure of the distribution detection part of FIG. It is a figure which shows the structure of the 1st HPF of FIG. It is a figure which shows the waveform of the signal input to the 1st HPF of FIG. It is a figure which shows the waveform of the signal output from the 1st HPF when the distribution detection part of FIG. 1 is not determined. It is a figure which shows the waveform of the signal output from the 1st HPF of FIG. It is a figure which shows the structure of the receiving apparatus which concerns on Example 2. FIG. It is a figure which shows the waveform of the signal input to the 1st HPF of FIG. It is a figure which shows the waveform of the signal output from the 1st HPF when the distribution detection part of FIG. 9 is not determined. It is a figure which shows the waveform of the signal output from the 1st HPF of FIG. It is a figure which shows the structure of the receiving apparatus which concerns on Example 3. FIG. It is a figure which shows the waveform of the signal output from the demodulation part of FIG. It is a figure which shows the waveform of the signal output from the delay device of FIG. It is a figure which shows the waveform of the signal output from the mute part of FIG.

(Example 1)
Before explaining the present invention in detail, first, an outline will be given. The first embodiment of the present invention relates to a receiving device that performs direct conversion type orthogonal detection. Since the DC component contained in the orthogonally detected baseband signal causes deterioration of the characteristics, the DC component has been reduced by using the above-mentioned coupling capacitor or the like. However, when the DC component fluctuates abruptly, the coupling capacitor cannot follow it. In order to reduce the deterioration of the characteristics due to the sudden fluctuation of the DC component, the receiving device according to the present embodiment performs the following processing.

The receiving device uses a high-pass filter to reduce the DC components contained in the orthogonally detected I-phase baseband signal and Q-phase baseband signal. Further, the receiving device measures the distribution of the I-phase baseband signal and the Q-phase baseband signal at the orthogonal coordinates, and detects that the DC component fluctuates when the distribution is biased. The receiving device changes the state of the high-pass filter when it detects a fluctuation in the DC component. Specifically, the values of the DC components of the I-phase baseband signal and the Q-phase baseband signal from the occurrence of the fluctuation of the DC component to the detection are derived, and the inside of the high-pass filter is based on the values. Rewrite the data.

FIG. 1 shows the configuration of the receiving device 100 according to the first embodiment. The receiving device 100 includes an antenna 10, an orthogonal detection unit 12, a first ADC (Analog to Digital Converter) 14, a second ADC 16, a first measurement filter 18, a second measurement filter 20, a first HPF (High-Pass Filter) 22, and the like. It includes a second HPF 24, a distribution detection unit 26, a demodulation unit 28, and a local oscillator 30. The orthogonal detection unit 12 includes a first amplification unit 40, a distribution unit 42, a phase shift unit 44, a first mixer 46, a first LPF (Low-Pass Filter) 48, a second amplification unit 50, a second mixer 52, and a second LPF 54. The third amplification unit 56 is included.

The antenna 10 receives an RF (Radio Frequency) signal from a transmitter (not shown). The RF signal is, for example, FM-modulated, but is not limited to this. The antenna 10 outputs the received RF signal (hereinafter, also referred to as “received signal”) to the first amplification unit 40. The first amplification unit 40 is an LNA (Low Noise Amplifier) and amplifies the RF signal from the antenna 10. The first amplification unit 40 outputs the amplified RF signal to the distribution unit 42. The distribution unit 42 separates the RF signal from the first amplification unit 40 into two systems. The distribution unit 42 outputs the separated RF signals to the first mixer 46 and the second mixer 52.

The local oscillator 30 outputs the local oscillation signal to the phase shift unit 44 and the first mixer 46. The phase shift unit 44 phase shifts the local oscillation signal from the local oscillator 30 by 90 degrees. The phase shift unit 44 outputs the phase-shifted local oscillation signal to the second mixer 52. The first mixer 46 generates an I-phase baseband signal (hereinafter referred to as “I signal”) by multiplying the RF signal from the distribution unit 42 and the local oscillation signal from the local oscillator 30. The first mixer 46 outputs an I signal to the first LPF 48. The second mixer 52 generates a Q-phase baseband signal (hereinafter referred to as “Q signal”) by multiplying the RF signal from the distribution unit 42 and the local oscillation signal from the phase shift unit 44. The second mixer 52 outputs a Q signal to the second LPF 54.

The first LPF 48 executes band limitation by removing a signal having a frequency equal to or higher than the cutoff frequency among the I signals from the first mixer 46. The first LPF48 outputs an I signal of a low frequency component (hereinafter, also referred to as “I signal”) to the second amplification unit 50. The second LPF 54 executes band limitation by removing a signal having a frequency equal to or higher than the cutoff frequency among the Q signals from the second mixer 52. The second LPF 54 outputs a low frequency component Q signal (hereinafter, also referred to as “Q signal”) to the third amplification unit 56.

The second amplification unit 50 amplifies the I signal from the first LPF 48, and the third amplification unit 56 amplifies the Q signal from the second LPF 54. The I signal output from the second amplification unit 50 contains an unnecessary DC component, and the Q signal output from the third amplification unit 56 also contains an unnecessary DC component. As described above, the orthogonal detection unit 12 performs orthogonal detection of the RF signal. Further, the orthogonal detection unit 12 is composed of an analog device, for example, one chip.

The first ADC 14 performs analog / digital conversion on the I signal from the second amplification unit 50. The first ADC 14 outputs an I signal converted into a digital signal (hereinafter, also referred to as “I signal”) to the first measurement filter 18 and the first HPF 22. The second ADC 16 performs analog / digital conversion on the Q signal from the third amplification unit 56. The second ADC 16 outputs the Q signal converted into a digital signal (hereinafter, also referred to as “Q signal”) to the second measurement filter 20 and the second HPF 24.

The first measurement filter 18 performs a moving average on the I signal from the first ADC 14. The first measurement filter 18 outputs the moving average value for the I signal to the first HPF 22. Here, the execution of the moving average corresponds to measuring the DC component. The second measurement filter 20 executes a moving average for the Q signal from the second ADC 16. The second measurement filter 20 outputs the moving average value for the Q signal to the second HPF 24.

The first HPF 22 reduces the DC component of the I signal from the first ADC 14, and outputs the I signal (hereinafter, also referred to as “I signal”) with the reduced DC component to the demodulation unit 28. The second HPF 24 reduces the DC component of the Q signal from the second ADC 16 and outputs the Q signal with the reduced DC component (hereinafter, also referred to as “Q signal”) to the demodulation unit 28. The moving average value from the first measurement filter 18 is input to the first HPF 22, and the moving average value from the second measurement filter 20 is input to the second HPF 24. Under normal conditions, these are input. The moving average of is not used. The case of using the moving average value will be described later.

The demodulation unit 28 demodulates the I signal from the first HPF 22 and the Q signal from the second HPF 24. The demodulation unit 28 outputs a demodulation signal which is a demodulation result. The demodulation result in the demodulation unit 28 corresponds to an audio signal.

The distribution detection unit 26 inputs an I signal from the first HPF 22 and a Q signal from the second HPF 24. The distribution detection unit 26 observes the distribution of the I signal and the Q signal on the IQ plane. When the distribution detection unit 26 detects that the distribution is biased, the distribution detection unit 26 outputs the detection signal to the first HPF 22 and the second HPF 24. This detection signal is a signal for changing the state of the first HPF22 and the second HPF24. In the following, two specific examples of the configuration of the distribution detection unit 26 will be described, and then specific examples of the configuration of the first HPF 22 will be described to explain changes in the state between the first HPF 22 and the second HPF 24.

FIG. 2 shows the configuration of the distribution detection unit 26. The distribution detection unit 26 includes a quadrant determination unit 300, a first moving average calculation unit 302, a second moving average calculation unit 304, a third moving average calculation unit 306, a fourth moving average calculation unit 308, and a bias detection unit 310.

The quadrant determination unit 300 defines a plurality of quadrants as shown in FIG. 3 in order to determine the quadrants of the I signal from the first HPF 22 and the Q signal from the second HPF 24. FIG. 3 shows a plurality of quadrants defined by the quadrant determination unit 300. As shown in the figure, four quadrants A1, A2, A3 and A4 are defined. Here, when the value of the input I signal is indicated by "I" and the value of the input Q signal is indicated by "Q", the quadrant determination unit 300 has four quadrants A1 based on the following determination conditions. The classification into A2, A3, and A4 is executed.
A1: I ≧ 0, Q ≧ 0
A2: I <0, Q ≧ 0
A3: I <0, Q <0
A4: I ≧ 0, Q <0
The quadrant determination unit 300 has output terminals corresponding to each of the four quadrants, outputs "1" from the output terminal corresponding to the quadrant including the combination of the I signal and the Q signal, and outputs the other output terminals. Outputs "0" from.

The first moving average calculation unit 302 is connected to the output terminal corresponding to the quadrant "A1" of the quadrant determination unit 300, and the second moving average calculation unit 304 is the output terminal corresponding to the quadrant "A2" of the quadrant determination unit 300. Connected to. Further, the third moving average calculation unit 306 is connected to the output terminal corresponding to the quadrant "A3" of the quadrant determination unit 300, and the fourth moving average calculation unit 308 corresponds to the quadrant "A4" of the quadrant determination unit 300. Connected to the output terminal. The first moving average calculation unit 302 to the fourth moving average calculation unit 308 move average the values input from the quadrant determination unit 300 with a constant number of samples. The first moving average calculation unit 302 to the fourth moving average calculation unit 308 output the moving average value to the bias detection unit 310.

The bias detection unit 310 inputs the moving average values from each of the first moving average calculation unit 302 to the fourth moving average calculation unit 308. If I and Q signals appear in all quadrants within a certain number of samples, all moving averages will be values other than "0", but I and Q signals will appear in any of the quadrants. If not, the moving average value corresponding to the quadrant becomes "0". When any of the four moving average values becomes "0", the bias detection unit 310 outputs a detection signal indicating the detection of the bias of the distribution to the first HPF 22 and the second HPF 24.

FIG. 4 shows another configuration of the distribution detection unit 26. The distribution detection unit 26 includes a quadrant determination unit 500, a power calculation unit 502, a selection unit 504, a first averaging unit 506, a second averaging unit 508, a third averaging unit 510, a fourth averaging unit 512, and a power comparison. Includes part 514. The quadrant determination unit 500 executes the same processing as the quadrant determination unit 300. The quadrant determination unit 500 outputs the determined quadrant to the selection unit 504.

The power calculation unit 502 inputs an I signal from the first HPF 22 and a Q signal from the second HPF 24. The power calculation unit 502 calculates the square value of the I signal, calculates the square value of the Q signal, and calculates the power value by adding them. The power calculation unit 502 outputs the power value to the selection unit 504. The selection unit 504 inputs the power value from the power calculation unit 502, and inputs the quadrant determination result from the quadrant determination unit 500. The selection unit 504 has an output terminal corresponding to each of the four quadrants, and outputs a power value from the output terminal corresponding to the determination result of the quadrant. The power value is not output at the other output terminals.

The first averaging unit 506, the second averaging unit 508, the third averaging unit 510, and the fourth averaging unit 512 calculate the average value of the input power values (hereinafter referred to as "average power value"). That is, the average power value for each quadrant is derived. The power comparison unit 514 inputs the average value of the power values from the first averaging unit 506 to the fourth averaging unit 512. The power comparison unit 514 detects the bias of the distribution by comparing the average power value of each quadrant. For example, if the ratio of the maximum value to the minimum value of the average power value is 10 times or more, the power comparison unit 514 outputs a detection signal indicating the detection of the bias of the distribution to the first HPF 22 and the second HPF 24. It is not limited to "10" times.

FIG. 5 shows the configuration of the first HPF22. The first HPF 22 includes an addition unit 600, a delay unit 602, an addition unit 604, an amplification unit 606, an amplification unit 608, a delay unit 610, a selection unit 612, and an amplification unit 614.

The delay unit 602 delays the I signal from the first ADC 14 by one sample. The I signal delayed by one sample is input to the primary LPF composed of the addition unit 604, the amplification unit 608, and the delay unit 610, and the primary LPF outputs the averaged I signal. Here, assuming that the coefficient of the amplification unit 608 is α, the gain of the primary LPF composed of the addition unit 604, the amplification unit 608, and the delay unit 610 is 1 / (1-α). Gain correction (1-α) is performed on the averaged I signal. The addition unit 600 subtracts the gain-corrected I signal from the I signal from the first ADC 14. The addition unit 600 outputs the addition result as an I signal with a reduced DC component. Here, α is a value of 1 or less, and the closer it is to 1, the steeper the characteristics of the HPF.

In such a configuration, the amplification unit 614 performs gain correction of the moving average value. When the selection unit 612 receives the detection signal from the distribution detection unit 26, the selection unit 612 rewrites the internal value of the delay unit 610 according to the gain-corrected moving average value. As described above, the gain of the primary LPF composed of the addition unit 604, the amplification unit 608, and the delay unit 610 is 1 / (1-α), and the internal value of the delay unit 610 is also 1 / (1 / (1) of the average value. 1-α) times. Therefore, when the gain of the input moving average value is 1, the amplification unit 614 performs 1 / (1-α) times processing so as to have the same gain as the value inside the delay unit 610. The second HPF 24 is configured in the same manner as in FIG. 5, and processes the Q signal instead of the I signal.

In this way, when the distribution detection unit 26 detects that the distribution is biased, the values of the signals in the first HPF 22 and the second HPF 24 are measured by the first measurement filter 18 and the second measurement filter 20. It can be rewritten as the value of the DC component. As a result, the bias of the distribution of the I signal and the Q signal output from the first HPF 22 and the second HPF 24 is reduced, so that the distortion of the signal demodulated by the demodulation unit 28 is also reduced.

FIG. 6 shows the waveform of the signal input to the first HPF 22. Here, as an example, in "T1", the level of the I signal increases due to the fluctuation of the DC component. The level of the I signal up to "T1" is constant, and the level of the I signal from "T1" is also constant.

FIG. 7 shows the waveform of the signal output from the first HPF 22 when the distribution detection unit 26 does not determine. When the first HPF 22 simply operates as an HPF, the fluctuation of the DC component from "T1" is output as it is, and the DC component converges to "0" according to the time constant of the first HPF 22. For the sake of clarity, the processing delay in the first HPF 22 is set to "0".

FIG. 8 shows the waveform of the signal output from the first HPF22. If the I signal is distributed only to positive values as shown in FIG. 7, the distribution detection unit 26 determines after a certain period of time that there is a bias in the signal. After the determination, the internal data of the first HPF 22 is rewritten with the value of the I signal averaged by the first measurement filter 18, so that the signal as shown in FIG. 8 is output. Here, since the processing delay until the determination is made by the distribution detection unit 26 is indicated as "T2-T1", the level of the I signal from "T2" is the same as the level of the I signal up to "T1". Become. The waveform of the signal in the second HPF 24 is also the same as in FIGS. 6 to 8.

This configuration can be realized by the CPU, memory, or other LSI of any computer in terms of hardware, and by programs loaded in memory in terms of software, but here it is realized by cooperation between them. It depicts a functional block that will be used. Therefore, it is understood by those skilled in the art that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof.

According to this embodiment, when it is detected that the distribution of the baseband signal is biased, the state of the high-pass filter is changed. Therefore, even if the DC component fluctuates, the influence of the fluctuation of the DC component is affected. Can be reduced. Further, since the influence of the fluctuation of the DC component is reduced, the time until the output becomes stable can be shortened even when the unnecessary DC component fluctuates suddenly. Further, when it is detected that the distribution of the baseband signal is biased, the value of the signal in the high-pass filter is rewritten to the value of the DC component, so that the DC component after the fluctuation can be cut. Further, since the value of the signal in the high-pass filter is changed so as to cut the DC component after the fluctuation, the fluctuation of the output waveform of the high-pass filter due to the fluctuation of the DC component can be reduced. Further, since the fluctuation of the output waveform of the high-pass filter due to the fluctuation of the DC component is reduced, the distortion of the waveform of the demodulated signal can be reduced.

(Example 2)
Next, Example 2 will be described. The second embodiment of the present invention relates to a direct conversion type receiving device as in the first embodiment. In the second embodiment, it is an object to further shorten the period affected by the fluctuation of the DC component in the signals output from the first HPF and the second HPF. Here, the differences from the past will be mainly explained.

FIG. 9 shows the configuration of the receiving device 100 according to the second embodiment. In the receiving device 100, the configuration of FIG. 1 includes a first delay device 32, a second delay device 34, a first detection HPF 36, and a second detection HPF 38. The first delay device 32 is arranged between the first ADC 14 and the first HPF 22, and the second delay device 34 is arranged between the second ADC 16 and the second HPF 24. Further, the distribution detection unit 26 is connected to the first detection HPF36 without connecting the first HPF22, and is connected to the second detection HPF38 without connecting the second HPF24. Here, the first detection HPF36 and the second detection HPF38 have the same configurations as the first HPF22 and the second HPF24.

The first delay device 32 delays the I signal output from the first ADC 14 for a period corresponding to the processing delay in the first measurement filter 18, and the delayed I signal (hereinafter, also referred to as “I signal”). ) Is output to the first HPF22. The second delay device 34 delays the Q signal output from the second ADC 16 for a period corresponding to the processing delay in the second measurement filter 20, and the delayed Q signal (hereinafter, also referred to as “Q signal”). ) Is output to the second HPF24. The first HPF 22 executes the same processing as before for the I signal from the first delay device 32, and the second HPF 24 executes the same processing as before for the Q signal from the second delay device 34. do.

The first detection HPF 36 reduces the DC component of the I signal from the first ADC 14, and outputs the I signal with the reduced DC component (hereinafter, also referred to as “I signal”) to the distribution detection unit 26. It can be said that the I signal from the first ADC 14 is an I signal avoiding the delay caused by the first delay device 32. The second detection HPF 38 reduces the DC component of the Q signal from the second ADC 16 and outputs the Q signal with the reduced DC component (hereinafter, also referred to as “Q signal”) to the distribution detection unit 26. It can be said that the Q signal from the second ADC 16 is a Q signal that avoids the delay caused by the second delay device 34.

The distribution detection unit 26 executes the same processing as before for the I signal from the first detection HPF 36 and the Q signal from the second detection HPF 38. When the distribution detection unit 26 detects that the distribution is biased, the distribution detection unit 26 rewrites the value of the signal in the first detection HPF 36 to the value of the DC component measured by the first measurement filter 18. Further, when the distribution detection unit 26 detects that the distribution is biased, the distribution detection unit 26 rewrites the value of the signal in the second detection HPF 38 to the value of the DC component measured by the second measurement filter 20.

FIG. 10 shows the waveform of the signal input to the first HPF 22. The I signal delayed by the first delay device 32 is input to the first HPF 22. Here, the delay time in the first delay device 32 is indicated as "T3-T1".

FIG. 11 shows the waveform of the signal output from the first HPF 22 when the distribution detection unit 26 does not determine. When the first HPF 22 simply operates as an HPF, the fluctuation of the DC component from "T3" is output as it is, and the DC component converges to "0" according to the time constant of the first HPF 22.

FIG. 12 shows the waveform of the signal output from the first HPF22. In "T2", the value of the signal in the first HPF 22 is rewritten to the value of the DC component measured by the first measurement filter 18, so that the period affected by the fluctuation of the DC component is further shortened.

According to this embodiment, since the baseband signal is delayed for a period corresponding to the processing delay in the measurement filter and then output to the high-pass filter, the timing of inputting the baseband signal to the high-pass filter can be delayed. .. Further, since the timing of inputting the baseband signal to the high-pass filter is delayed, the period affected by the fluctuation of the DC component can be further shortened.

(Example 3)
Next, Example 3 will be described. Example 3 of the present invention relates to a direct conversion type receiving device as before. The third embodiment also aims to further shorten the period affected by the fluctuation of the DC component. Here, the differences from the past will be mainly explained.

FIG. 13 shows the configuration of the receiving device 100 according to the third embodiment. In the receiving device 100, the delay device 60 and the mute unit 62 are included in the configuration of FIG. The delay device 60 is connected to the demodulation unit 28 and inputs a demodulation signal from the demodulation unit 28. The delay device 60 delays the demodulation signal and outputs the delayed demodulation signal (hereinafter, also referred to as “demodulation signal”) to the mute unit 62. The mute unit 62 inputs the demodulated signal from the delay device 60. When the distribution detection unit 26 detects that the distribution is biased, the mute unit 62 mutes the demodulated signal. That is, the mute unit 62 sets the demodulated signal to “0” for a certain period of time.

FIG. 14 shows the waveform of the signal output from the demodulation unit 28. Here, it is assumed that the waveform of the signal output from the first HPF 22 is the same as that in FIG. For example, when demodulating an FM-modulated signal, if the amplitude change of the I signal and the Q signal is large in the demodulation unit 28, the phase change may also be large. Therefore, in the demodulated signal, pulsed waveforms appear at "T1" and "T2".

FIG. 15 shows the waveform of the signal output from the delay device 60. Due to the delay in the delay device 60, the pulsed waveform appearing in "T1" moves to "T1'", and the pulsed waveform appearing in "T2" moves to "T2'".

FIG. 16 shows the waveform of the signal output from the mute unit 62. In the mute unit 62, the pulsed waveforms appearing in "T1'" and "T2'" are set to "0".

According to this embodiment, a distorted demodulation signal is output until the distribution detection unit detects that the distribution is biased, but since it is delayed and then muted, the distorted demodulation signal is output. Can be prevented. Further, since the output of the distorted demodulated signal is prevented, the period affected by the fluctuation of the DC component can be further shortened.

The present invention has been described above based on the examples. This embodiment is an example, and it is understood by those skilled in the art that various modifications are possible for each of these components and combinations of each processing process, and that such modifications are also within the scope of the present invention. ..

Any combination of Examples 1 to 3 is also valid. According to this modification, the effect of the combination can be obtained.

10 Antenna, 12 Orthogonal detector, 14 1st ADC, 16 2nd ADC, 18 1st measurement filter, 20 2nd measurement filter, 22 1st HPF, 24 2nd HPF, 26 Distribution detection unit, 28 Demodulation unit, 30 Local oscillator , 40 1st amplification unit, 42 distribution unit, 44 phase shift unit, 46 1st mixer, 48 1st LPF, 50 2nd amplification unit, 52 2nd mixer, 54 2nd LPF, 56 3rd amplification unit, 100 receiver.

Claims (3)

An orthogonal detector that detects the received signal orthogonally and outputs the orthogonal I-phase and Q-phase baseband signals.
A measuring filter for measuring the DC component of the baseband signal output from the orthogonal detector, and a measuring filter.
A delay device that delays the baseband signal output from the orthogonal detector for a period corresponding to the processing delay of the measurement filter, and a delay device.
A high-pass filter that reduces the DC component of the baseband signal delayed by the delay machine ,
A high-pass filter for detection that is a baseband signal output from the orthogonal detector and reduces the DC component of the baseband signal that avoids the delay caused by the delayer.
It is equipped with a distribution detection unit that detects the bias of the distribution of the baseband signal with the DC component reduced by the high-pass filter for detection.
When the distribution detector detects that the distribution is biased , the value of the signal in the high-pass filter is rewritten to the value of the DC component measured by the measurement filter, and further, in the detection high-pass filter. A DC component fluctuation suppressing device, characterized in that the value of the signal of is rewritten to the value of the tidal current component measured by the measurement filter . A step in which an orthogonal detector detects a received signal orthogonally and outputs orthogonal I-phase and Q-phase baseband signals.
The step of measuring the DC component of the baseband signal with a measuring filter,
A step of delaying the baseband signal output from the orthogonal detector by the delay device for a period corresponding to the processing delay by the measurement filter.
A step of reducing the DC component of the baseband signal delayed by the delay device with a high-pass filter, and
A step of reducing the DC component of the baseband signal output from the orthogonal detector with a high-pass filter for detection, and
The step of detecting the bias of the distribution of the baseband signal whose DC component is reduced by the high-pass filter for detection by the distribution detection unit, and
When the distribution detection unit detects that the distribution is biased, the value of the signal in the high-pass filter is rewritten to the value of the DC component measured by the measurement filter, and the value in the high-pass filter for detection is rewritten. A step of rewriting the signal value to the value of the tidal current component measured by the measurement filter, and
A method for suppressing fluctuations in DC components, which comprises. A step in which an orthogonal detector detects a received signal orthogonally and outputs orthogonal I-phase and Q-phase baseband signals.
The step of measuring the DC component of the baseband signal with a measuring filter,
A step of delaying the baseband signal output from the orthogonal detector by the delay device for a period corresponding to the processing delay by the measurement filter.
A step of reducing the DC component of the baseband signal delayed by the delay device with a high-pass filter, and
A step of reducing the DC component of the baseband signal output from the orthogonal detector with a high-pass filter for detection, and
The step of detecting the bias of the distribution of the baseband signal whose DC component is reduced by the high-pass filter for detection by the distribution detection unit, and
When the distribution detection unit detects that the distribution is biased, the value of the signal in the high-pass filter is rewritten to the value of the DC component measured by the measurement filter, and the value in the high-pass filter for detection is rewritten. A program for causing a computer to perform a step of rewriting a signal value into a value of a power flow component measured by the measurement filter .

Images