JP3575952B2 - Receiver having DC offset removal function and communication system using the same - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a receiver incorporated in a portable wireless terminal that can be used in a wireless communication system and a wireless communication system using the same, and particularly to a receiver using a direct conversion receiving method and a superheterodyne receiving method. The present invention relates to a small receiver having a function of removing a DC offset (hereinafter, also referred to as a DC offset as necessary), which is a DC component, and a wireless communication system using the same.
[0002]
[Prior art]
With the dramatic development of wireless communication systems in recent years, there has been an increasing demand for wireless terminals to be smaller and less expensive. The direct conversion receiving method has attracted attention as a receiving method that meets this demand. Hereinafter, the configuration and operation principle of the direct conversion receiver will be described with reference to the drawings.
[0003]
FIG. 53 is a diagram showing a basic configuration of a direct conversion receiver. Here, the high-frequency signal received by the antenna 2 of the receiving unit 1 is amplified by the RF amplifier 11 in the analog signal processing circuit 10 and then distributed to two systems. Then, the signals are mixed by the mixers 16 and 17 with a carrier having substantially the same frequency as the received signal supplied from the local oscillator 18 and frequency-converted directly to a base frequency band (baseband). Here, the local oscillator 18 is directly connected to the mixer 16, and is connected to the mixer 17 via a π / 2 phase shifter 19. Therefore, the two signals that have been frequency-converted into baseband have a phase of π / 2 with each other. Unnecessary frequency components are removed from these two systems of baseband signals by low-pass filters (hereinafter abbreviated as LPF-Low-Pass Filters) 22 and 23 each serving to select a channel. After that, the baseband signal is amplified to a desired signal level by the baseband amplifiers 26 and 27, and then A / D converted by an analog / digital (hereinafter abbreviated as A / D) converter 3, and The original data is demodulated by the detection / demodulation means constituting the digital signal processing circuit 40.
[0004]
In this direct conversion receiving method, since a received signal is directly frequency-converted into a baseband, it does not have an intermediate frequency and has no image response in principle. Therefore, there is an advantage that a steep filter for image removal which is indispensable in the superheterodyne system is not required. Also, the LPFs 22 and 23 for channel selection can be made into large-scale integrated circuits (LSIs), and there is an advantage that with the recent dramatic progress of LSIs, a receiver can be made smaller and less expensive. Was.
[0005]
Now, the direct conversion receiving system is suitable for miniaturization and price reduction, but this receiving system has the following problems. This problem will be described with reference to FIG.
[0006]
In FIG. 54 (a), a reference carrier necessary for performing a frequency conversion operation in the mixer 16 (or 17) is supplied from the local oscillator 18. Here, the isolation between the local port 16a and the RF port 16b of the mixer 16 is preferably ideally infinite, but is actually about 30 dB. Therefore, the reference carrier inputted from the local port 16a is leaked to the RF port 16b side, and a part thereof is reflected on the output side of the RF amplifier 11 to become a reflected wave 32, and is inputted again to the mixer 16. Alternatively, after passing through the RF amplifier 11 and leaking to the antenna 2 and being radiated from the antenna 2 to the outside as shown by reference numeral 34, it is reflected by the reflector 36 and re-input from the antenna 2, and the reflected wave 35 Is input to the mixer 16 again. The reflected waves 32 and 35 are mixed with the reference carrier from the local oscillator 18 by the mixer 16 (self-mixing). Here, since the reflected waves 32 and 35 have the same frequency as the reference carrier, they appear as DC output components (hereinafter, DC offset) in the output of the mixer 16 by the self-mixing.
[0007]
FIG. 54B is a diagram showing the state of the DC offset on the frequency axis. That is, in the direct conversion method, the desired wave is originally frequency-converted to a baseband frequency band including a DC component, so that the DC offset component 7 generated by reflection is superimposed on the desired wave 6. It is known that this kind of DC offset is a factor that deteriorates the reception error rate particularly in the case of differential detection, and D (= desired wave) U (= DC offset) for obtaining a desired reception error rate It is necessary to attenuate the DC offset component to such an extent that a component (hereinafter, D / U) ratio of, for example, 20 to 30 dB can be obtained. However, the reference carrier supplied from the local oscillator 18 usually has a level of about 0 dBm, and the reflected waves 32 and 35 that accompany the reference carrier generally have a level higher than the level of the desired wave to be received. Therefore, in order to obtain a desired D / U, a means for removing only the DC offset component on the output side of the mixer 16 is required.
[0008]
As a method conventionally used to remove this DC offset, there is a method of providing AC coupling means (hereinafter, AC couple) 30 and 31 at the outputs of mixers 16 and 17 as shown in FIG. This method is effective when the DC offset is always constant, but has the following problem when the DC offset fluctuates with time. FIG. 55A shows the output of the mixer 16 without an AC couple, and shows a case where the DC offset 104 is superimposed on the desired wave 108. Here, it is assumed that the DC offset 104 in the period 101 changes to the DC offset 105 at time t′103. This corresponds to the case where the operating condition of the circuit of the RF amplifier 11 changes in FIG. 54. For example, the gain of the RF amplifier 11 is switched based on the control signal 33 from the digital signal processing circuit 4 at time t′103. In such a case, a case where the output impedance of the RF amplifier 11 changes and the reflection amount 32 fluctuates can be considered.
[0009]
At this time, the difference 106 between the DC offset 104 before the time t'103 and the DC offset 105 after the time t'103 in FIG. FIG. 55B shows a state in which the output of the mixer 16 is subjected to the AC couple 30 in such a case. That is, a transient response 109 corresponding to the time constant of the AC couple 30 occurs in the period 107 due to the influence of the DC offset difference 106. If a signal to be received arrives before the transient response 109 stops, the desired wave is affected by the DC offset, and the reception characteristics are degraded. That is, even if the AC couple 30 is used, the influence of the DC offset cannot be removed. Further, when the AC couple 30 is used, as shown in FIG. 55 (b), for the desired signal including the DC component, the desired wave of the desired wave is obtained by the frequency characteristic 8 of the AC couple shown in FIG. 54 (b). There was a drawback that a part was deleted, which also deteriorated the reception characteristics.
[0010]
As described above, providing a means for switching the gain of the RF amplifier 11 is a method that is often used to expand the reception dynamic range, particularly in a direct conversion receiver. In addition, this is a method that is usually performed to prevent battery consumption in a small receiver. Such battery saving control of the RF circuit also causes a change in the operating condition of the circuit, so that the same DC offset fluctuation as described above occurs. Therefore, avoiding the influence of the DC offset fluctuation as described above is indispensable for a small receiver, especially for a direct conversion receiver.
[0011]
In addition, as can be seen from the above description, the speed at which the DC offset fluctuates generally corresponds to the speed at which the reflected wave re-input to the mixer 16 fluctuates. This has been described so far mainly on the reflected wave 32 from the RF amplifier 11 in FIG. On the other hand, in FIG. 54 (a), when the light is radiated from the antenna 2 and reflected by the external reflector 36 and re-input to the mixer 16, it corresponds to the speed at which the state of the external reflector 36 changes. As a result, the DC offset amount at the output of the mixer 16 also fluctuates. For example, when the external reflector 36 is a moving vehicle, the DC offset changes at the same speed as the fading pitch generated based on the moving speed.
[0012]
FIG. 56 shows this situation. Here, reference numeral 111 in FIG. 56B denotes a TDMA frame, which periodically receives the reception slots 112 and 116 assigned to the terminal itself. FIG. 56 (a) shows a DC offset, and reference numeral 105 denotes a relatively high-speed DC offset fluctuation occurring in accordance with the fading pitch. On the other hand, 113 and 114 are also DC offsets, which are relatively slow DC offset fluctuations that change due to battery saving or gain switching at time t'103. Therefore, in a direct conversion receiver under a real environment, such a high-speed DC offset fluctuation and a low-speed DC offset fluctuation are mixed. For this reason, it is practically desirable to be able to more flexibly remove the influence of the DC offset fluctuation according to the cause of the DC offset, the difference in the time fluctuation of the DC offset, and the like.
[0013]
Further, the problem related to the DC offset fluctuation described above is that not only the above-mentioned zero IF receiver, but also that the received frequency as shown in FIG. 57 is once converted to the intermediate frequency and then converted to the baseband again. This also occurs in a so-called superheterodyne receiving system. That is, FIG. 57 is a diagram illustrating a basic configuration of a receiver including an analog quadrature demodulation unit. Here, the high-frequency signal received by the receiving unit 1 including the antenna 2 is amplified by the RF amplifier 11. This signal is frequency-converted by the frequency converter 12 to an intermediate frequency.
[0014]
That is, the mixer 14 of the frequency converter 12 multiplies the signal by the reference signal from the local oscillator 13, and the BPF (bandpass filter) 15 removes a wide-range component generated at the time of the multiplication. The received signal frequency-converted to the intermediate frequency by the frequency converter 12 is then distributed to two systems. Then, the mixer 16 and the mixer 17 mix the carrier with a carrier having substantially the same frequency as the intermediate frequency signal supplied from the local oscillator 18 and frequency-convert (orthogonal demodulate) the signal into a baseband frequency band. Here, the local oscillator 18 is connected to the mixer 16 and also to the mixer 17 via the π / 2 phase shifter 19. Therefore, the two systems of signals that have been frequency-converted into baseband have a phase of π / 2 with each other. Unnecessary frequency components other than the desired channel are removed from the two baseband signals by LPFs (low-pass filters) 18 and 19, respectively, which serve to select channels. Thereafter, the signal is amplified to a desired signal level by the baseband amplifiers 26 and 27, A / D converted by the A / D converter 3, and demodulated to the original signal by the detector built in the digital signal processing circuit 4. Is done. Note that a filter for removing an image is required at a stage subsequent to the RF amplifier 11, but this filter will be omitted hereafter.
[0015]
The superheterodyne receiver having the configuration shown in FIG. 57 also operates in the same manner as the above-mentioned zero-IF receiver, and thus has the same problem as the problem associated with the time variation of the DC offset described with reference to FIGS. A point had arisen.
[0016]
Further, in a receiver or a zero-IF receiver including the quadrature demodulation unit, it is necessary to perform gain switching in the radio unit. A conventional example in which this gain switching is performed will be described with reference to FIGS. FIG. 58 shows a conventional example in which radio section gain switching is applied to a zero IF receiver. In FIG. 58, the analog signal processing circuit 10A has the same configuration as the analog signal processing circuit 10 of FIG. 53 except that there are no AC couples 30 and 31. For example, in FIG. 58, the radio section for radio section gain switching refers to the analog signal processing circuit 10A including the RF amplifier 11, the mixers 16, 17, and the amplifiers 26, 27.
[0017]
In FIG. 58, an IQ signal 117 at a stage preceding the detector 36 is extracted and input to an intensity detection / comparison circuit 37 for detecting and comparing the received electric field intensity. The received electric field intensity is calculated by the intensity detection / comparison circuit 37 and compared with the reference voltage 38. As a result, optimal gains to be set for the RF amplifier 11, the mixers 16, 17, and the amplifiers 26, 27 are determined, and the gain control signal 121 is transmitted. That is, the gain control signals 118, 119, and 120 are supplied to the RF amplifier 11, the mixers 16, 17, and the amplifiers 26, 27. The gain switching control is performed by setting the gain of each circuit according to the reception electric field strength, for example, as shown in the table of FIG. In FIG. 59, five receiving modes from mode A to mode E are provided by a combination of the gains of the radio unit, so that a receiving dynamic range of 100 dB can be secured.
[0018]
However, in the case where the radio section gain switching shown in FIG. 58 is performed, the following problem occurs particularly with respect to the DC offset. This problem will be described with reference to FIGS. FIGS. 60 (a) and 61 (a) are diagrams showing only one of the IQ channels of the zero IF receiver of FIG. 58. Here, how the DC offset output of the mixer 16 fluctuates by switching the gain of the RF amplifier 11 will be described. FIG. 60A shows the state of mode E in FIG. 59, that is, the state where the gain of the RF amplifier 11 is set to 0 dB. On the other hand, FIG. 61A shows the state of the mode D, that is, the gain of the RF amplifier 11 is set to 20 dB. The gain of the RF amplifier 11 is switched from the state of FIG. 60A to 20 dB in FIG. 61 by the RF amplifier gain switching control signal 118 sent from the control unit (not shown) (from the mode E in FIG. 59). Mode D). At this time, the amount reflected from the local oscillator 18 through the mixer 16 and reflected by the RF amplifier 11 is different between the reflected wave 124 in FIG. 60A and the reflected wave 125 in FIG. 61A. This is because the output impedance of the RF amplifier 11 is different between FIG. 60 (b) and FIG. 61 (b). At this time, in both cases of FIG. 60 (b) and FIG. 61 (b), a direct current (DC) component due to self-mixing is superimposed on the desired signal component 123 at the mixer output 122. Here, the mixer DC output DCLOW in the case of FIG. 60B and the DC output DCHIGH of the mixer in the case of FIG. 61B have different values for the above reason. Therefore, when the gain of the RF amplifier 11 is switched from 0 dB (the state shown in FIG. 60B) to 20 dB (the state shown in FIG. 61B) (from the mode E to the mode D in FIG. 59), the output of the mixer 16 is changed. Causes a DC offset fluctuation of a difference between DCLOW and DCHIGH.
[0019]
As described above, even when the gain of the mixer 16 is constant (a change in the mixer gain at the time of switching from the mode E to the mode D = 0 dB), the output of the mixer 16 has a DC offset variation in accordance with the gain switching of the RF amplifier 11. Will happen.
[0020]
The phenomenon in which the DC offset output changes as described above does not occur only when the gain of the RF amplifier 11 is changed. A change in the DC offset also occurs due to a change in the gain of the mixer 16, the amplifier 26, or the like, as in the case of the change in the gain of the RF amplifier 11. Further, in circuits with different gains, the output DC component of the circuit alone is different, and this also causes a DC offset fluctuation when the gain of the circuit is switched.
[0021]
If such a DC offset variation occurs during a call, a very fast correction of the DC offset variation is required. This will be described with reference to FIG. FIG. 62A is a diagram showing a reception time slot of TDMA, and FIG. 62B is an enlarged view of the reception time slot. In FIG. 62A, the code T is the TDMA frame length. After receiving the reception time slot 126 allocated to the own terminal in the mode E of FIG. 59, the mode shifts to the mode D at the gain switching timing 129, and the next slot 127 is received. Here, at the gain switching timing 129, the DC offset changes from D to E. When correcting the DC offset, it is necessary to perform the DC offset correction before the start time 130 of the reception time slot. However, in a system in which the frame length T is very short, the required operation time may not be enough. Further, as shown in FIG. 62 (b), when it is necessary to perform gain switching of mode A, mode B, mode C, mode D, and mode E in reception time slot 127 allocated to the terminal itself. It is necessary to instantaneously perform DC offset correction. When the instantaneous DC offset correction cannot be realized, the DC offsets A, B, C, D, and E in the respective reception modes are different as shown in FIG. , And the receiving characteristics are greatly degraded.
[0022]
Further, in the conventional direct conversion receiver, the LPFs 18 and 19 can be formed into an LSI. And the receiving characteristics may be degraded.
[0023]
[Problems to be solved by the invention]
As described above, the conventional direct conversion receiver has a problem that the reception error rate is deteriorated due to the DC offset generated when the received signal is processed by the analog signal processing circuit. Further, in the superheterodyne receiver, a decrease in the reception error rate due to the time variation of the DC offset is a problem.
[0024]
Further, even if the DC offset is removed only by the AC couple, if the DC offset varies with time, there is a disadvantage that the influence of the DC offset cannot be completely removed due to a transient response in the AC couple. Further, for a received signal having a DC signal component, the AC couple deletes a part of the signal component, so that the reception characteristic may be deteriorated due to the partial deletion of the signal component. In addition, there is a problem that a sufficient DC offset removing function cannot be exerted simply by providing an AC couple in the analog signal processing unit.
[0025]
Since a reception error rate is degraded due to a DC offset generated when the received signal is processed by the analog signal processing circuit, there is a drawback that good communication cannot be performed in a system using such a receiver.
[0026]
Further, in a receiver including a conventional quadrature demodulation unit, there has been a problem of deterioration of reception characteristics due to a DC offset generated in an analog signal processing unit. A method of detecting and correcting a DC offset is also conceivable, but the time required for DC offset detection and correction has been a problem. Therefore, there has been a problem that it is not possible to cope with a DC offset fluctuation which occurs at the time of high-speed gain switching of the radio unit, which is required when there is a sudden change in amplitude of the reception level or when the reception level is unknown.
[0027]
In addition, there is a problem that the reception characteristics are deteriorated due to the variation of the cutoff frequency of the filter to be formed into an LSI. Because of the degradation of the reception error rate due to the DC offset generated when the received signal is processed by the analog signal processing circuit and the variation of the cut-off frequency of the filter, a good call can be made in a system using such a receiver. There was a disadvantage that it could not be done.
[0028]
Further, when performing DC offset detection, if a signal wave having a DC component other than the DC offset component to be detected is received, the DC offset cannot be accurately detected. For this reason, when a radio wave used in another wireless communication system is received from the antenna, there is a possibility that the DC offset cannot be accurately detected due to the influence of the incoming wave.
[0029]
The present invention uses a receiver capable of accurately removing a DC offset following a time variation even when a DC offset generated in an analog processing unit varies with time, and using the receiver. It is intended to provide a communication system.
[0030]
[Means for Solving the Problems]
To achieve the above object, a receiver according to claim 1 includes a receiving unit that receives a radio frequency signal, and an analog signal processing that performs amplification, band conversion, and frequency conversion on an analog signal input from the receiving unit. DC offset removing function, comprising: an analog-to-digital conversion section for converting an output of the analog signal processing section from an analog signal to a digital signal; and a digital signal processing section for processing the digital signal converted by the analog-to-digital conversion section. A receiver provided in the digital signal processing unit for detecting a DC offset signal generated in the receiving unit or the frequency conversion unit; and the offset detection unit provided in the digital signal processing unit. Offset holding means for holding the DC offset signal detected by the A D / A converter for converting the DC offset signal detected by the signal processor into an analog signal, and the analog converter based on the DC offset signal provided in the analog signal processor and converted to an analog signal by the DA converter. First offset correction means for correcting the signal; A second offset correction unit provided in the digital signal processing unit and digitally reducing a part of the DC offset signal held by the offset holding unit to reduce the DC offset; When the absolute value of the detected offset exceeds a predetermined threshold, at least an offset allocating unit for correcting the offset exceeding the predetermined threshold by the first offset correction unit, It is characterized by having.
[0031]
The receiver according to claim 2 is the receiver according to claim 1, wherein the DC offset held by the offset holding unit is included. Is updated every time an offset is detected by the offset detection means. It is characterized by:
[0032]
Further, the receiver according to claim 3 is the receiver according to claim 3. 1 In the receiver described in the above, The predetermined threshold is a power of two It is characterized by:
[0033]
The receiver according to claim 4 is A receiving unit for receiving a radio frequency signal, an analog signal processing unit for amplifying, band converting, and frequency converting the analog signal input from the receiving unit; and converting the output of the analog signal processing unit from an analog signal to a digital signal. And a digital signal processing unit for processing the digital signal converted by the AD conversion unit. The receiver having a DC offset removing function, the receiver being provided in the digital signal processing unit Offset detection means for detecting a DC offset signal generated in the receiving unit or the frequency conversion unit, and offset holding means provided in the digital signal processing unit and holding the DC offset signal detected by the offset detection means, The DC offset signal detected by the digital signal processing unit is A DA converter for converting to a log signal, a first offset correction unit provided in the analog signal processing unit and correcting the analog signal based on a DC offset signal converted to an analog signal by the DA converter; A second offset correction unit provided in the digital signal processing unit and digitally reducing a part of the DC offset signal held by the offset holding unit to reduce the DC offset; The higher-order bit of the offset is converted to an analog value by the DA converter, the offset is corrected by the first offset correction means, and the lower-order bit of the offset held in the offset holding means is used. The offset is corrected by the second offset correcting means. It is characterized by:
[0034]
The receiver according to claim 5 is A receiving unit for receiving a radio frequency signal, an analog signal processing unit for amplifying, band converting, and frequency converting the analog signal input from the receiving unit; and converting the output of the analog signal processing unit from an analog signal to a digital signal. And a digital signal processing unit for processing the digital signal converted by the AD conversion unit. The receiver having a DC offset removing function, the receiver being provided in the digital signal processing unit Offset detection means for detecting a DC offset signal generated in the receiving unit or the frequency conversion unit, and offset holding means provided in the digital signal processing unit and holding the DC offset signal detected by the offset detection means, The DC offset signal detected by the digital signal processing unit is A DA converter for converting to a log signal, a first offset correction unit provided in the analog signal processing unit and correcting the analog signal based on a DC offset signal converted to an analog signal by the DA converter; A second offset correction unit provided in the digital signal processing unit and digitally reducing a part of the DC offset signal held by the offset holding unit to reduce the DC offset, and the offset holding unit includes: First storage means for holding at least the initial value of the offset detected by the offset detection means; and the offset after the offset is corrected by the first and second offset correction means based on the initial value of the offset. Of the offset varying with time detected by the detecting means. Comprising second storage means for holding the moving component, the It is characterized by:
[0035]
Further, the receiver according to claim 6 is the receiver according to claim 6. 5 In the receiver described in The initial value of the offset stored in the first storage unit is detected only once by the offset detection unit and is not changed thereafter. It is characterized by:
[0036]
Further, the receiver according to claim 7 is the receiver according to claim 7. 5 In the receiver described in The initial value of the offset stored in the first storage means is detected and set when power is turned on. It is characterized by:
[0037]
Also, the receiver according to claim 8 is the receiver according to claim 5 In the receiver described in 1, the initial value of the offset stored in the first storage means, Detected and updated each time a predetermined period elapses It is characterized by:
[0038]
Further, the receiver according to claim 9 is the receiver according to claim 9. 5 In the receiver described in the above, the initial value of the offset stored in the first storage means, Updated when the variation of the offset that changes with time exceeds a predetermined value It is characterized by:
[0039]
Further, the receiver according to claim 10 is the receiver according to claim 5 In the receiver according to the above, The offset variation stored in the second storage unit is corrected by the second offset correction unit provided in the digital signal processing unit. It is characterized by:
[0040]
Further, the receiver according to claim 11 is the receiver according to claim 11. 5 In the receiver described in 1, the initial value of the offset stored in the first storage means, The variation of the offset, which is corrected by the first offset correction means provided in the analog signal processing unit and stored in the second storage means, is calculated by the second offset correction means provided in the digital signal processing unit. Is corrected by the offset correction means It is characterized by:
[0041]
Further, the receiver according to claim 12 is: A receiving unit for receiving a radio frequency signal, an analog signal processing unit for amplifying, band converting, and frequency converting the analog signal input from the receiving unit; and converting the output of the analog signal processing unit from an analog signal to a digital signal. And a digital signal processing unit for processing the digital signal converted by the AD conversion unit. The receiver having a DC offset removing function, the receiver being provided in the digital signal processing unit Offset detection means for detecting a DC offset signal generated in the receiving unit or the frequency conversion unit, Previous Offset holding means provided in the digital signal processing section for holding the DC offset signal detected by the offset detection means, and DA conversion for converting the DC offset signal detected by the digital signal processing section into an analog signal And a first offset correction unit provided in the analog signal processing unit and configured to correct the analog signal based on a DC offset signal converted into an analog signal by the DA conversion unit. Means for measuring the received electric field strength input via the unit, means for setting a plurality of gains in the analog signal processing unit based on the received electric field strength, and the plurality of sets set in the analog signal processing unit Said offset detecting means for detecting a plurality of DC offset values generated in accordance with a gain; The offset holding means for holding the DC offset value of the above, and the first offset correction means for correcting the DC offset value corresponding to the gain set in the analog signal processing section, further comprising the analog signal processing The unit includes a mixer pair for frequency-converting at least an in-phase component and a quadrature component of the radio frequency signal input to the reception unit and a signal orthogonal to each other, and an in-phase component channel and a quadrature component channel that are outputs of the mixer pair. And a baseband filter provided respectively, wherein the first offset correction means is provided at least in a preceding stage of the baseband filter for correcting the DC offset generated in the analog signal processing unit. It is characterized by:
[0042]
Further, the receiver according to claim 13 has the following features. 12 In the receiver described in An analog signal processing unit set to a first gain value, the AD conversion unit converting an output of the analog signal processing unit into a digital value, an overflow detection circuit detecting an overflow state of the AD conversion unit, Control means for controlling a gain of the analog signal processing unit to be set to a second gain value smaller than the first gain value when an overflow state is detected by the overflow detection circuit. It is characterized by:
[0043]
Further, the receiver according to claim 14 is the claim Thirteen In the receiver described in The analog signal processing unit includes a storage unit that detects and stores a DC offset generated from an input radio frequency signal, and the first offset correction unit reads the DC offset from the storage unit even in a single reception. Correct DC offset based on unity gain value It is characterized by:
[0044]
The receiver according to claim 15 is: A receiving unit for receiving a radio frequency signal, an analog signal processing unit for amplifying, band converting, and frequency converting the analog signal input from the receiving unit; and converting the output of the analog signal processing unit from an analog signal to a digital signal. And a digital signal processing unit for processing the digital signal converted by the AD conversion unit. The receiver having a DC offset removing function, the receiver being provided in the digital signal processing unit Offset detection means for detecting a DC offset signal generated in the receiving unit or the frequency conversion unit, Previous Offset holding means provided in the digital signal processing section for holding the DC offset signal detected by the offset detection means, and DA conversion for converting the DC offset signal detected by the digital signal processing section into an analog signal And a first offset correction unit provided in the analog signal processing unit and configured to correct the analog signal based on a DC offset signal converted into an analog signal by the DA conversion unit. An analog signal absent means for providing no input to the analog signal input to the signal processing unit is provided, and the offset detecting means detects the DC offset when the analog signal is absent, and the detected DC offset is detected at this time. The first offset correction means determines a DC offset based on the DC offset value. Is corrected, the analog signal no input means, is configured by a changeover switch provided between the radio frequency signal amplifier provided in the analog signal processing unit and the receiving unit, the analog signal no input means, An attenuator connected in parallel to a radio frequency signal amplifier provided in the analog signal processing unit, four switches provided before and after the amplifier and the attenuator, and provided on a connection line at a stage preceding the amplifier and the attenuator. And a signal supply path from the receiving unit to the analog signal processing unit is always connected, so that the analog signal processing unit can be set to a non-input state. It is characterized by:
[0045]
Further, the receiver according to claim 16 is: A receiving unit for receiving a radio frequency signal, an analog signal processing unit for amplifying, band converting, and frequency converting the analog signal input from the receiving unit; and converting the output of the analog signal processing unit from an analog signal to a digital signal. And a digital signal processing unit for processing the digital signal converted by the AD conversion unit. The receiver having a DC offset removing function, the receiver being provided in the digital signal processing unit Offset detection means for detecting a DC offset signal generated in the receiving unit or the frequency conversion unit, Previous Offset holding means provided in the digital signal processing section for holding the DC offset signal detected by the offset detection means, and DA conversion for converting the DC offset signal detected by the digital signal processing section into an analog signal And a first offset correction unit provided in the analog signal processing unit and configured to correct the analog signal based on a DC offset signal converted to an analog signal by the DA conversion unit. The detection means detects the DC offset by the time average of the output of the AD conversion unit, and the first offset correction means processes the DC offset converted to an analog signal by the DA conversion unit in the analog processing unit. Correct the DC offset by subtracting from the analog signal, The offset detecting means detects the DC offset of the current receiving slot with the time average value of the DC offset detected from the past receiving slot in the time division multiple access system as an initial value, and the first offset correcting means detects the detected current offset. The offset detection means comprises a cumulative addition circuit for cumulatively adding the digital signal input from the AD converter, and a division circuit for dividing the cumulatively added signal. A plurality of delay circuits for delaying the output of the offset detection means by a predetermined time, and a weighting set in advance so that the value delayed by the delay circuit becomes heavier the closer to the DC offset. A plurality of weighting circuits for multiplying and outputting coefficients, and an output of the weighting circuit; An adding circuit for outputting the value as a DC offset value a sum is more configuration It is characterized by:
[0046]
Further, the receiver according to claim 17 is the receiver according to claim 16, Each weighting coefficient of the plurality of weighting circuits is set so that the older the weight, the lighter and the newer the weight. It is characterized by:
[0047]
Further, the receiver according to claim 18 has the following features. 16 In the receiver described in The weighting coefficient set in the plurality of weighting circuits changes according to a time-varying amount of change in the DC offset detected by the offset detection right unit. It is characterized by:
[0048]
The receiver according to claim 19 is: A receiving unit for receiving a radio frequency signal, an analog signal processing unit for amplifying, band converting, and frequency converting the analog signal input from the receiving unit; and converting the output of the analog signal processing unit from an analog signal to a digital signal. And a digital signal processing unit for processing the digital signal converted by the AD conversion unit. The receiver having a DC offset removing function, the receiver being provided in the digital signal processing unit Offset detection means for detecting a DC offset signal generated in the receiving unit or the frequency conversion unit, Previous Offset holding means provided in the digital signal processing section for holding the DC offset signal detected by the offset detection means, and DA conversion for converting the DC offset signal detected by the digital signal processing section into an analog signal And a first offset correction unit provided in the analog signal processing unit and configured to correct the analog signal based on a DC offset signal converted into an analog signal by the DA conversion unit. A test signal generator for providing a test mode for testing a band limiting characteristic of the signal processing unit, wherein the digital signal processing unit generates a test signal for testing the band limiting characteristic of the analog signal processing unit; and The output from the test signal generator in the test mode An adder that adds a test signal to the DC offset signal, wherein the first correction unit outputs the output of the adder after being converted into an analog signal by the DA converter to the analog signal processing unit. Supply as input to the provided band limiting circuit It is characterized by:
[0049]
The receiver according to claim 20 is the receiver according to claim 20. 19 In the receiver described in The analog signal processing unit tests the band limiting characteristic of the analog signal processing unit after the DC offset is detected by the offset detection unit and the DC offset is held by the offset holding unit. It is characterized by:
[0050]
Further, the receiver according to claim 21 is the claim 19 In the receiver described in The analog signal processing unit includes a band limiting circuit having a function of adjusting a band limiting characteristic of the analog signal by a frequency characteristic control signal, and the digital signal processing unit is supplied to the band limiting circuit during the test mode. A frequency characteristic control unit that generates the frequency characteristic control signal according to a difference between a frequency characteristic detected by the test signal and a desired frequency characteristic. It is characterized by:
[0051]
Further, according to claim 22 The communication system includes a transmitter for transmitting a radio frequency signal including an information signal including audio and video, a communication network for transmitting and receiving the radio frequency signal, and a receiving unit for receiving the radio frequency signal. An analog signal processing unit that performs amplification, band conversion, and frequency conversion processing on an analog signal input from a reception unit; an AD conversion unit that converts an output of the analog signal processing unit from an analog signal to a digital signal; A digital signal processing unit for processing the digital signal converted by the conversion unit; offset detection means provided in the digital signal processing unit for detecting a DC offset signal generated in the receiving unit or the frequency conversion unit; A processing unit that holds the DC offset signal detected by the offset detection unit; Offset holding means, a DA converter for converting the DC offset signal detected by the digital signal processor into an analog signal, and a DC provided in the analog signal processor and converted to an analog signal by the DA converter. First offset correction means for correcting the analog signal based on the offset signal, and digitally reducing a part of the DC offset signal provided in the digital signal processing unit and held by the offset holding means, A second offset correction unit that reduces a DC offset, and when an absolute value of the detected offset detected by the offset detection unit exceeds a predetermined threshold, at least an offset exceeding the predetermined threshold is used for the offset. Offset for correction by the first offset correction means Comprising Ri and receiver with a DC offset removing function of and means, the divided, the It is characterized by:
[0052]
According to claim 23, The communication system includes: a transmitter for transmitting a radio frequency signal including an information signal including audio and video; a communication network for transmitting and receiving the radio frequency signal; a receiving unit for receiving the radio frequency signal; An analog signal processing unit for performing amplification, band conversion, and frequency conversion processing on an analog signal input from a unit, an AD conversion unit for converting an output of the analog signal processing unit from an analog signal to a digital signal, and an AD conversion unit A digital signal processing unit for processing the digital signal converted by the unit; offset detection means provided in the digital signal processing unit for detecting a DC offset signal generated in the receiving unit or the frequency conversion unit; A holding unit for holding the DC offset signal detected by the offset detection means. Set holding means, a DA converter for converting the DC offset signal detected by the digital signal processor into an analog signal, and a DC provided in the analog signal processor and converted to an analog signal by the DA converter. First offset correction means for correcting the analog signal based on the offset signal, and digitally reducing a part of the DC offset signal provided in the digital signal processing unit and held by the offset holding means, A second offset correction means for reducing a DC offset, wherein the higher-order bit of the offset held in the offset holding means is converted into an analog value by the DA converter, and the first offset correction means As well as being held by the offset holding means. And a receiver having a DC offset removal function of correcting an offset by the second offset correction means using a lower bit of the offset It is characterized by:
[0053]
According to claim 24, The communication system includes: a transmitter for transmitting a radio frequency signal including an information signal including audio and video; a communication network for transmitting and receiving the radio frequency signal; a receiving unit for receiving the radio frequency signal; An analog signal processing unit for performing amplification, band conversion, and frequency conversion processing on an analog signal input from a unit, an AD conversion unit for converting an output of the analog signal processing unit from an analog signal to a digital signal, and an AD conversion unit A digital signal processing unit for processing the digital signal converted by the unit; offset detection means provided in the digital signal processing unit for detecting a DC offset signal generated in the receiving unit or the frequency conversion unit; A holding unit for holding the DC offset signal detected by the offset detection means. Set holding means, a DA converter for converting the DC offset signal detected by the digital signal processor into an analog signal, and a DC provided in the analog signal processor and converted to an analog signal by the DA converter. First offset correction means for correcting the analog signal based on the offset signal, and digitally reducing a part of the DC offset signal provided in the digital signal processing unit and held by the offset holding means, Second offset correction means for reducing a DC offset, The offset holding means A first storage unit for storing at least an initial value of the offset detected by the offset detection unit; and a first storage unit for correcting the offset by the first and second offset correction units based on the initial value of the offset. A receiver having a DC offset removal function, comprising: a second storage unit that holds a variation in offset that changes with time detected by the offset detection unit. It is characterized by:
[0054]
According to claim 25, The communication system includes a transmitter for transmitting a radio frequency signal including an information signal including audio and video, a communication network for transmitting and receiving the radio frequency signal, and a receiving unit for receiving the radio frequency signal. An analog signal processing unit that performs amplification, band conversion, and frequency conversion processing on an analog signal input from a reception unit; an AD conversion unit that converts an output of the analog signal processing unit from an analog signal to a digital signal; A digital signal processing unit that processes the digital signal converted by the conversion unit; and an offset detection unit that is provided in the digital signal processing unit and detects a DC offset signal generated by the reception unit or the frequency conversion unit. Previous Offset holding means provided in the digital signal processing section for holding the DC offset signal detected by the offset detection means, and DA conversion for converting the DC offset signal detected by the digital signal processing section into an analog signal A first offset correction unit provided in the analog signal processing unit and configured to correct the analog signal based on a DC offset signal converted to an analog signal by the DA conversion unit; and an input through the reception unit. Means for measuring the received electric field strength, means for setting a plurality of gains in the analog signal processing unit based on the received electric field strength, and corresponding to the plurality of gains set in the analog signal processing unit. The offset detecting means for detecting a plurality of generated DC offset values; and the plurality of DC offsets. The offset holding means, and the first offset correction means for correcting the DC offset value corresponding to the gain set in the analog signal processing unit, further, the analog signal processing unit, A mixer pair for frequency-converting at least the in-phase component and the quadrature component of the radio frequency signal input to the receiving unit, which are orthogonal to each other, are provided in the in-phase component channel and the quadrature component channel which are outputs of the mixer pair, respectively. A baseband filter, and the first offset correction unit has a DC offset removal function provided at least in a preceding stage of the baseband filter to correct the DC offset generated in the analog signal processing unit. And a receiver It is characterized by:
[0055]
According to claim 26, The communication system includes a transmitter for transmitting a radio frequency signal including an information signal including audio and video, a communication network for transmitting and receiving the radio frequency signal, and a receiving unit for receiving the radio frequency signal. An analog signal processing unit that performs amplification, band conversion, and frequency conversion processing on an analog signal input from a reception unit; an AD conversion unit that converts an output of the analog signal processing unit from an analog signal to a digital signal; A digital signal processing unit that processes the digital signal converted by the conversion unit; and an offset detection unit that is provided in the digital signal processing unit and detects a DC offset signal generated by the reception unit or the frequency conversion unit. Previous Offset holding means provided in the digital signal processing section for holding the DC offset signal detected by the offset detection means, and DA conversion for converting the DC offset signal detected by the digital signal processing section into an analog signal And a first offset correction unit provided in the analog signal processing unit and configured to correct the analog signal based on a DC offset signal converted into an analog signal by the DA conversion unit. An analog signal absent means for providing no input to the analog signal input to the signal processing unit is provided, and the offset detecting means detects the DC offset when the analog signal is absent, and the detected DC offset is detected at this time. The first offset correction means determines a DC offset based on the DC offset value. Is corrected, the analog signal no input means, is configured by a changeover switch provided between the radio frequency signal amplifier provided in the analog signal processing unit and the receiving unit, the analog signal no input means, An attenuator connected in parallel to a radio frequency signal amplifier provided in the analog signal processing unit, four switches provided before and after the amplifier and the attenuator, and provided on a connection line at a stage preceding the amplifier and the attenuator. And a DC offset removing function that enables the analog signal processing unit to be in a non-input state even when the signal supply path from the receiving unit to the analog signal processing unit is always connected. Equipped with a receiver It is characterized by:
[0056]
According to claim 27, The communication system includes a transmitter for transmitting a radio frequency signal including an information signal including audio and video, a communication network for transmitting and receiving the radio frequency signal, and a receiving unit for receiving the radio frequency signal. An analog signal processing unit that performs amplification, band conversion, and frequency conversion processing on an analog signal input from a reception unit; an AD conversion unit that converts an output of the analog signal processing unit from an analog signal to a digital signal; A digital signal processing unit that processes the digital signal converted by the conversion unit; and an offset detection unit that is provided in the digital signal processing unit and detects a DC offset signal generated by the reception unit or the frequency conversion unit. Previous Offset holding means provided in the digital signal processing section for holding the DC offset signal detected by the offset detection means, and DA conversion for converting the DC offset signal detected by the digital signal processing section into an analog signal And a first offset correction unit provided in the analog signal processing unit and configured to correct the analog signal based on a DC offset signal converted to an analog signal by the DA conversion unit. The detection means detects the DC offset by the time average of the output of the AD conversion unit, and the first offset correction means processes the DC offset converted to an analog signal by the DA conversion unit in the analog processing unit. Correct the DC offset by subtracting from the analog signal, The offset detecting means detects the DC offset of the current receiving slot with the time average value of the DC offset detected from the past receiving slot in the time division multiple access system as an initial value, and the first offset correcting means detects the detected current offset. The offset detecting means comprises a cumulative addition circuit for cumulatively adding the digital signal input from the AD converter, and a division circuit for dividing the cumulatively added signal. A plurality of delay circuits for delaying the output of the offset detection means by a predetermined time, and a weighting set in advance so that a value delayed by the delay circuit becomes heavier as the DC offset becomes closer to the DC offset. A plurality of weighting circuits for multiplying and outputting coefficients, and an output of the weighting circuit; Comprises an adding circuit for outputting the value a sum as a DC offset value, and a receiver with a DC offset removing features that are more configuration It is characterized by:
[0057]
According to claim 28, A wireless communication system, a transmitter that transmits a radio frequency signal composed of an information signal including audio and video, a communication network for transmitting and receiving the radio frequency signal, and a receiving unit that receives the radio frequency signal, An analog signal processing unit that performs amplification, band conversion, and frequency conversion processing on the analog signal input from the reception unit; an AD conversion unit that converts the output of the analog signal processing unit from an analog signal to a digital signal; A digital signal processing unit that processes the digital signal converted by the AD conversion unit; and an offset detection unit that is provided in the digital signal processing unit and detects a DC offset signal generated by the reception unit or the frequency conversion unit. Previous Offset holding means provided in the digital signal processing section for holding the DC offset signal detected by the offset detection means, and DA conversion for converting the DC offset signal detected by the digital signal processing section into an analog signal And a first offset correction unit provided in the analog signal processing unit and configured to correct the analog signal based on a DC offset signal converted into an analog signal by the DA conversion unit. A test signal generator for testing a band limiting characteristic of the signal processing unit, wherein the digital signal processing unit generates a test signal for testing the band limiting characteristic of the analog signal processing unit; and The output from the test signal generator in the test mode An adder that adds a test signal to the DC offset signal, wherein the first correction unit outputs the output of the adder after being converted into an analog signal by the DA converter to the analog signal processing unit. A receiver having a DC offset removing function to be supplied as an input of the provided band limiting circuit. It is characterized by:
[0060]
If the communication system is configured as described above, the DC offset generated in the analog signal processing circuit at the input of the A / D converter of the receiver can be reduced, so that the signal exceeds the input range of the A / D converter due to the DC offset. Distortion can be prevented, deterioration of the reception error rate can be reduced, and good communication can be performed. In addition, since the AC couple is not used, there is no influence of the transient response of the time change of the DC offset, so that the reception error rate is not deteriorated, so that good communication can be performed. Furthermore, it is possible to remove only a DC offset component which is an error with respect to a signal using a modulation method including a large number of low frequency components including DC, so that it is possible to reduce an error rate of a received signal and perform good communication. Can be.
[0061]
Further, with the above-described configuration, by storing the offset value only once when the power is turned on, a rough offset can be removed even immediately after the start of a call, so that deterioration of the reception error rate can be reduced.
[0062]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of a receiver having a DC offset removing function according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a configuration of a receiver having a DC offset removing function according to the first embodiment of the present invention.
[0063]
In FIG. 1, a high-frequency signal received by an antenna 2 constituting a signal input unit 1 is amplified by an RF amplifier 11 in an analog signal processing circuit 10, and then a local oscillator 13, a mixer 14, and a band-pass filter (hereinafter, referred to as a BPF). -Abbreviated as "Band-Pass Filter-" 15. The frequency is once converted into an intermediate frequency by a frequency converter 202 composed of 15 and distributed to two systems. Then, the mixer 16 and the mixer 17 respectively mix the carrier with a carrier having substantially the same frequency as the intermediate frequency signal supplied from the local oscillator 18 and directly convert the frequency into a baseband frequency band. Here, the local oscillator 18 is directly connected to the mixer 16, and is connected to the mixer 17 via a π / 2 phase shifter 19. Therefore, the two signals that have been frequency-converted into baseband have a phase difference of π / 2 from each other. Unnecessary frequency components are removed from these two baseband signals by LPFs 22 and 23, each of which plays a role of channel selection. Thereafter, the baseband signal is amplified to a desired signal level by the baseband amplifiers 28 and 29, and then A / D-converted by the A / D converter 3 to detect and demodulate the digital signal processing circuit 40. 50 demodulates the original data.
[0064]
In the digital signal processing circuit 40, the DC offsets superimposed on the respective baseband signals are detected by the DC offset detecting means 41 and 42, and the DC offset holding means 43 and 44 hold the respective DC offsets. The held DC offset is converted from a digital signal to an analog signal by the D / A converter 5, and is applied to the output side of the first offset correction means 24, 25 or the amplifiers 26, 27 provided at the outputs of the LPFs 22, 23. The DC offset converted into an analog signal by the D / A converter 5 is subtracted from the baseband signal by the first offset means 28 and 29 provided.
[0065]
Thereby, the DC offset generated in the analog signal processing circuit 10 at the input of the A / D converter 3 can be reduced, and the reception error rate can be reduced. Further, it is possible to prevent the signal from being distorted beyond the input range of the A / D converter due to the DC offset, and it is also possible to prevent a reception error caused by this distortion. Further, since the AC couple is not used, it is not affected by the transient response of the time change of the DC offset, and the reception error rate is not deteriorated. In particular, it is possible to remove only a DC offset component that causes an error with respect to a signal of a modulation method including many low frequency components including DC, so that it is possible to reduce deterioration of an error rate of a received signal.
[0066]
Further, the DC offset converted into an analog signal by the D / A converter 5 may be subtracted from the baseband signal frequency-converted by the first offset correction means 20, 21 immediately after the mixers 16, 17. In particular, in this case, by detecting and holding the DC offset at a predetermined gain in advance, the DC offset at the mixer output (LPF input) can be used in response to a change in the DC offset caused by gain switching before frequency conversion. Can be canceled, so that the transient response of the residual DC offset due to the time constant of the LPF can be reduced as compared with the case of canceling after the LPF output.
[0067]
In FIG. 1, even in a direct conversion receiver having no frequency converter 12, it is exactly the same that the DC offset can be removed and the error rate of the received signal can be reduced. Also, by using such a receiver in a wireless communication system, the error rate of a received signal can be reduced, and good communication can be performed.
[0068]
FIG. 2 shows a receiver according to a second embodiment in which second offset correction means 45 and 46 are provided in a digital signal processing circuit 40. In FIG. 2, a part of the DC offset held by the DC offset holding means 43, 44 is removed by the second offset correction means 45, 46. As a result, in the analog signal processing circuit 10, the first offset correction means 20 and 21 roughly correct the DC offset so as to prevent the signal from being distorted beyond the input range of the A / D converter due to the DC offset. In the digital signal processing circuit 40, fine DC offset correction can be performed by the second offset correction means 46 and 47. Therefore, the precision of the D / A converter 5 and the precision of the correction by the first offset correction means 20 and 21 can be relaxed, so that the expensive high precision D / A converter 5 and the first offset correction means 20 and 21 can be reduced. A high-precision analog subtractor is not required, and the cost can be reduced.
[0069]
It should be noted that the DC offset is accurately removed by repeatedly detecting the DC offset with time by the DC offset detecting means and updating the offset value held in the offset holding means every time the offset is detected. be able to. For example, when the received signal is TDMA, it may be performed before a reception slot periodically allocated to the own terminal starts.
[0070]
The offset holding means 43 in FIG. 2 includes a first storage means 47 for holding an initial value of the offset as shown in FIG. 3, and a DC offset detecting means for correcting the offset based on the initial value of the offset. By providing the second storage means 48 for holding a portion of the offset that changes with time, the change of the DC offset with time may be handled. The offset holding means 44 has the same configuration as the offset holding means 43 shown in FIG.
[0071]
For example, the DC offset detected by the DC offset detecting means may be set as the initial value when the input from the antenna is cut off at the time of shipment or when the power is turned on. In particular, when the temporal change of the DC offset, such as the DC offset occurring in response to the fading pitch, is small in view of the entire DC offset, it is only necessary to set the initial value once at the time of shipment. Thus, since the DC offset held in the first storage means is removed in advance, it is possible to reduce the deterioration of the reception error rate when receiving the reception slot allocated to the terminal for the first time after the power is turned on.
[0072]
In FIG. 2, the distribution of the DC offset to be corrected to the first and second offset correction means is performed by a first and second offset correction means according to a predetermined threshold Ref1, for example, as in the third embodiment shown in FIG. The threshold value Ref1 is set to a value that does not cause the signal to be distorted beyond the input range of the A / D converter 3 even if there is a DC offset, by the distribution means 51 and 52 that distributes the DC offset to be corrected. Just fine.
[0073]
FIG. 5 is a block diagram showing an example of a specific configuration of the offset distribution unit 51 (or 52). The comparing unit 54 compares the DC offset input from the offset holding unit 43 (or 44) with a predetermined threshold value calculated by the absolute value calculating unit 53 for the absolute value of the DC offset. Further, the polarity of the threshold Ref1 is matched with the polarity of the input DC offset by the polarity selection circuit 55, and is subtracted from the input DC offset by the subtraction circuit 56. When the absolute value of the input DC offset is larger than the threshold value Ref1, the output of the subtraction circuit 56 is selected by the switch means SW2 by the output of the comparison means 54, and is converted to an analog value by the D / A converter 5, and is converted to the first offset. The output of the polarity selection circuit 55 is output to the correction means 20 and 21 and output to the second offset correction means by the switch means SW1. When the absolute value of the input DC offset is smaller than the threshold Ref1, the output to the D / A converter 5 is selected to be zero by the switch SW2 based on the output of the comparator 54. The DC offset input by the switch SW1 is selected for the second offset correction unit 45 (or 46).
[0074]
By configuring the offset distribution means 51 and 52 as described above, when the absolute value of the input DC offset exceeds the threshold value Ref1, the excess is input via the D / A converter 5. The output corresponding to the threshold value ReF1 is output to the first offset correction means 20 and 21 and output to the second offset correction means 45 and 46. If the absolute value of the input DC offset does not exceed the threshold value Ref1, all the DC offsets can be output to the second offset correction means 45 and 46.
[0075]
FIG. 6 shows a specific example of the comparing means 54 in FIG. 5 when the threshold value Ref1 is selected to be a value represented by a power of two. FIG. 6 shows a case where the Nth bit from the most significant bit (MSB) is selected as the threshold. The OR circuit 54A constituting the comparing means 54 ORs the N signals from the MSB of the input DC offset to the Nth bit to determine whether or not the DC offset is equal to or greater than the threshold value. No circuit is required. By selecting the threshold value Ref1 to be a value represented by a power of 2, the offset distribution means 51 and 52 can be simplified.
[0076]
FIG. 7 is a block diagram showing a receiver according to the fourth embodiment of the present invention. The first offset correcting means removes the upper bits of the detected and held DC offset, and the second offset correcting means removes the lower bits of the detected and held DC offset. Therefore, the upper bits are roughly offset-corrected by the analog signal processor 10, and the lower bits are finely offset-corrected by the digital signal processor 40. Thereby, the offset distributing means can be simplified.
[0077]
In FIG. 3 showing a specific configuration of the offset holding unit according to the second embodiment described above, the first storage unit 47 holds and outputs the initial value of the offset, and the second storage unit 48 stores the time. A configuration may be adopted in which the variation of the offset over time is held and output. Four specific examples of the method of setting the initial value will be described as a fifth embodiment with reference to FIGS.
[0078]
FIG. 8 is a flowchart showing a first initial value setting method. With the input from the antenna disconnected at the time of shipment, the DC offset detected by the DC offset detecting means 41, 42 is set as an initial value. That is, the antenna terminal is terminated as shown in step ST1 in FIG. 8, and the DC offset is detected as shown in ST2. After that, the initial value is stored in the first storage means 47 as shown in step ST3. When a change in the DC offset due to a temperature change, an aging change, or the like is small in view of the entire DC offset, it is only necessary to set an initial value once at the time of shipment. As a result, the DC offset previously held in the first storage means is removed, so that the reception error rate at the time of receiving the first reception slot allocated to the terminal at the start of a call is reduced. it can. The steps shown in FIG. 8 need only be performed once at the time of factory shipment. When the first initial value setting method is adopted, it is appropriate to use a read-only memory such as a ROM as the first storage means 47.
[0079]
When the radio unit has a plurality of gain modes as in a conventional receiver and generates a different DC offset in each gain mode, the same operation as described above is repeated by the number of gain modes. By storing the DC offset for the gain mode in the first storage means 47, the effective DC offset can be removed.
[0080]
Next, in a second initial value setting method, the DC offset detected by the DC offset detecting means 41 and 42 is set as the initial value in a state where the input from the antenna is cut off when the power is turned on. In particular, when the temporal variation of the DC offset is small in view of the entire DC offset, such as a DC offset generated corresponding to the fading pitch, it is only necessary to set the initial value once when the power is turned on. Thereby, since the DC offset held in the first storage means 47 is removed in advance, deterioration of the reception error rate when the reception slot assigned to the terminal is first received after the power is turned on can be reduced. .
[0081]
This processing step is shown in FIG. 9. In ST0, the power switch is turned on, the antenna terminal is terminated as shown in step ST1, and the DC offset is detected as shown in ST2. After that, the initial value is stored in the first storage means 47 as shown in step ST3. The above processing steps may be performed every time the power is turned on. When this method is employed, it is appropriate to use a readable / writable memory such as a RAM as the first storage means 47.
[0082]
Similarly to the first initial value setting method, when the radio unit has a plurality of gain modes as in a conventional receiver and generates different DC offsets in each gain mode, By repeating the same operation for the number of gain modes and storing the DC offset for each gain mode in the first storage means 47, it is possible to remove the effective DC offset.
[0083]
The third initial value setting method is to update the storage contents of the first storage means 47 at any time after a predetermined period elapses with the DC offset detected by the offset detection means 41 and 42. Even if the DC offset changes depending on the temperature or the like, according to the third method, the initial value can be effectively updated, and the deterioration of the reception error rate can always be reduced.
[0084]
As a specific processing operation, the antenna terminal is terminated as shown in step ST1 of FIG. 10, a DC offset is detected as shown in ST2, and then the initial value is stored in the first storage means 47 as shown in step ST3. And finally wait for a predetermined period to elapse as shown in step ST4. By repeating the above processing steps, the latest DC offset value is always held in the first storage means 47, and the initial value can be set more accurately.
[0085]
As a fourth initial value setting method, when the value of the DC offset detected by the offset detecting units 41 and 42 exceeds a predetermined threshold, the initial value stored in the first storage unit 47 is changed. To be updated. The DC offset varies with temperature and aging. If the variation is within a predetermined range, the DC offset is corrected using the offset value stored in the second storage means 48. Although it is possible to reduce the deterioration of the reception error rate, if it exceeds a predetermined range, it may not be possible to perform a sufficient correction by the DC offset correction using the second storage means. Therefore, it is necessary to prevent this.
[0086]
The processing steps of the fourth initial value setting method will be described with reference to FIG. As shown in FIG. 11, the operation of terminating the antenna terminal in step ST1 and detecting the DC offset in step ST2 is the same as the other initial value setting methods. After step ST2, it is determined in step ST5 whether the DC offset exceeds a predetermined threshold Vth. When it is determined that the value of the DC offset exceeds the predetermined threshold value Vth, the process proceeds to step ST3, and the DC offset is stored in the first storage unit 47 as an initial value. If it is determined in step ST5 that the value of the DC offset exceeds the predetermined threshold value Vth, the process proceeds to step ST4, and waits without any processing until a predetermined period elapses.
[0087]
By repeating the above processing, the value of the DC offset stored in the first storage means 47 is updated as necessary, and a more accurate initial value can be set.
[0088]
Next, how to set the predetermined threshold value Vth will be described with reference to FIG. Now, assume that the dynamic range of the A / D converter is Vad, and the maximum level of a signal input to the A / D converter is Vsig (pp). At this time, the DC offset that can be corrected by the second offset correction means is ± (Vad−Vsig) / 2 at the maximum. Therefore, by setting “Vth = (Vad−Vsig) / 2”, the fifth embodiment operates most efficiently. However, in practice, it is realistic to set “Vth = (Vad−Vsig) / 2−α” in consideration of the predetermined margin α.
[0089]
By using the receiver according to the fifth embodiment having the above-described first to fourth initial value setting methods, the variation of the offset that is converted with time and held in the second storage means 48 can be digitally processed. The correction is performed by a second offset correction unit provided in the unit 40. This is because the offset variation that changes with time stored in the second storage means 48 needs to be removed as quickly as possible because the change is relatively fast. Therefore, it is advantageous that the variation of the offset is digitally removed by the second offset correction means because it is the fastest in terms of time. The second offset correction means for digitally removing the offset is generally smaller in the range that can be corrected but is smaller than the fixed offset generated in comparison with the first offset correction means for correcting the offset in an analog manner. Since the offset that changes with time is considered to be sufficiently small, it does not pose a significant problem.
[0090]
For the initial value of the DC offset for each gain mode of the radio section stored in the first storage means 47, it is more effective to perform the offset correction by the first offset correction means. This is because the fixed offset value stored in the first storage means has a considerably large value compared to the variation of the offset stored in the second storage means, so that the correction range is wide. It is more effective to perform the correction by the first offset correction unit. Further, the correction of the fixed offset value stored in the first storage means is not changed once it is set, or even if it is changed, it is changed at a very long time cycle. For this reason, even if the correction is made in an analog manner by the first offset correction means, the problem of a time delay does not occur.
[0091]
Next, an embodiment in which correction of a DC offset and switching control of a gain of an analog signal processing unit are performed will be described. In some embodiments, a DC offset is detected for each of a plurality of gains of the receiver and stored in a memory, and the DC offset is optimally corrected for each state.
[0092]
FIG. 13 is a block diagram showing the configuration of the receiver according to the sixth embodiment. The basic configuration of the receiver according to the sixth embodiment is substantially the same as the configuration of the first embodiment shown in FIG. In the drawings, the same reference numerals are given, and the repeated description is omitted. The difference is that the switch 4 is provided at a position where the analog signal processing unit 10 receives the radio frequency signal from the antenna 2 of the receiving unit 1, and the receiving electric field intensity detection for detecting the receiving electric field intensity of the digital signal processing unit 40. A means 57 is provided, and a gain switching control signal 58 is output to the analog signal processing unit 10 based on the electric field strength detected by the electric field strength detecting means 57. Specifically, the RF amplifier 11 is supplied with the RF amplifier gain switching control signal 59, the quadrature demodulators of the mixers 16 and 17 are supplied with the mixer gain switching control signal 60, and amplifies the analog signal of the base frequency. The baseband amplifiers 26 and 27 are supplied with an amplifier gain switching control signal 61.
[0093]
The operation of the receiver according to the sixth embodiment based on the above configuration will be described. The high-frequency signal transmitted from the wireless base station is received by the antenna 2 and is low-noise amplified by the RF amplifier 11 via the switch 4. The RF amplifier 11 has a configuration in which the gain is variable by a switching control signal 59 supplied from the digital signal processing unit 40. The high-frequency signal amplified by the RF amplifier 11 is mixed with the reference carrier signal from the local oscillator 13 by the mixer 14 in the frequency converter 12 and then converted into an intermediate frequency signal by removing unnecessary components by the BPF 15. The output is divided into two systems, an in-phase component and a quadrature component. The in-phase and quadrature components divided into two systems are frequency-converted to base frequencies by mixers 16 and 17, respectively. The operation of this quadrature demodulation unit is the same as that of the receiver of the first embodiment shown in FIG. The mixers 16 and 17 are also supplied with a mixer gain switching control signal 60 from the digital signal processor 40. The DC offset component is removed by the first offset correction means 20 and 21 at the subsequent stage of the mixers 16 and 17, respectively. The configuration and operation are the same as those of the receiver of the first embodiment.
[0094]
The desired signals that have been frequency-converted to baseband by the mixers 16 and 17 are input to LPFs 22 and 23. The LPFs 22 and 23 have a channel selection function for removing unnecessary waves other than the desired waves and adjacent channel waves, and a subsequent stage. It is inserted in front of the A / D converter 3 to have an anti-aliasing function. The amplifiers 26 and 27 at the subsequent stage of the LPFs 22 and 23 are variable gain amplifiers, and are provided to supply a desired wave to the A / D converter 3 at the subsequent stage at a desired voltage level. The gains of the variable gain amplifiers 26 and 27 are variably controlled by an amplifier gain switching control signal 61 supplied from the digital signal processing unit 40. Therefore, when the dynamic range of the A / D converter 3 is sufficiently wide, the amplifiers 26 and 27 can be omitted.
[0095]
Although FIG. 13 has been described on the assumption that the mixer 13 of the frequency converter 12 has no gain variable function, the present invention is not limited to this, and the mixer 13 may have a gain variable function as necessary. It may be. Further, in the receiver of the sixth embodiment shown in FIG. 13, it has been described that the frequency converter 12 is provided. However, in principle, the present invention provides an in-phase component (I) and a quadrature component (Q). It is sufficient to provide a quadrature demodulation unit (mixers 22 and 23) having the two channels described above. The frequency converter 12 and the amplifiers 26 and 27 perform A / D conversion on the output signals of the LPFs 22 and 23 with sufficient amplitude. It is provided for delivery to the container 3. Therefore, when the A / D converter 3 is, for example, a multi-bit converter, omitting the amplifiers 26 and 27 does not depart from the gist of the present invention.
[0096]
When the above is embodied, the receiver according to the seventh embodiment shown in FIG. 14 is obtained. In FIG. 14, the frequency converter 12, and the variable gain amplifiers 26 and 27 are omitted as described above. The DC offset detecting means 41 and 42 and the DC offset holding means 43 and 44 provided in the digital signal processing unit 40 are configured as shown in FIGS. That is, FIG. 15A showing the first specific example is obtained by adding a reference average value correction circuit 62, and the reference average value correction circuit 62 includes a reference average value holding unit 63 and an adder 64. ing. The reference average value held in the holding unit 63 is a DC component originally included in the modulation signal component. In this case, if the DC offset is uniformly corrected, the original DC component may be removed. become. Therefore, when the DC component of the modulation scheme used in the system is known, a reference average value of the DC component is prepared in advance, and the DC offset obtained by the DC offset detection means 41 (or 42) is obtained. An accurate DC offset is obtained by subtracting the reference average value from the offset, and this is held by the DC offset holding means 43 (or 44). As shown in FIG. 15B showing the second specific example, the reference average value for detecting the DC offset after first subtracting the reference average value from the base frequency signal input from the A / D converter 3 The correction circuit 65 may be configured.
[0097]
Next, an operation procedure of the receiver according to the seventh embodiment will be described in detail with reference to a flowchart for the case of the receiver in FIG. As the gain switching mode of the receiving unit, four receiving modes shown in FIG. 16 are assumed. In FIG. 16, a total of four reception modes are set with the RF amplifier 11 having two gains of 10 dB and -30 dB, and the mixers 16 and 17 having two gains of 20 dB and 0 dB. The basic operation of the receiver shown in FIG. 13 is the same as the operation procedure described below, except that the gain switching control (control signal 61) for the amplifiers 26 and 27 exists. This receiver is suitably applied to a TDMA system as shown in FIG. In the following, it is assumed that reception is repeated in which the operation of receiving only the reception time slots 67 and 68 assigned to the own terminal is performed in the TDMA frame 66 having the period T shown in FIG.
[0098]
The receiver according to the present invention is characterized in that a DC offset generated for each reception mode of the analog signal processing unit 2 is assumed and held in advance, and is read out in each reception mode to be used to perform DC offset correction. .
[0099]
First, an operation procedure for detecting a DC offset and storing it as a DC offset correction value in the DC offset holding units 43 and 44 in FIG. 14 will be described with reference to the flowchart in FIG.
[0100]
In the flowchart of FIG. 18, first, the analog signal processing unit 10 is set to a state where the DC offset can be measured (ST11). In order to measure the DC offset generated by the analog signal processing unit 10 in FIG. 14 alone, it is necessary to prevent an external signal from being input from the signal input unit 1. For this purpose, for example, a high-frequency switch 4 that cuts off the input of the signal input unit 1 may be provided at the subsequent stage of the antenna 2 and the switch 4 may be set to “OFF” at the time of DC offset measurement. This high-frequency switch 4 can also be used as a transmission / reception switch in a receiver for a TDMA / TDD system, for example. Further, the analog signal processing unit 10 is set to a reception state in order to measure a DC offset generated in an actual operation state. In other words, when the battery saving function (not shown) is provided in each circuit of the analog signal processing unit 10, it is canceled, the local oscillator 18 is also operated, and the reference carrier signal is transmitted to the mixers 16 and 17. Set it.
[0101]
Next, n is set as a reception mode, and an initial value “1” is set (ST12). Here, when n = 1 to 4 correspond to the reception modes A to D in FIG. 16 according to the reception mode in FIG. 16, n = 1 becomes the mode A, and the RF amplifier 12 has 10 dB and the mixer 16 has 20 dB. Is set (ST13). In this mode A, the DC offset generated at the output of the analog signal processing unit 2 is detected by the DC offset detecting means 41 (or 42) having the configuration shown in FIG. 15 (ST14). The detected DC offset value is stored in the DC offset holding units 43 and 44 as a “DC offset correction value” when the analog signal processing unit 10 is set to the mode A (ST15). Subsequently, in the case of n = 2, that is, in the case of the reception mode B (ST17), similarly, the DC offset value generated in the analog signal processing unit 10 is measured and stored in the DC offset holding units 43 and 44.
[0102]
Finally, the DC offset value of n = 4 (reception mode D) is measured, stored in the DC offset holding units 43 and 44, and the process ends (ST16). Therefore, a DC offset value (= DC offset correction value) is obtained for each of the reception modes A to D. These DC offsets are shown as A to D in the rightmost column of FIG. The DC offset measurement value is stored and held in the DC offset holding unit 43 of FIGS. 13 and 14 in a format as shown in FIG. Note that the order of measuring each reception mode at the time of DC offset measurement can be set arbitrarily.
[0103]
Next, a procedure for selecting and setting the reception mode of the receiver according to the seventh embodiment employing the present DC offset correction will be described with reference to FIGS. FIG. 19 is a diagram showing an operation procedure for setting the optimum gain of the receiving unit for the receiver, that is, the receiving mode. The problem with setting the desired gain of the receiver is that there is no information about the received signal level. Therefore, when the signal level is extremely high or extremely low, there is a problem that the reception electric field intensity cannot be measured and the gain of the receiver cannot be set.
[0104]
The operation procedure in FIG. 19 is a method in which the receiver sets the optimum gain for each circuit of the analog signal processing unit 10 while measuring the reception electrification intensity. Here, four reception modes of reception modes A to D shown in FIG. 16 are assumed, and the reception modes A to D are described corresponding to n = 1 to 4. According to FIG. 19, first, the gain of each circuit of the analog signal processing unit 10 is set to the reception mode A when n = 1 (ST21, ST22). After that, as a DC offset correction value, a value (A in FIG. 16) corresponding to the reception mode A is read from the DC offset holding units 43 and 44 and sent to the first offset correction units 24 and 25 to set the DC offset correction. Is performed (ST23). In this state, an incoming signal is received (ST24), and the reception electric field intensity detection circuit 57 measures and detects the reception electric field intensity (ST25). The operation procedure of this step ST25 will be described later.
[0105]
Hereinafter, while the pure mode is sequentially set (ST12, ST12), when the C / N (C: signal strength, N: receiver thermal noise) at which the reception electric field strength can be detected is reached (ST16), the input signal is changed. The optimum reception mode for receiving the level is set (ST28). Here, the reception mode may be sequentially set from a mode with a large gain shown in FIG. 16 to a mode with a small gain (mode A to mode D), or vice versa. When it is necessary to set the optimum reception mode at a high speed, it is not always necessary to set the optimum reception mode one by one, and the setting may be performed every other or by skipping some.
[0106]
Here, the method of detecting the received electric field strength shown in ST25 of FIG. 19 will be described with reference to FIG. FIG. 20 is a diagram showing an operation procedure for measuring the electric field intensity. In this receiver, it is necessary to measure the absolute value of the received electric field strength at the input end of the antenna 2 in order to set the gain of the analog signal processing unit 2 to an optimum value. In the receiver provided with the quadrature demodulator shown in FIGS. 13 and 14, the signal voltage input to the A / D converter 3 can be calculated by the reception electric field strength detection circuit 57 by digital operation. This calculation can be easily realized, for example, by taking the root of the sum of squares of each IQ channel.
[0107]
Therefore, the signal voltage level (P _AD ) (ST29 in FIG. 20), and subtracting the total gain of the analog signal processing unit 2 from this value to obtain the received electric field strength (P _RF ) Can be calculated. That is, the gain (R) of the RF amplifier 11, the gain (M) of the mixer 16, and the gain (B) of the baseband section such as the LPF 22 and the amplifier 26 may be subtracted from the PAD (ST30). The gain of each circuit of the analog signal processing unit 10 is sequentially updated for each of the reception time slots 67 and 68 assigned to the own terminal shown in FIG. 17, but the value of the gain set for each circuit is changed each time. It may be stored in a memory or the like.
[0108]
Next, a receiving operation procedure at the time of a telephone call of the receiver to which the above-described DC offset detection, reception mode selection, and reception electric field strength measurement are applied will be described. The receiving procedure is particularly perforated when the receiver is applied to a TDMA or TDD system. Therefore, first, a frame configuration of a system premised on the present reception operation procedure will be described. FIG. 21 is a diagram showing a frame configuration in a TDMA or TDD system. In FIG. 21, T is one frame length, and 67 and 68 are reception time slots allocated to the own terminal.
[0109]
When the time slot 68 is received, the reception mode is set before the reception of the slot 68 based on the reception electric field strength detected in the time slot 67 of the immediately preceding frame. That is, the receiving field strength of the subsequent 68 is predicted from the receiving field strength obtained in the slot 67, and the receiving mode of the analog signal processing unit 10 is set. This is because if the fading period FT determined by the fluctuation of the reception electric field strength 70 during fading in FIG. 21 is sufficiently longer than the one frame length T, the reception electric field strength of the reception slot 67 of the preceding frame is used to calculate the reception slot of the subsequent frame. This is based on the fact that the received electric field strength of E.68 can be predicted to some extent.
[0110]
Next, the receiving operation procedure will be described in detail with reference to FIG. FIG. 22 is a flowchart showing a basic receiving operation procedure of the receiver during a call. Here, the reception of the reception time slot in FIG. 21 is considered. After turning on the power (ST31), the receiver performs the DC offset measurement (FIG. 18) and the gain setting of the analog signal processing unit 10 (FIG. 19) in the initial setting (ST32), and enters a receivable state. Thereafter, in reception slot 67 (ST33), reception electric field strength P _RF Is measured (ST34). A reception mode for receiving the subsequent 68 is set from the reception electric field strength of the reception slot 67, and a DC offset correction value corresponding to the reception mode is read from the DC offset holding means 43 and 44 and set. Then, the subsequent (ST36) desired slot 68 is received (ST37). In the seventh embodiment, it is assumed that the reception electric field strength is substantially constant during one slot 68, and the set reception mode is fixed during reception of the slot 68.
[0111]
The DC offset generated in each circuit of the analog signal processing unit 10 slightly fluctuates with the passage of time due to the temperature characteristics of the circuit, even in the same pure mode. In this case, it is necessary to detect the DC offset in a time zone other than the initial setting (ST32) immediately after the power is turned on (ST31) and update the contents of the DC offset holding means 43. The time for detecting the DC offset other than when the power is turned on needs to be a time zone other than the desired reception slot. For example, the DC offset may be detected at a time other than the reception of the desired slot in the battery saving mode at a predetermined time or every predetermined frame.
[0112]
Next, the timing relationship between the gain control signal sent from the digital signal processing circuit 40 to the analog signal processing unit 10 and the DC offset control signal will be described with reference to FIG. In FIG. 17, reference numeral 71 denotes a gain control signal for setting a reception mode of the analog signal processing unit 10, and 72 denotes a control signal for correcting a DC offset. In the reception slot 67, the signal is received in the reception mode corresponding to the control signal value 73, and the DC offset control corresponding to the reception mode is performed by the control signal 75. In the reception slot 68, the reception is performed in the reception mode corresponding to the control signal value 75, and the DC offset control corresponding to the reception mode is performed by the control signal. In this receiver, the reception mode is determined based on the reception electric field strength measured in the preceding reception slot 67. Therefore, the gain control signal 71 for setting the reception mode switches from the control signal value 73 in the reception slot 67 to the control signal value 74 at the timing t2 before the subsequent reception slot 68. Here, t2 may be any time before the reception slot start time t3. On the other hand, the DC offset control signal 72 for performing the DC offset correction in the analog signal processing unit 10 also switches from 75 to 76. This switching timing t1 'may be basically before the subsequent reception slot 68 start time t3. Therefore, unless a circuit failure occurs in the analog signal processing unit 10 due to the switching of the control signal 72 to 75 or 76, the switching is performed at either t1 or t1 'regardless of the gain switching timing t2 of the gain control signal 71. May be.
[0113]
The reception operation procedure described with reference to FIG. 22 is a method of setting the reception mode of the subsequent reception slot based on the reception electric field strength of the preceding reception slot 67 of the reception frame of FIG. However, more practically, it is desirable that the reception mode for receiving the slot 68 be determined and set according to the reception electric field strength at the time of reception of the desired reception slot 68. Hereinafter, this method will be described. First, a general configuration of the reception slot 68 is shown in FIG. Here, slot 68 is a desired reception slot, 77 and 78 are adjacent slots, and 80 and 81 are guard times. The slot 76 includes a start symbol 82, a preamble 83, a unique word 84, an information part 85, and the like. Here, for example, if the reception electric field strength can be measured in the preamble 83 section, it is possible to set a more appropriate reception mode for receiving the information portion 85 in this slot based on the information.
[0114]
Hereinafter, an operation procedure for measuring the reception electric field strength in the desired reception slot 68, performing the reception mode setting / DC offset correction, and receiving the information portion 85 will be described with reference to FIG. In FIG. 24, the operations of turning on the power (ST41) and initial setting (ST42) are the same as those described in FIG. Unlike the case of FIG. 22, n = 1 described in ST43 indicates that the desired reception slot 67 has already been received at the present time. At this time, the reception mode of the analog signal processing unit 10 is the reception mode set in the initial setting (ST42), and the DC offset correction corresponding to this reception mode is performed (ST44). Then, the reception electric field strength P in the currently received reception slot is determined using the head of the reception slot 67 (for example, the preamble 83 in FIG. 23). _RF 'Is measured (ST85). And this P _RF ′, An optimum reception mode is set, and a DC offset correction value corresponding to the reception mode is read from the DC offset holding units 43 and 44 and set (ST46).
Thereafter, the reception slots after the preamble 83 are received (ST47). From the subsequent frame (n ≧ 2: ST49), the initial value of the reception mode set by the reception electric field strength measurement (ST45) is set to the reception mode used when the previous frame (n = 1) is received. It is effective to set it. For example, when the reception is performed in the reception mode B of FIG. 16 with n = 1, the reception mode B may be used as an initial value of the reception electric field strength measurement (ST45) with n = 2. Alternatively, from the viewpoint of avoiding the saturation of the A / D converter 3 at the time of the reception electric field strength measurement (ST45) at n = 2, the reception mode which is one rank lower than n = 1 and has less gain is set as the initial value. Is also good.
[0115]
According to the above-described reception operation procedure, even if a DC offset occurs in the analog signal processing unit 10 instead of the receiver of the present invention, it is possible to realize good reception performance without being affected by the DC offset.
[0116]
Here, the configuration and operation of the first offset correction means of the analog signal processing unit 10 shown in FIGS. 13 and 14 will be described with reference to FIGS. 14 and 25. A receiver that performs this operation is particularly effective when performing reception while performing DC offset correction in a reception slot. FIG. 25 is a diagram showing that the DC component generated at the output of the mixer 16 is affected by the time constants of the LPFs 22 and 23. FIG. 25A is a diagram showing the timing of the gain switching control signal 58 in FIG. 14, and the switching of the gain for each circuit of the analog signal processing unit 10 is performed at time t ′. FIG. 25B is a diagram illustrating a change in the DC component of the mixer output (LPF input), and a DC offset fluctuation 86 occurs as the gain of the analog signal processing unit 10 changes at time t.
[0117]
The DC offset fluctuation 86 corresponds to, for example, a difference between DCHIGH in FIG. 61B and DCLOW in FIG. At this point, it is assumed that DC offset correction has not been performed yet. FIG. 25C illustrates the output of the LPF 22 when FIG. 25B is input. Here, a response 87 occurs due to the time constant of the LPF, and a delay of 89 occurs before the output stabilizes. FIG. 25D shows the inverse characteristic of the DC offset 86. FIG. 25 (e) is a signal obtained by correcting FIG. 25 (c) showing the output of the LPF 22 with the signal of FIG. 25 (d). That is, in the section of the delay 89 caused by the influence of the time constant of the LPF 22, the DC offset correction output becomes like 88, and accurate correction cannot be realized.
[0118]
In order to solve this, DC offset correction may be performed before the LPF 22. According to this method, as shown in FIG. 25 (f), the output of the DC offset correction circuit can realize complete DC offset correction without being affected by the delay 89. As described above, in the present receiver, in order to prevent the influence of the time constant of the LPFs 22 and 23, the first offset correction means is preferably provided at least in the preceding stage of the LPFs 22 and 23 (20 in FIGS. 13 and 14). , 21). The same applies to the above-described reception procedure in FIG. 22, that is, the case where the DC offset correction is performed in a section other than the desired reception slot. That is, it is preferable that the first offset correction means be set at least in the preceding stage of the LPFs 22 and 23 so as to minimize the influence of the time constant of the LPFs 22 and 23.
[0119]
As described above, in FIGS. 13 and 14, the configuration in the case where the DC offset is corrected only by the analog signal processing unit 10 has been described. However, it is clear that the present invention is effective not only in the seventh embodiment but also in a receiver configured to correct the DC offset by the digital signal processing circuit 40. That is, FIG. 26 is a receiver according to the eighth embodiment in which the second DC offset correction means 45 and 46 are provided in the digital signal processing circuit 40 in FIG. 13, and the operation of this portion will be described with reference to FIG. This is the same as the second embodiment described.
[0120]
Further, as in the ninth embodiment shown in FIG. 27, a method is also conceivable in which the amount of DC offset to be corrected is distributed to the analog signal processing unit 10 and the digital signal processing circuit 40. That is, a configuration may be adopted in which the DC offset distribution units 51 and 52 are added. This can also be easily realized by adopting a configuration similar to that of the third embodiment shown in FIG. As for the reception procedure, all the procedures of the detection, setting, and correction of the DC offset correction value described above may be performed not only for the analog value but also for the digital value.
[0121]
With reference to FIG. 28, a description will be given of a receiving operation procedure for receiving while distributing DC offset correction to a digital system and an analog system. Here, it is assumed that the reception slot shown in FIG. 21 is received. After the power is turned on (ST50), the receiver performs DC offset measurement (FIG. 18) and sets the gain of the analog signal processing unit 10 (FIG. 19) in the initial setting (ST51), and enters a receivable state. In the DC offset measurement, a DC offset component to be corrected by the analog signal processing unit 2 and the digital signal processing circuit 40 is distributed from the measured DC offset. The configuration of this part is the same as that of the third embodiment shown in FIG. Thereafter, in the reception slot 67 (ST52), the reception electric field strength P _RF Is measured (ST53). The reception mode for receiving the subsequent 68 is determined and set from the reception electric field strength of the reception slot 67. At the same time, the DC offset correction value corresponding to the reception mode is read from the DC offset holding units 43 and 44, and is set for the analog signal processing unit 10 and the DC offset correction unit of the digital signal processing circuit 40, respectively (ST54). Steps ST55 to ST58 will be described later. Then, the subsequent desired slot 68 is received (ST59) (ST60). In the present embodiment, it is assumed that the reception electric field strength is substantially constant during one slot 68, and the set reception mode is fixed during reception of the slot 68.
[0122]
As described with reference to FIG. 22, the DC offset generated in each circuit of the analog signal processing unit 10 slightly fluctuates with the passage of time due to the temperature characteristics of the circuit even in the same reception mode. Therefore, it is necessary to sequentially detect the DC offset and update the contents of the DC offset holding means 43. At this time, the DC offset can be corrected by the analog signal processing unit 10 or corrected by the digital signal processing circuit 40, so that it is possible to respond more flexibly if the method of updating is sequentially updated. Steps ST55 to ST58 in FIG. 28 are procedures for realizing this content.
[0123]
First, in ST55, the receiving operation is performed in the set receiving mode and the DC offset correction in the analog signal processing unit 10 and the digital signal processing circuit 40 to detect the DC offset. When the DC offset correction amount in the digital signal processing circuit 40 exceeds a predetermined value and it is determined that the analog signal processing unit 10 should correct the DC offset (ST56), the DC offset in the analog signal processing unit 10 is determined. Change the offset correction amount. The change in the DC offset correction amount performed by the analog signal processing unit 10 is realized by, for example, updating the DC offset correction value table in the rightmost column of FIG. 16 (ST58). When this table is updated, the correction amount of the digital signal processing circuit 40 in consideration of the correction amount of the analog signal processing unit 10 is calculated and set again (ST57). If it is determined in step ST56 that the DC offset correction amount of the analog signal processing unit 10 does not need to be changed, the DC offset correction value of only the digital signal processing circuit 40 is updated (ST57).
[0124]
Here, since the analog signal processing unit 10 performs the DC offset correction for each reception mode, the DC offset amount corrected by the digital signal processing circuit 40 is smaller than the DC offset amount corrected by the analog signal processing unit 10. Do it. Therefore, the DC offset correction amount performed by the digital signal processing circuit 40 does not need to be tabulated in correspondence with each reception mode of the analog signal processing unit 10.
[0125]
The detection of the DC offset and the reassignment of the DC offset to the analog signal processing unit 10 and the digital signal processing circuit 40 shown in ST55 to ST58 in this procedure do not usually need to be performed for each frame, and are performed once every several frames. What should be done is the number of times.
[0126]
Regarding the receivers according to the eighth and ninth embodiments described above, it is clear that the present invention can be effectively applied to the direct conversion receiver without the frequency converter 12 in FIGS.
[0127]
Hereinafter, the operation of the receiver having the DC offset removal function according to the tenth embodiment at the time of burst capture will be described in detail with reference to the drawings. The received signal input to the receiver of the tenth embodiment is a burst signal shown in FIG. In the case of TDMA communication, this burst signal is received at a predetermined cycle. When this cycle is sufficiently earlier than the fading cycle, the gain setting of the receiver, that is, the selection of the reception mode can be performed using the information of the previous burst (part of the seventh embodiment).
[0128]
On the other hand, even if synchronization with the base station is established, if the fading period is shorter than the burst period, there is no correlation between the received electric field intensity of the previous burst and the received electric field intensity of the current burst. Therefore, it is necessary to capture and receive an incoming signal in a state where the reception mode cannot be set using the information of the previous burst. This corresponds to a so-called “burst reception at the time of synchronization” when a control signal is received during battery saving (hereinafter, BS). Also, when performing initial connection with the base station, it is necessary to first turn on the power of the terminal, perform so-called “asynchronous continuous reception”, and capture a control signal transmitted from the base station. In this case, synchronization with the base station is not established, and it is not known at which time a signal arrives from the base station. That is, it is necessary to receive an incoming signal from a base station that suddenly appears from a no-signal section.
[0129]
The tenth embodiment solves this problem and removes a DC offset for determining a reception mode within one arriving burst and demodulating received information even for a burst arriving signal from a no-signal section. Provide a receiver with a function. Hereinafter, a tenth embodiment in which the receiving operation procedure shown in FIGS. 29 to 32 is applied to the receiver having the configuration shown in FIG. 14 will be described. For simplicity, DC offset correction has been described to be performed only by the analog signal processing unit 10, but the DC offset correction in the digital signal processing circuit 40 can be effectively applied in the same manner as described above. It is possible.
[0130]
FIG. 29 is a diagram showing an operation procedure of a control unit (not shown) for controlling the reception mode and DC offset in the digital signal processing circuit 40 of the receiver. Here, it is assumed that the reception mode shown in FIG. 16 is set for the receiver in FIG. This procedure ends in the section of the preamble 83 shown in FIG. 23, and aims to receive information after the unique word 84 after the reception mode is set.
[0131]
The control unit performs the receiving operation according to the following procedure. After the power is turned on (ST62), first, the DC offset is measured for all the reception modes and stored in the DC offset holding units 43 and 44 (ST63). This procedure is as shown in FIG. Then, the receiving frequency is set to the control channel through which the control signal is transmitted from the base station (ST64), and the gain of the analog signal processing unit 10 is set to the maximum value (ST65). In the reception mode of FIG. Next, a counter for measuring time is reset (t = 0) (ST66). The CD offset correction value (A in FIG. 16) corresponding to the CDW and the current reception mode (mode A) is read from the DC offset holding means 43 and 44 and set (ST67). In this state, continuous reception is performed (ST68), and the arrival of a control signal transmitted from the base station is waited.
[0132]
When the overflow of the A / D converter is detected (ST69), it means that the signal has arrived. The overflow is detected when the maximum value digital data output from the A / D converter appears. Alternatively, the A / D converter may be provided with an overflow detection function, and the overflow may be performed when the flag is set. When an overflow occurs, the gain of the analog signal processing unit 10 is reduced (ST72).
[0133]
For example, if the mode is to be lowered by one in FIG. When the mode changes, a delay occurs before the signal reaches the control circuit of the digital signal processing circuit 40 due to a control delay or a delay due to a response of the analog signal processing unit 10. In this delay section, the amplitude intensity of the signal whose gain has dropped cannot be measured accurately. Therefore, the delay time is calculated in advance, and overflow detection is stopped in the delay time (t1) section (ST74). Alternatively, the overflow detection may be ignored by the control circuit. Thereafter, the time counter is reset again (t = 0), and overflow detection is started. Thereafter, this operation is repeated with a resolution of Δt determined by the clock speed supplied to the digital signal processing circuit 40 (ST70). Then, when no overflow is detected in a predetermined time interval (t = t0), an optimal reception mode is selected, and it is assumed that the reception signal is within the dynamic range of the D / A converter 5. to decide.
[0134]
The above receiving operation procedure ends during the period of the preamble 83 in FIG. 23, and thereafter, the subsequent unique word 84 is received in this receiving mode (ST75). If the unique word (UW) can be detected (ST76), since the control signal is transmitted from the base station to the own station, the subsequent information portion 85 is received. Enter (ST77). If a unique word cannot be detected, it is determined that an overflow has occurred due to some interference wave or the like, and the process returns to the initial reception state (ST65).
[0135]
In a state in which an overflow occurs (ST69) and the gain is lowered (ST72) and the overflow still occurs even when all the reception modes are used (ST73), the received electric field strength is very high, and the dynamic range of the receiver is reduced. The state has been exceeded. In the example of FIG. 16, an overflow occurs even when the mode is set to mode D (lowest gain). In this state, since it is impossible to receive an incoming signal, it is possible to immediately return to the initial reception state (ST65). However, after receiving subsequent information with the current gain, return to the initial state from (ST75). Is also good.
[0136]
FIG. 30 is a diagram showing different operation procedures of a control unit (not shown) for controlling the reception mode and the DC offset in the digital signal processing circuit 40 of the receiver according to the eleventh embodiment. The eleventh embodiment is basically the same as FIG. 29, and is a method of receiving signals while sequentially decreasing the gain from the maximum gain. However, the difference from FIG. 29 is that steps ST78 to ST83 in which the A / D converter 3 does not cause an overflow even when the analog signal processing unit 10 has the maximum gain are inserted.
[0137]
This procedure is effective when a very multi-bit A / D converter is used for the D / A converter 5. That is, when the dynamic range of the A / D converter is large and the signal level is small, overflow does not occur even when the analog signal processing unit 10 has the maximum gain. In FIG. 30, steps up to step ST65 are the same as those in FIG. 29, and the reception mode is set to the maximum gain. Thereafter, the counter for measuring the time is reset (t = 0) (ST78), and the DC offset correction value corresponding to the current reception mode is read from the DC offset holding means 43 and 44 and set (ST79). . In this state, continuous reception is performed (ST80), and a control signal transmitted from the base station is received.
[0138]
In step ST81, a predetermined bit of the A / D converter 3 is detected, or an overflow is detected. First, by detecting a predetermined bit of the output of the A / D converter 3, it is determined whether or not the input signal is at or above a predetermined level. If the level is equal to or higher than the predetermined level, it is determined that the signal has arrived, and the procedure goes to step ST75 with the maximum gain to perform the receiving operation. In addition, even if an overflow of the A / D converter 3 is detected at the time of the procedure ST81, it is determined that the signal has arrived, and the same reception operation procedure as that of FIG. 29 is performed after the procedure ST72. If the signal level does not exceed the predetermined level in step ST81, it is determined that no signal has arrived. In FIG. 30 described above, steps ST78 to ST83 are inserted in FIG.
[0139]
FIG. 31 is a diagram showing an operation procedure of a control unit (not shown) for controlling the reception mode and the DC offset in the digital signal processing circuit 40 of the receiver according to the twelfth embodiment. In the tenth and eleventh embodiments of FIGS. 29 and 30, the optimum reception mode is selected by setting the gain of the analog signal processing unit 10 to the maximum value and sequentially decreasing the gain. Conversely, in the twelfth embodiment (FIG. 30), the optimum reception mode is operated by setting the gain of the analog signal processing unit 10 to the lowest value and sequentially increasing the gain. In FIG. 31, steps ST62, ST63, and ST64 are the same as those in FIG. Next, the gain of the analog signal processing unit 10 is set to the lowest value (ST85). This corresponds to mode D in the reception mode in FIG.
[0140]
Next, the counter for measuring the time is reset (ST66), and the DC offset correction value (D in FIG. 16) corresponding to the current reception mode (mode D) is set (ST67). In this state, continuous reception is performed (ST68), and a control signal transmitted from the base station is received. Here, it is determined whether a predetermined bit of the output of the A / D converter 3 has been set (ST86). This means that it is determined whether or not the signal level input to the A / D converter 3 is equal to or higher than a predetermined level. This determination is repeated with a resolution of Δt in a predetermined time section (t = t0) (ST70, ST71). When it is determined that the signal level input to the A / D converter 3 is insufficient, it is necessary to increase the gain of the analog signal processing unit 2 (ST87). In the example of FIG. 16, the reception mode D is shifted to C to increase the gain. After increasing the gain, the level detection is stopped only for the delay t1 section in consideration of the control delay and the response of the analog signal processing unit 10 as in the case of FIG. 29 (ST88). Thereafter, the time counter is reset again (t = 0), and the level detection is started. If it is determined in step ST86 that a sufficient signal level has been input to the A / D converter 3, it is determined that the optimum gain has been set in the analog signal processing unit 10.
[0141]
The procedure so far ends during the period of the preamble 83 in FIG. 23, and the subsequent unique word 84 is received in the reception mode determined here (ST75). If the unique word (UW) can be detected (ST76), since the control signal is transmitted from the base station to the own station, the subsequent information portion 85 is received. Enter (ST77). If a unique word cannot be detected, it is determined that no signal has arrived, and the process returns to the initial reception state (ST85).
[0142]
In step ST87, when the gain of the analog signal processing unit 10 is increased and the signal level is not sufficient even when all the reception modes are used (ST73), the received electric field strength is very weak and the noise level of the receiver is reduced. It is considered that the desired wave is buried. In this state, since it is impossible to receive an incoming signal, it may be returned to the initial reception state (ST85) immediately. However, after receiving the subsequent information with the current gain, the operation returns to the initial state from (ST75). Is also good.
[0143]
FIG. 32 shows an operation procedure of a control unit (not shown) for controlling the reception mode and the DC offset in the digital signal processing circuit 40 of the receiver according to the thirteenth embodiment. In FIG. 32, up to the procedure ST63 is the same as FIG. In the following procedure, the receiving mode is set to the initial mode, specifically, the receiving mode one level higher than the lowest gain (one step higher in gain). The example of FIG. 16 corresponds to mode C. Next, the counter for measuring the time is reset (ST65). The DC offset correction value (C in FIG. 16) corresponding to the current reception mode (mode C) is read from the DC offset holding units 43 and 44 and set (ST67). In this state, a control signal transmitted from the base station that performs continuous reception (ST68) is received.
[0144]
Here, when overflow of the A / D converter is detected (ST69), the reception mode is reduced by one (gain is reduced by one step) (ST91). That is, at this time, the gain is the lowest (reception mode D in FIG. 16). Then, the preamble and the preamble are received in the reception mode as they are (ST75). This is because, in the initial stage (ST90), the receiving mode is set to one level higher than the lowest gain (one step higher in gain), and if overflow occurs, there is no other way than to receive at the lowest gain. Conversely, if no overflow is detected in a predetermined time interval (t = t0), it is determined that the gain of the radio unit is insufficient, and the gain of the analog signal processing unit 10 is increased (ST87). . In the example of FIG. 16, the gain is increased by shifting the reception mode from C to B. After increasing the gain, the overflow detection is stopped only for the delay t1 section in consideration of the control delay and the response of the analog signal processing unit 10 as in the case of FIG. 29 (ST74).
[0145]
Thereafter, the time counter is reset again (t = 0) to start overflow detection, and thereafter, this operation is performed until an overflow occurs at a resolution of Δt determined by the clock speed supplied to the digital signal processing circuit 40. Repeat (ST70). If an overflow has occurred, the mode is returned to the previous mode, that is, the gain is reduced by one step to the receiving mode (ST91), and the receiving operation after the preamble is performed (ST75). In the receiving operation procedure in the thirteenth embodiment, since the gain is sequentially increased from the receiving mode having a small gain, if an overflow occurs, the previous receiving mode can be regarded as the optimal receiving mode. Is the feature.
[0146]
In step ST87, the state in which no overflow occurs even when all the reception modes are used (ST73) is considered to be a state in which the reception electric field strength is extremely weak and the desired wave is buried in the noise level of the receiver. In this state, since it is impossible to receive an incoming signal, it is possible to return to the initial reception response (ST85) immediately. However, after receiving the subsequent information with the current gain, return to the initial state from (ST75). Is also good.
[0147]
Here, the reception operation procedures shown in FIGS. 29 to 32 will be compared. First, the time required until the reception mode is set will be compared. In FIGS. 31 and 32, the reception operation is performed while switching from a small gain to a large gain, so that the LPF 22 is less affected by the transient response due to the time constant. That is, even if there is an excessive response of the signal before the gain switching, since the subsequent signal level is higher, it is unlikely that this level is erroneously detected.
[0148]
This will be described with reference to FIG. FIG. 33A shows the output of the LPF 22 when switching from high gain to low gain. FIG. 33B shows the output of the LPF 22 when switching from low gain to high gain. In the case of FIG. 33A, when the gain is switched from the high gain to the low gain at time t ′, the signal level changes from 91 to 92. However, due to the influence of the time constant of the LPF, the signal 91 remains 93 after the gain switching (t ′) and is superimposed on the desired signal 92. Although the signal is attenuated by the time constant of the LPF of the signal 93, the level of the desired signal 92 cannot be accurately determined due to the influence of the signal 93 in the section indicated by 97 after the switching. Therefore, in order to determine the level of the desired signal 92, it is necessary to have the level up to the time indicated by 97. That is, a detection ignoring section is required, and a delay of 97 occurs in level determination of the desired signal 92.
[0149]
On the other hand, FIG. 33B shows a case where the gain is changed from a low gain to a high gain. In FIG. 33B, when the gain is switched from low to high at time t ′, the signal level changes from 94 to 95. As in the case of FIG. 33A, the signal 94 remains 96 after the gain switching (t ') due to the influence of the time constant of the LPF, and is superimposed on the desired signal. However, since the predetermined signal 95 has been switched to a high gain, the signal level is higher than that of the signal 96 to be superimposed, and the influence on the level determination is small. Therefore, in FIG. 33 (b), the level of desired signal 96 can be determined immediately after time t '. As described above, when the determination is made by switching from the low gain to the high gain, the detection ignoring section can be shortened. As described above, in the methods of FIGS. 31 and 32, the delay of “detection ignored section: t1” (ST74, ST88) required in each method can be shortened. Therefore, the reception mode can be set at a high speed.
[0150]
On the other hand, in the “method of switching from high gain to low gain” of the reception operation procedure in FIGS. 29 and 39, the detection ignoring section needs to be longer than in FIGS. 31 and 32 as described above.
[0151]
Next, the suitability in the receiving mode will be compared. This reception operation procedure is required in the “asynchronous continuous reception” mode when the terminal is powered on and the initial connection with the base station is performed. The reception operation procedure shown in FIGS. 29 and 30 is effective for both “asynchronous continuous reception” when performing initial connection with the base station by turning on the terminal power supply and “synchronous burst reception” during BS. It is. In particular, even when it is not clear when a signal arrives at the time of “asynchronous continuous reception” immediately after the terminal is turned on, since the signal waits at the maximum gain, the arrival of the signal can be determined by overflow detection.
[0152]
On the other hand, it is difficult to detect a burst arriving signal in a no-signal section in the reception operation procedure shown in FIGS. 31 and 32. This is because it is difficult to determine the presence or absence of an incoming signal in a state where it is unknown whether the signal has arrived (asynchronous state immediately after power-on). Therefore, the receiving operation procedure shown in FIGS. 31 and 32 is more suitable for "burst reception at the time of synchronization" than for "asynchronous continuous reception".
[0153]
As described above, each operation procedure has a feature. That is, the procedures in FIGS. 29 and 30 are suitable for “asynchronous continuous reception”, and the procedures in FIGS. 31 and 32 require only a short time to determine the reception mode, and are suitable for “burst reception during synchronization”. It is effective for Therefore, at the time of “asynchronous continuous reception” at the time of terminal power ON, one of the reception operation procedures of FIGS. 29 and 30 is used, and at the time of “burst reception at the time of synchronization”, one of FIGS. 31 and 32 is used. It is effective to use an appropriate combination as necessary, such as using the receiving operation procedure described above. For example, after the power is turned on (ST61) in FIGS. 31 and 32, the reception operation procedure shown in FIGS. 29 and 30, ie, the procedure of “burst reception at the time of synchronization” is inserted. Then, in the BS state after the synchronization is once established, burst acquisition may be performed using the method shown in FIGS.
[0154]
Next, receivers according to fourteenth to sixteenth embodiments of the present invention will be described with reference to FIGS. When performing DC offset detection, if a signal wave having a DC component other than the DC offset component to be detected is received, the DC offset cannot be accurately detected. Therefore, if a radio wave used in another wireless communication system is received from the antenna 2 in particular, there is a possibility that the DC offset cannot be accurately detected due to the influence of the incoming wave.
[0155]
In order to prevent this effect, the present receiver is characterized in that it includes means for preventing a signal from being received from an antenna when detecting a DC offset component, that is, means for turning off a received signal. Several embodiments of the method will be described with reference to the drawings.
[0156]
FIG. 34A is a view for explaining a fourteenth embodiment of the present invention. Here, a switch 4a is provided to cut off a signal received by the antenna 2 from off. The switch 4a turns off the signal path from the antenna 2 when performing the DC offset detection. Then, it is connected to the terminating resistor 4b set to the same value as the input impedance of the antenna 2. This operation prevents the incoming signal received by the antenna 2 from being sent to the analog signal processing unit 10 and the digital signal processing unit 40. Further, the input of the RF amplifier 11 is terminated by the terminating resistor 4b, that is, the input impedance of the antenna 2. This is to prevent a change in the DC offset output due to the value of the input impedance of the RF amplifier between the detection of the DC offset and the reception of the desired signal.
[0157]
The switch 4a in FIG. 34A can be easily configured by MOS switches, SW1 and SW2 as shown in FIG. The operation modes of SW1 and SW2 at this time are shown in FIG. That is, control is performed such that SW1 is turned on and SW2 is turned off during normal reception, and SW1 is turned off and SW2 is turned on when DC offset is detected. A control signal is sent from the digital signal processing unit to the gates of SW1 and SW2 in accordance with the state of the presence or absence of the DC offset detection, and the ON / OFF operation is performed.
[0158]
In principle, the switch 4a may be provided before the DC offset is detected. Generally, it is desirable to be before the block that provides the gain, and it is desirable to be before the RF amplifier 12.
[0159]
Next, a receiver according to a fifteenth embodiment as another configuration for turning off the reception signal will be described. FIG. 36 shows an example in which an attenuator 90 is connected in parallel with the RF amplifier 11. The input impedance of the attenuator 90 is set to the same value as the input impedance of the antenna 2 and the RF amplifier 11, for example, 50Ω. This attenuator 90 is used in place of the RF amplifier 11 when a strong electric field is input, and serves to prevent the receiver from being saturated. That is, the RF amplifier 11 is used when receiving a signal at a normal level, and the attenuator 90 is used when the received signal level is higher than a predetermined value. FIG. 37 shows the operation modes of the MOS switches SW1 to SW7 in FIG. 36 at this time. That is, when receiving the normal level, SW3 and SW6 are turned on, SW4 and SW7 are turned off, and the RF amplifier 11 operates. On the other hand, when the received signal level is higher than the predetermined value, the attenuator mode is set, SW3 and SW6 are turned off, SW4 and SW7 are turned on, and the attenuator 90 operates.
[0160]
Further, this configuration is characterized in that SW5 is provided. When DC offset is detected, SW5 and SW6 are turned on, and SW3, SW4, and SW7 are turned off. In this state, the signal input from the antenna 2 is turned off, and the RF amplifier 11 is terminated with the same value as the input impedance of the attenuator 90, that is, the input impedance of the antenna 2. By doing so, it is possible to set so that the DC offset output does not change due to the value of the input impedance of the RF amplifier 11 between when the DC offset is detected and when the desired signal is received.
[0161]
By employing the above method, even if any radio wave is received from the antenna 2 at the time of detecting the DC offset, the DC offset can be satisfactorily detected without being affected by the arriving wave.
[0162]
In the fourteenth and fifteenth embodiments, the case where the DC offset component is buried in other signal components and cannot be detected has been described. However, when the level of the arriving wave received from the antenna is small and it can be considered that there is no arriving wave, it may not affect the DC offset detection. For such a case, a means for detecting the received signal strength (RSSI: received electric field strength detector) is provided, and when the received signal strength of the incoming wave becomes smaller than a predetermined value, DC offset detection is performed. You may do it.
[0163]
FIG. 38 is a diagram for explaining a sixteenth embodiment relating to the above method. FIG. 38 shows only one of the IQ channels. Here, the output of the A / D converter 3 is input to the RSSI detection means 98, and the input voltage of the arriving wave received by the antenna 2 to the digital signal processing unit 40 is detected. When the detected value is smaller than the predetermined value, the receiver performs the DC offset detection operation on the assumption that the DC offset detection is not affected. Specifically, if the detected value is lower than the DC offset value allowed by the demodulator 50 in the digital signal processing circuit 40 by about 10 dB, the DC offset detection is not affected. As a result of the RSSI detection, when it is determined that the received electric field strength of the arriving wave received from the antenna 2 is low and there is no arriving wave, the control signal 99 is transmitted to the DC offset detecting means 41 to perform the DC offset detection. Execute. The control signal 99 may be sent from the detection / demodulation means 50.
[0164]
The DC offset detecting means 41 (or 42) in FIG. 1 can be configured as shown in FIG. In the figure, 411 is an accumulative addition circuit, and 412 is a division circuit. Next, the operation of the receiver according to the seventeenth embodiment of the present invention will be described.
[0165]
The output signal of the A / D converter 3 is a signal obtained by frequency-converting an input signal from the antenna 2 to a baseband and further converting the signal into a digital signal. This signal is input to the accumulation circuit 411. The signal input to the accumulation circuit 411 is a modulated signal on which a DC offset is superimposed.
[0166]
The accumulation circuit 411 adds digital data output from the A / D converter 3 for each sample. By cumulatively adding the input signals in this manner, only the DC offset component included in the output signal of the A / D converter 3 is added. This is because the average value of the modulated signal other than the DC offset becomes zero when the signal is cumulatively added over a long period.
[0167]
By dividing this signal by the number of data accumulated in the division circuit 412, the absolute value of the DC offset included in the output of the A / D converter 3 can be obtained. By setting the number of data to be accumulated to be a power of 2, the dividing circuit 42 can be realized very easily by bit shift.
[0168]
By configuring the DC offset detection means 41 using the accumulation circuit 411 and the division circuit 412 as described above, it is possible to detect the DC offset value by calculating the time average of the output signal of the A / D converter 3. Can be.
[0169]
If the number of data to be cumulatively added (integration period) is long enough to sufficiently remove the DC component contained in the modulated signal, it can be detected accurately, but there is a time lag before the correction is made. If the period is set to be short, the detection error of the DC offset increases, so it is important to set an appropriate value. According to the seventeenth embodiment, the setting of the integration period can be realized very easily by changing the number of data to be added in the accumulating circuit, and the setting can be easily changed.
[0170]
FIG. 40 is a diagram illustrating a received signal having an offset component. Here, the received signal 404 is a received signal having the received thermal noise and DC offset component, and the original signal 402 is shown for comparison. Here, the deviation of the DC component from the (analog) ground level 405 is the DC offset component 406. The signal is converted to a digital signal for signal processing. FIG. 41 is a diagram for explaining this state. In FIG. 41, T represents one symbol section, 501 represents a received signal waveform, and 503 represents an (analog) ground level. In FIG. 41A, a DC offset is detected by performing five samples (〇) in one symbol section T. That is, this sample point 504 is input to the DC offset detecting means 41 of FIG. 1 and a DC offset is detected by an operation such as accumulation and division (506 is a DC offset component detected in FIG. 41A). Represents). On the other hand, in FIG. 41B, the DC offset 507 is detected by using 10 samples (both Δ and black circles) in one symbol section T.
[0171]
Comparing FIG. 41 (a) and FIG. 41 (b), it is clear that FIG. 41 (b) having more sample points can better approximate the received signal waveform. Therefore, as for the DC offset component, the DC offset component is more accurately detected by the reference numeral 507 in FIG. 41B than by the reference numeral 506 in FIG. 41A. However, when the number of samplings is increased, the signal processing of the digital section is increased by that amount, which causes a problem that the operation time and the current consumption increase. In general, when the C / N of the received signal is good, the influence of the number of sampling points on the reception error rate characteristics and the detected DC offset amount becomes smaller. Therefore, the sampling number can be appropriately changed depending on the C / N state of the received signal, and the DC offset detection with a good reception error rate and desired accuracy can be performed without unnecessarily increasing the operation amount of the digital section. I can do it. Here, in order to grasp the state of C / N, for example, a reception error rate of a known pattern such as a unique word is appropriately observed, and in a receiver performing diversity, how to generate diversity. (The C / N of the received signal is better when the number of diversity switching is smaller).
[0172]
As described above, the DC offset of the output of the A / D converter 3 is cumulatively added and divided by the number of added data, thereby enabling accurate detection of the DC offset. Further, by setting the number of data to be added to a power of two, the division circuit 412 can be realized by a bit shift.
[0173]
A problem in the DC offset correction by the above configuration is a case where the signal component itself has a DC component. Next, a DC offset detection method effective in such a case will be described.
[0174]
FIG. 42 is a diagram showing an embodiment in which a DC offset reference average value correction circuit is added to the DC offset detection means 41 of FIG. Here, the reference average value 63 is a DC component that the modulation signal component originally has. When the modulation signal component has a DC component, if the DC offset correction is performed, even the original DC component is removed. Therefore, when the DC component of the modulation scheme used in the system is known, a reference average value of the DC component is prepared in advance. Then, by subtracting the DC component detected by the DC offset detection means 41 by the subtraction circuit 64, only the DC offset component can be accurately detected. Here, in FIG. 42, this reference average value is subtracted from the output of the DC offset detection means 41. Further, as shown in FIG. 43, a configuration in which the reference average value is subtracted from the output of the A / D converter 3 may be adopted. With the configuration shown in FIG. 43, the DC offset inherent in the signal component before the accumulating circuit 411 included in the DC offset detection means 41 can subtract the reference average value. Therefore, in the configuration of FIG. 43, although the amount of calculation is larger than that of FIG. 42, there is an advantage that the DC component originally included in the signal component can be removed more finely on the time axis. Therefore, when DC offset detection with high accuracy is required, the configuration shown in FIG. 43 is adopted, and the time interval for subtracting the reference average value 63 is set to be short, so that it is possible to flexibly respond.
[0175]
Next, a receiver according to an eighteenth embodiment having the DC offset removing function of the present invention will be described with reference to the drawings. FIG. 44 is a diagram illustrating a TDMA frame format of a TDMA system in which the present receiver is used. Here, 3001, 3002, 3003, and 3004 are allocated to reception slots, and 3005 is a slot other than the reception slots (for example, 3001 and 3002, or 3002 and 3003), and the state of the receiver (temperature change or the like). If the surrounding radio wave environment (fading) does not change, the amount of DC offset generated in these slots is expected to be very close. In this receiver, processing is performed by regarding the DC offset amount detected in each adjacent reception slot as the DC offset amount generated in the subsequent reception slot. As a result, the DC offset can be detected at high speed and more accurately within a limited time, and therefore, the DC offset can be corrected at higher speed.
[0176]
FIG. 45 is a diagram showing a configuration example of a DC offset detecting means for this purpose. In FIG. 45, the DC offset initial value 1301 stores the DC offset value detected in the previous reception slot as the DC offset initial value. In the subtraction circuit 1302, the DC offset initial value 1301 is subtracted from the received signal converted into a digital signal by the A / D converter 3 and sent to the DC offset detection means 41. The DC offset detection means 41 has the above-described configuration, and the detected DC offset value is sent to the DC offset holding means 43 and used for DC offset correction.
[0177]
If the amount of DC offset generated in each adjacent receiving slot of the TDMA system is exactly the same, the DC offset can be completely removed by subtracting the DC offset value (initial value) of the previous receiving slot from the received signal. Even if the DC offset amounts are not exactly the same, the DC offset amounts are considered to be very close values between adjacent reception slots because there is little change in the state of the receiver and the surrounding radio wave environment. Therefore, it is clear that the present configuration allows the DC offset to be detected faster and with a smaller amount of calculation than when the DC offset value of the previous reception slot is not used as the initial value.
[0178]
In FIG. 45, it is clear that the DC offset detecting means 41 may be the DC offset detecting means 62 (or 65) provided with the above-mentioned reference average value correcting means. In each reception slot, the DC offset initial value 1301 may be set in consideration of a DC offset value detected in an earlier reception slot, instead of a DC offset value detected only in the previous slot.
[0179]
In FIG. 45, the subtraction of the DC offset initial value 1301 is performed in the digital section after the A / D converter 3, but may be performed in the preceding stage of the A / D converter 3, that is, in the analog section. FIG. 46 shows an example of a configuration in which the subtraction of the DC offset initial value 1401 is performed by an analog subtraction circuit 1402 provided in a stage preceding the A / D converter 3. As described above, in the configuration in which the DC offset initial value 1401 is subtracted by the analog section, the DC offset initial value is large, and the A / D converter 3 at the subsequent stage may be saturated unless it is subtracted by the analog section in advance. This is particularly effective in certain cases. Here, the DC offset detecting means 41 may be a DC offset detecting means 62 (or 65) including the above-described reference average value correcting means. Alternatively, it may be 1303 shown in FIG. In this case, the DC offset initial value is divided into both digital and analog values and subtracted.
[0180]
Next, a receiver according to a nineteenth embodiment of the present invention will be described. In the above-mentioned samurai history mode, a method is used in which the detected DC offset is subtracted in the next slot. Here, in order to accurately detect the DC offset amount, a longer detection period (integration period) is preferable. However, in order to follow the fluctuation of the DC offset caused by fading or the like, the shorter the integration period, the better. That is, there is a trade-off between the accuracy of DC offset canceling and the ability to follow the fluctuation, and it is necessary to select an appropriate integration period. However, when the amount of change in the DC offset increases or decreases, it is difficult to set a fixed integration period in advance.
[0181]
In order to avoid such a problem, in the nineteenth embodiment, the offset is detected and removed by the following method. That is, a predetermined number of past DC offset detection values of each slot are held, and each DC offset value is weighted and averaged.
[0182]
FIG. 47 shows the configuration of the nineteenth embodiment. In the figure, the A / D converter 3, and the DC offset detecting means 42 composed of the accumulative adding circuit 421 and the dividing circuit 422 are the same as those shown in FIG. Reference numeral 43 denotes a DC offset holding unit, which includes a delay circuit 431, a weighting coefficient circuit 432, an addition circuit 433, and a division circuit 434.
[0183]
The delay circuit 431 holds the value output from the DC offset detection means for one slot and then outputs the value. Therefore, the output of the leftmost delay circuit 431-1 in the figure is the detection value V1 one slot before, the output of the second delay circuit 431-2 from the left is the detection value V2 two slots before, and the rightmost delay circuit. The output of 431-N becomes the detected value Vn N slots before. The weighting coefficient circuit 432 multiplies the input value by a preset weighting coefficient value Wn and outputs the result.
[0184]
The addition circuit 433 calculates the sum of the outputs of the weighting coefficient circuits and outputs the value. The division circuit 434 divides the input value by the sum of the weighting coefficient values and outputs the result. The number a divided by the division circuit 434 is the sum of the weighting coefficient values (W1 + W2 +... + Wn).
[0185]
Next, the operation of the DC offset cancel device in the receiver according to the nineteenth embodiment will be described. The DC offset value detected N slots before is set to Vn, the DC offset value detected before (N-1) slots is set to Vn-1, and the DC offset value detected one slot before is set to V1. These values correspond to the output of the delay circuit 431, respectively.
[0186]
The weighting coefficient for the information before the N slot is Wn, the weighting coefficient for the information before the (N-1) slot is Wn-1,..., And the weighting coefficient for the information before the 1 slot is W1. These values are held in the weighting coefficient circuit 432, respectively. At this time, the output of the division circuit 434 corresponding to the estimated value Ve of the DC offset is as follows.
Ve = (Wn.Vn + Wn-1.Vn-1 + ... + W1.V1) / (Wn + Wn-1 + ... + W1)
The numerator of this equation is the output value of the addition circuit 433, that is, the input value of the division circuit 434, and the denominator is the sum of the weighting coefficient values (W1 + W2 +... + Wn). Therefore, the output value of the division circuit 434 becomes the estimated value Ve of the offset.
[0187]
As described above, by setting appropriate values for Wn to W1, more accurate estimation can be performed using past detection values. However, it is Wn = <Wn-1 = <... <W1.
How to set the weighting coefficient Wn
Method of changing Wn by arithmetic series {FIG. 48 (a)}
Method of changing Wn by geometric series {FIG. 48 (b)}
A method of changing Wn stepwise in a stepwise manner {FIG. 48 (c)}
And so on. The case where Wn is all 1 (or all the same values) corresponds to a method of simply averaging the past N slots. In the nineteenth embodiment, the DC offset can be detected and removed adaptively by using past detected values as needed.
[0188]
For example, as shown in FIG. 49 (a), when the temporal variation of the DC offset is small, it is considered that the past detected value and the actual DC offset value are almost the same, so that all the same weighting coefficients are used. By using this to make the integration period longer, a more accurate estimated value can be obtained and accurate offset removal can be performed.
[0189]
Further, as shown in FIG. 49B, when the temporal variation of the DC offset is large, there is a high possibility that the past detected value and the actual offset value are different, so the coefficient of the past data should be set small. Accordingly, it is possible to perform offset removal with improved time tracking. In the nineteenth embodiment, by using the method described above, it is possible to remove the DC offset with high accuracy while maintaining the ability to follow the fluctuation.
[0190]
Also, as in the twentieth embodiment shown in FIG. 50, in the test mode, for example, a limited wave of a predetermined frequency is generated by the test signal generator 414 by the selection means 413, and the D / A converter 5 and the first DC By monitoring the output of the digital signal processing circuit 40 in addition to the inputs of the LPFs 22 and 23 via the offset correction means 20 and 21, the band limiting characteristics of the analog signal processing circuit can be obtained and used for adjustment. As a result, a D / A converter for converting a digitally generated test signal into an analog signal and a D / A converter for converting a digitally detected DC offset into an analog signal can be used in common. The size can be reduced.
[0191]
For example, as shown in FIG. 51, the specific adjustment is performed by providing the digital signal processing circuit 40 with frequency characteristic control means 415 and 416 and providing the LPFs 22 and 23 with a cutoff frequency adjustment function. For example, the frequency characteristic control means 415 and 416 detect whether the gain of a limited wave having a desired cutoff frequency, which is a test signal passed through the LPFs 22 and 23, is larger or smaller than a desired gain (for example, -3 dB). Then, the comparison signal is output as a control signal to the LPFs 22 and 23 to control the LPFs 22 and 23 to have a desired gain at a desired cutoff frequency. As a result, it is possible to prevent the reception characteristics from deteriorating due to the variation in the cutoff frequency of the LPF when the LSI is used. Adjustment of the cutoff frequency of the LPF may be achieved by switching a resistor, a capacitor, or a current that determines the time constant of the filter.
[0192]
FIG. 52 shows an example of the frequency characteristic control means. The gain of the signal obtained through the LPF is obtained, for example, by calculating the gain at a desired cut-off frequency by the gain calculating means 417 which detects the peak value of the signal, and comparing it with the gain Ref2 by the comparing means 418. Then, the comparison result is fed back to the LPF as a control signal. Adjustment of the cutoff frequency of the LPFs 22 and 23 may be performed after the detection and correction of the DC offset so that the test signal does not have an error in the detection of the distortion gain in the LFP or the A / D converter due to the DC offset. .
[0193]
By using the receiver according to the first to twentieth embodiments described above in a communication system, it is possible to reduce the deterioration of the error rate of a received signal, and particularly to adjust the band limiting characteristic according to the twentieth embodiment. Good communication can be performed by using a receiver that can. The communication system according to the twenty-first embodiment using such a receiver includes a transmitter for transmitting a radio frequency signal composed of an information signal including audio and video, and a transmitter and a receiver for transmitting and receiving the radio frequency signal. Network, a receiving unit for receiving the radio frequency signal, an analog signal processing unit for amplifying, band converting, and frequency converting the analog signal input from the receiving unit, and the analog signal processing unit An analog-to-digital conversion unit for converting the output from the analog signal into a digital signal; a digital signal processing unit for processing the digital signal converted by the analog-to-digital conversion unit; and a reception unit or frequency provided in the digital signal processing unit. An offset detection means for detecting a DC offset signal generated by the conversion unit; and Offset holding means for holding the DC offset signal detected by the offset detecting means, a DA converter for converting the DC offset signal detected by the digital signal processing section into an analog signal, and an analog signal processing section. A first offset correction unit that corrects the analog signal based on the DC offset signal converted to an analog signal by the DA conversion unit, and a receiver having a DC offset removal function. I have.
[0194]
【The invention's effect】
As described above, according to the configuration of the receiver of the present invention, the DC offset is detected using the DC offset detected in the past reception slot as the initial value, thereby realizing the DC offset correction at higher speed and with higher accuracy. be able to.
[0195]
Further, in the present invention, it is possible to reduce a reception error rate due to a DC offset generated when a received signal is processed by an analog signal processing circuit. Also, by using the receiver according to the present invention, it is possible to realize voice and data communication with good quality without deteriorating a reception error rate due to a DC offset generated when a received signal is processed by an analog signal processing circuit. Can be.
[0196]
Further, the receiver having the DC offset removing function according to the present invention has means for storing a DC offset that changes according to a gain set by the analog signal processing unit for each gain. Therefore, there is an effect that the DC offset correction can be realized faster and more accurately by using the stored DC offset value. Furthermore, by the radio unit gain switching function and the method of reading out the stored DC offset value, the dynamic range is not impaired even when the incoming reception level is unknown or when there is a sudden amplitude change in the reception level. This has the effect that the gain of the receiver can be controlled at high speed.
[0197]
Further, the DC offset generated in the analog signal processing circuit at the input of the A / D converter can be reduced, and the reception error rate can be reduced. In addition, it is possible to prevent the signal from being distorted beyond the input range of the A / D converter due to the DC offset, and to prevent a reception error due to the distortion.
[0198]
Further, since the AC couple is not used, there is no influence of the transient response of the time change of the DC offset, so that the reception error rate does not deteriorate. In particular, since it is possible to remove only a DC offset component which is an error with respect to a signal of a modulation method including many low frequency components including DC, it is possible to reduce a deterioration of an error rate of a received signal.
[0199]
Further, a D / A converter that converts a DC offset into an analog signal from a D / A converter required for detecting a frequency characteristic of a band limiting unit in an analog signal processing circuit having characteristics that vary due to an LSI by a test signal is provided. Since they can be shared, the chip area can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a basic configuration of a receiver according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a basic configuration of a receiver according to a second embodiment of the present invention.
FIG. 3 is a block diagram showing a specific configuration of an offset holding unit in FIG. 2;
FIG. 4 is a block diagram showing a basic configuration of a receiver according to a third embodiment of the present invention.
FIG. 5 is a block diagram showing a specific configuration of an offset distribution unit in FIG. 4;
FIG. 6 is a block diagram showing a specific configuration of a comparing unit in FIG. 4;
FIG. 7 is a block diagram showing a basic configuration of a receiver according to a fourth embodiment of the present invention.
FIG. 8 is a flowchart illustrating a first initial value setting method in a receiver according to a fifth embodiment of the present invention.
FIG. 9 is a flowchart illustrating a second initial value setting method in the receiver according to the fifth embodiment of the present invention.
FIG. 10 is a flowchart illustrating a third initial value setting method in the receiver according to the fifth embodiment of the present invention.
FIG. 11 is a flowchart illustrating a fourth initial value setting method in the receiver according to the fifth embodiment of the present invention.
FIG. 12 is a characteristic diagram for explaining how to obtain a threshold value Vth used in the fourth initial value setting method shown in FIG. 11;
FIG. 13 is a block diagram showing a basic configuration of a receiver according to a sixth embodiment of the present invention.
FIG. 14 is a block diagram showing a basic configuration of a receiver according to a seventh embodiment of the present invention.
FIG. 15 is a block diagram showing two specific examples (a) and (b) of a reference average value correction circuit according to the seventh embodiment.
FIG. 16 is a table showing an example of a gain switching mode of the receiver according to the present invention.
FIG. 17 is a conceptual diagram showing a TDMA slot applied to the communication system according to the present invention.
FIG. 18 is a flowchart illustrating an operation procedure for holding an offset correction value.
FIG. 19 is a flowchart showing an operation procedure for setting a reception mode of the receiver.
FIG. 20 is a flowchart showing an operation procedure for measuring a reception electric field strength.
FIG. 21 is a conceptual diagram showing a frame configuration in a TDMA or TDD system.
FIG. 22 is a flowchart showing a basic receiving operation procedure during a call of the receiver.
FIG. 23 is a conceptual diagram showing a general configuration of a reception slot.
FIG. 24 is a flowchart showing a reception operation procedure for simultaneously performing reception mode setting and offset correction.
FIG. 25 is a characteristic diagram illustrating that the DC component is affected by the time constant of the LPF, which has been described with reference to FIGS.
FIG. 26 is a block diagram showing a basic configuration of a receiver according to an eighth embodiment of the present invention.
FIG. 27 is a block diagram showing a basic configuration of a receiver according to a ninth embodiment of the present invention.
FIG. 28 is a flowchart showing an operation procedure of receiving while distributing a DC offset.
FIG. 29 is a flowchart showing an operation procedure of a reception mode / DC offset control unit.
FIG. 30 is a flowchart showing the operation procedure of the control unit of the receiver according to the eleventh embodiment.
FIG. 31 is a flowchart showing the operation procedure of the control unit of the receiver according to the twelfth embodiment.
FIG. 32 is a flowchart showing the operation procedure of the control unit of the receiver according to the thirteenth embodiment.
FIGS. 33 (a) and 33 (b) are characteristic diagrams showing the difference between the gain switching shown in FIGS. 29 and 32, and FIGS.
FIG. 34 is a block diagram showing a configuration of a main part of a receiver according to a fourteenth embodiment, with (a) and (b).
FIG. 35 is a table showing the operation modes of FIG. 34 (b).
FIG. 36 is a block diagram showing a configuration of a main part of a receiver according to a fifth embodiment.
FIG. 37 is a table showing operation modes of the switch in FIG. 36;
FIG. 38 is a block diagram showing a configuration of a main part of the sixteenth embodiment.
FIG. 39 is a block diagram showing a configuration of a DC offset detection unit of the receiver.
FIG. 40 is a waveform characteristic diagram for explaining DC offset.
41A and 41B are characteristic diagrams for explaining that DC offset detection accuracy is improved by making the number of samples variable.
FIG. 42 is a block diagram showing a configuration of a DC offset detection unit in the receiver according to the present invention.
FIG. 43 is a block diagram showing a configuration of a DC offset detection unit in the receiver according to the present invention.
FIG. 44 is a conceptual diagram illustrating the configuration of a TDMA system in which the present receiver is used.
FIG. 45 is a block diagram showing a configuration of a DC offset detection unit of the receiver applied to the TDMA system.
FIG. 46 is a block diagram showing a configuration of a DC offset detector of a receiver applied to a TDMA system.
FIG. 47 is a block diagram showing a main part of a receiver according to a nineteenth embodiment.
48 is a characteristic diagram illustrating the operation of the receiver illustrated in FIG. 47 with reference to (a) to (c).
FIG. 49 is a characteristic diagram for explaining the operation of the receiver shown in FIG. 47 with reference to (a) and (b).
FIG. 50 is a block diagram showing a basic configuration of a receiver according to a twentieth embodiment of the present invention.
FIG. 51 is a block diagram showing a specific configuration of FIG. 50;
FIG. 52 is a block diagram showing a main part of FIGS. 50 and 51;
FIG. 53 is a block diagram showing a configuration of a conventional direct conversion receiver including an AC couple in a signal path in an analog signal recording circuit.
54 (a) is a block diagram showing a main part of a mixer, and FIG. 54 (b) is a characteristic diagram for explaining that a DC offset occurs.
FIG. 55 is a view for explaining that DC offset removal is insufficient in an AC couple.
FIG. 56 is a view for explaining that a DC offset has a variable component and a fixed component.
FIG. 57 is a block diagram showing a configuration of a conventional direct conversion receiver.
FIG. 58 is a view showing the configuration of a conventional zero-IF receiver having a radio section gain switching function.
FIG. 59 is a table showing a wireless gain switching mode.
FIGS. 60A and 60B are a block diagram and a characteristic diagram showing that DC offset fluctuation occurs due to gain switching of a radio unit. FIGS.
61 (a) is a block diagram and FIG. 61 (b) is a characteristic diagram showing that DC offset fluctuation occurs due to gain switching of a radio unit.
FIG. 62 is a conceptual diagram showing that deterioration of reception characteristics due to DC offset fluctuation is shown in (a) when correction is not in time, and (b) when it occurs in a reception slot.
[Explanation of symbols]
1 Receiver
2 Antenna
3 A / D converter
5 D / A converter
10 Analog signal processing unit
16,17 mixer
20, 21, 24, 25, 28, 29 First offset correction means
22,23 LPF
40 Digital signal processing unit
41, 42 DC offset detecting means
43,44 DC offset holding means
45, 46 Second offset correction means
51,52 Offset distribution means

Claims (28)

A receiving unit for receiving a radio frequency signal, an analog signal processing unit for amplifying, band converting, and frequency converting the analog signal input from the receiving unit; And a digital signal processing unit that processes the digital signal converted by the AD conversion unit, a receiver having a DC offset removal function,
Offset detection means provided in the digital signal processing unit and detecting a DC offset signal generated in the reception unit or the frequency conversion unit,
Offset holding means provided in the digital signal processing unit and holding the DC offset signal detected by the offset detection means,
A DA converter for converting the DC offset signal detected by the digital signal processor into an analog signal,
First offset correction means provided in the analog signal processing unit and correcting the analog signal based on a DC offset signal converted to an analog signal by the DA conversion unit;
A second offset correction unit that is provided in the digital signal processing unit and digitally reduces a part of the DC offset signal held by the offset holding unit to reduce the DC offset;
When the absolute value of the offset detected by the offset detection means exceeds a predetermined threshold value, offset distribution for correcting at least the offset value exceeding the predetermined threshold value by the first offset correction means. Means,
A receiver having a DC offset removing function, comprising: 2. The receiver according to claim 1, wherein the DC offset signal held by the DC offset holding unit is updated every time an offset is detected by the offset detection unit . 3. 2. The receiver according to claim 1 , wherein the predetermined threshold is a power of two . A receiving unit for receiving a radio frequency signal, an analog signal processing unit for amplifying, band converting, and frequency converting the analog signal input from the receiving unit; And a digital signal processing unit that processes the digital signal converted by the AD conversion unit, a receiver having a DC offset removal function,
Offset detecting means provided in the digital signal processing unit and detecting a DC offset signal generated in the receiving unit or the frequency conversion unit,
Offset holding means provided in the digital signal processing unit and holding the DC offset signal detected by the offset detection means,
A DA converter for converting the DC offset signal detected by the digital signal processor into an analog signal,
First offset correction means provided in the analog signal processing unit and correcting the analog signal based on a DC offset signal converted to an analog signal by the DA conversion unit;
A second offset correction unit that is provided in the digital signal processing unit and digitally reduces a part of the DC offset signal held by the offset holding unit to reduce the DC offset;
Both when correcting an offset by the offset upper bits of the offset held by the holding means into an analog value by the DA conversion unit of the first offset correction means, the offset stored in the offset holding means A receiver having a DC offset removing function, wherein the offset is corrected by the second offset correcting means using lower bits . A receiving unit for receiving a radio frequency signal, an analog signal processing unit for amplifying, band converting, and frequency converting the analog signal input from the receiving unit; And a digital signal processing unit that processes the digital signal converted by the AD conversion unit, a receiver having a DC offset removal function,
Offset detecting means provided in the digital signal processing unit and detecting a DC offset signal generated in the receiving unit or the frequency conversion unit,
Offset holding means provided in the digital signal processing unit and holding the DC offset signal detected by the offset detection means,
A DA converter for converting the DC offset signal detected by the digital signal processor into an analog signal,
First offset correction means provided in the analog signal processing unit and correcting the analog signal based on a DC offset signal converted to an analog signal by the DA conversion unit;
A second offset correction unit that is provided in the digital signal processing unit and digitally reduces a part of the DC offset signal held by the offset holding unit to reduce the DC offset;
The offset holding unit includes a first storage unit that holds at least an initial value of the offset detected by the offset detection unit, and an offset that is set by the first and second offset correction units based on the initial value of the offset. A receiver having a DC offset removal function , comprising: a second storage unit that holds a variation in offset that changes with time detected by the offset detection unit after being corrected . The DC offset removing function according to claim 5 , wherein the initial value of the offset stored in the first storage unit is detected only once by the offset detection unit and is not changed thereafter. Receiver. The receiver according to claim 5 , wherein the initial value of the offset stored in the first storage unit is detected and set when power is turned on . 6. The reception apparatus according to claim 5 , wherein the initial value of the offset stored in the first storage unit is detected and updated every time a predetermined period elapses. Machine. 6. The apparatus according to claim 5 , wherein the initial value of the offset stored in the first storage unit is updated when a variation of the offset that changes with time exceeds a predetermined value . Receiver with DC offset removal function. 6. The DC power supply according to claim 5 , wherein the variation of the offset stored in the second storage unit is corrected by the second offset correction unit provided in the digital signal processing unit. Receiver with offset removal function. The initial value of the offset stored in the first storage unit is corrected by the first offset correction unit provided in the analog signal processing unit, and is stored by the second storage unit. 6. The receiver according to claim 5 , wherein the offset variation is corrected by the second offset correction unit provided in the digital signal processing unit . A receiving unit for receiving a radio frequency signal, an analog signal processing unit for amplifying, band converting, and frequency converting the analog signal input from the receiving unit; And a digital signal processing unit that processes the digital signal converted by the AD conversion unit, a receiver having a DC offset removal function,
An offset detecting means for detecting a DC offset signal generated by the receiving unit or the frequency converter is provided to the digital signal processing unit, the direct current detected by the offset detecting means provided in front SL digital signal processor Offset holding means for holding an offset signal, a DA converter for converting the DC offset signal detected by the digital signal processor into an analog signal, and an analog signal provided in the analog signal processor and being provided by the DA converter. And a first offset correction means for correcting the analog signal based on the DC offset signal converted to
Means for measuring a received electric field strength input via the receiving section, means for setting a plurality of gains in the analog signal processing section based on the received electric field strength, and wherein the plurality of gains are set in the analog signal processing section. The offset detection means for detecting a plurality of DC offset values generated corresponding to a plurality of gains, the offset holding means for holding the plurality of DC offset values, and a gain corresponding to the gain set in the analog signal processing unit The first offset correction means for correcting the DC offset value obtained,
Further, the analog signal processing unit includes a mixer pair that frequency-converts at least an in-phase component and a quadrature component of the radio frequency signal input to the reception unit, and a common-mode component that is an output of the mixer pair. A baseband filter provided in each of a channel and a quadrature component channel, wherein the first offset correction unit is provided at least in a stage preceding the baseband filter to correct the DC offset generated in the analog signal processing unit. receiver with a DC offset removal function, characterized in that are. An analog signal processing unit set to a first gain value, the AD conversion unit converting an output of the analog signal processing unit into a digital value, an overflow detection circuit detecting an overflow state of the AD conversion unit, Control means for controlling a gain of the analog signal processing unit to be set to a second gain value smaller than the first gain value when an overflow state is detected by the overflow detection circuit. A receiver having the DC offset removing function according to claim 12 . The analog signal processing unit includes a storage unit that detects and stores a DC offset generated from an input radio frequency signal, and the first offset correction unit reads out the first offset correction unit from the storage unit even in a single reception. 14. The receiver according to claim 13 , wherein the DC offset is corrected based on the gain value of 1 . A receiving unit for receiving a radio frequency signal, an analog signal processing unit for amplifying, band converting, and frequency converting the analog signal input from the receiving unit; And a digital signal processing unit that processes the digital signal converted by the AD conversion unit, a receiver having a DC offset removal function,
An offset detecting means for detecting a DC offset signal generated by the receiving unit or the frequency converter is provided to the digital signal processing unit, the direct current detected by the offset detecting means provided in front SL digital signal processor and offset holding means for holding the offset signal, more analog the DC offset signal detected by the digital signal processing unit and a DA converter for converting the analog signal to the DA conversion unit provided to the analog signal processing unit A first offset correction unit that corrects the analog signal based on the DC offset signal converted into a signal.
An analog signal absent means for providing no input to the analog signal input to the analog signal processing unit is provided, and when the analog signal is absent, the offset detecting means detects the DC offset. The first offset correction means corrects the DC offset based on the performed DC offset value,
The analog signal non-input means is configured by a changeover switch provided between the radio frequency signal amplifier provided in the analog signal processing unit and the receiving unit,
The analog signal non-input means includes an attenuator connected in parallel to a radio frequency signal amplifier provided in the analog signal processing unit, four switches provided before and after the amplifier and the attenuator, respectively, A fifth switch provided on a connection line at the preceding stage of the attenuator, wherein the signal supply path from the receiving unit to the analog signal processing unit is always connected, but the analog signal processing unit is not input. A receiver equipped with a DC offset removal function, which can be put into a state . A receiving unit for receiving a radio frequency signal, an analog signal processing unit for amplifying, band converting, and frequency converting the analog signal input from the receiving unit; And a digital signal processing unit that processes the digital signal converted by the AD conversion unit, a receiver having a DC offset removal function,
Offset detecting means provided in the digital signal processing unit and detecting a DC offset signal generated in the receiving unit or the frequency conversion unit,
And offset holding means for holding said detected DC offset signal by the offset detecting means provided in front SL digital signal processing unit,
A DA converter for converting the DC offset signal detected by the digital signal processor into an analog signal,
A first offset correction unit that is provided in the analog signal processing unit and corrects the analog signal based on a DC offset signal converted to an analog signal by the DA conversion unit;
The offset detection means detects the DC offset by a time average of the output of the AD conversion unit, and the first offset correction means processes the DC offset converted to an analog signal by the DA conversion unit in the analog processing unit. DC offset is corrected by subtracting from the analog signal
The offset detection means detects the DC offset of the current reception slot with the time average value of the DC offset detected from the past reception slot in the time division multiple access system as an initial value, and the first offset correction means detects the DC offset of the current reception slot. Correct the DC offset of the current receive slot,
The offset detecting means includes a cumulative adding circuit for cumulatively adding the digital signal input from the AD converter, and a dividing circuit for dividing the cumulatively added signal. A plurality of delay circuits for delaying the output of the unit by a predetermined time, and a plurality of weighting circuits for multiplying a value delayed by the delay circuit with a weighting coefficient set so as to be heavier as the DC offset is closer to the output, and outputting A receiver having a DC offset removing function, comprising: a summation circuit for obtaining a sum of outputs from the weighting circuit and outputting the sum as a DC offset value . The receiver according to claim 16, wherein the weighting coefficients of the plurality of weighting circuits are set such that the older the weight, the lighter the weight, and the newer the weight, the heavier the weight . 17. The DC power supply according to claim 16 , wherein the weighting coefficients set in the plurality of weighting circuits change according to a time-varying amount of change in the DC offset detected by the offset detection right unit. Receiver with offset removal function. A receiving unit for receiving a radio frequency signal, an analog signal processing unit for amplifying, band converting, and frequency converting the analog signal input from the receiving unit; And a digital signal processing unit that processes the digital signal converted by the AD conversion unit, a receiver having a DC offset removal function,
An offset detecting means for detecting a DC offset signal generated by the receiving unit or the frequency converter is provided to the digital signal processing unit, the direct current detected by the offset detecting means provided in front SL digital signal processor Offset holding means for holding an offset signal, a DA converter for converting the DC offset signal detected by the digital signal processor into an analog signal, and an analog signal provided in the analog signal processor and being provided by the DA converter. And a first offset correction means for correcting the analog signal based on the DC offset signal converted to
A test mode for testing a band limiting characteristic of the analog signal processing unit, wherein the digital signal processing unit generates a test signal for testing the band limiting characteristic of the analog signal processing unit; And a adder that adds the test signal output from the test signal generator to the DC offset signal in the test mode, wherein the first correction unit converts the analog signal into an analog signal by the DA conversion unit. A receiver having a DC offset removing function, wherein the output of the adder after the conversion is supplied as an input to a band limiting circuit provided in the analog signal processing unit. The analog signal processing unit tests the band limiting characteristic in the analog signal processing unit after the DC offset is detected by the offset detection unit and the DC offset is held by the offset holding unit. A receiver having the DC offset removing function according to claim 19. The analog signal processing unit includes a band limiting circuit having a function of adjusting a band limiting characteristic of the analog signal by a frequency characteristic control signal, and the digital signal processing unit is supplied to the band limiting circuit during the test mode. 20. The DC offset removing function according to claim 19 , further comprising frequency characteristic control means for generating the frequency characteristic control signal in accordance with a difference between a frequency characteristic detected by the test signal and a desired frequency characteristic. Equipped receiver. A transmitter for transmitting a radio frequency signal composed of an information signal including sound and image,
A communication network for transmitting and receiving the radio frequency signal,
A receiving unit that receives the radio frequency signal; an analog signal processing unit that performs amplification, band conversion, and frequency conversion processing on the analog signal input from the receiving unit; and outputs an analog signal from the analog signal to a digital signal. An A / D converter for converting the signal into a signal; a digital signal processor for processing the digital signal converted by the A / D converter; and a DC offset provided in the digital signal processor and generated by the receiver or the frequency converter. Offset detection means for detecting a signal; offset holding means provided in the digital signal processing unit for holding the DC offset signal detected by the offset detection means; and the DC offset detected by the digital signal processing unit. A DA converter for converting a signal into an analog signal, and the analog signal A first offset correction unit provided in the digital signal processing unit and configured to correct the analog signal based on the DC offset signal converted to an analog signal by the DA conversion unit; A second offset correction unit for digitally reducing a part of the DC offset signal held by the second unit to reduce the DC offset; A DC offset removal function, comprising: when the absolute value of the offset exceeds a predetermined threshold, the first offset correction unit corrects at least an offset exceeding the predetermined threshold by the first offset correction unit. A receiver with
A communication system comprising: A transmitter for transmitting a radio frequency signal composed of an information signal including sound and image,
A communication network for transmitting and receiving the radio frequency signal,
A receiving unit for receiving a radio frequency signal, an analog signal processing unit for amplifying, band converting, and frequency converting the analog signal input from the receiving unit; and converting the output of the analog signal processing unit from an analog signal to a digital signal. An analog-to-digital converter, a digital signal processor for processing the digital signal converted by the analog-to-digital converter, and a DC offset signal provided in the digital signal processor and generated by the receiver or frequency converter. Offset detecting means for detecting the DC offset signal, which is provided in the digital signal processing section and holds the DC offset signal detected by the offset detecting means, and the DC offset signal detected by the digital signal processing section. DA converter for converting the analog signal into an analog signal, and the analog signal processing A first offset correction means for correcting the analog signal based on a DC offset signal converted to an analog signal by the DA conversion section; and a first offset correction means provided for the digital signal processing section and held by the offset holding means. Second offset correction means for digitally reducing a part of the obtained DC offset signal to reduce the DC offset, wherein the higher-order bit of the offset held in the offset holding means is converted to the DA converter To correct the offset by the first offset correction means, and correct the offset by the second offset correction means using the lower bits of the offset held in the offset holding means. A receiver with an offset removal function,
A communication system comprising: A transmitter for transmitting a radio frequency signal composed of an information signal including sound and image,
A communication network for transmitting and receiving the radio frequency signal,
A receiving unit for receiving a radio frequency signal, an analog signal processing unit for performing amplification, band conversion, and frequency conversion processing on the analog signal input from the receiving unit; An analog-to-digital converter, a digital signal processor for processing the digital signal converted by the analog-to-digital converter, and a DC offset signal provided in the digital signal processor and generated by the receiver or frequency converter. Offset detecting means for detecting the DC offset signal provided in the digital signal processing section and holding the DC offset signal detected by the offset detecting means, and the DC offset signal detected by the digital signal processing section DA converter for converting the analog signal into an analog signal, and the analog signal processing A first offset correction means for correcting the analog signal based on a DC offset signal converted to an analog signal by the DA conversion section; and a first offset correction means provided for the digital signal processing section and held by the offset holding means. A second offset correction unit for digitally reducing a part of the DC offset signal thus obtained to reduce the DC offset, and the offset holding unit holds at least an initial value of the offset detected by the offset detection unit A first storage unit for storing the offset variation that changes with time detected by the offset detection unit after the offset is corrected by the first and second offset correction units based on the initial value of the offset. DC offset comprising: A receiver having a removal function,
A communication system comprising: A transmitter for transmitting a radio frequency signal composed of an information signal including sound and image,
A communication network for transmitting and receiving the radio frequency signal,
A receiving unit that receives the radio frequency signal; an analog signal processing unit that performs amplification, band conversion, and frequency conversion processing on the analog signal input from the receiving unit; and outputs an analog signal from the analog signal to a digital signal. An A / D converter for converting the signal into a signal; a digital signal processor for processing the digital signal converted by the A / D converter; and a DC offset provided in the digital signal processor and generated by the receiver or the frequency converter. an offset detecting means for detecting the signal, before Symbol offset holding means for holding said detected DC offset signal by the offset detecting means provided in the digital signal processing unit, the DC said detected by a digital signal processor A DA converter for converting an offset signal into an analog signal, and the analog signal A first offset correction unit provided in a control unit for correcting the analog signal based on a DC offset signal converted to an analog signal by the DA conversion unit; and a reception electric field strength input via the reception unit. Means for measuring; means for setting a plurality of gains in the analog signal processing unit based on the received electric field strength; and a plurality of DC offsets corresponding to the plurality of gains set in the analog signal processing unit. The offset detection means for detecting a value, the offset holding means for holding the plurality of DC offset values, and the first offset correction for correcting a DC offset value corresponding to a gain set in the analog signal processing unit Means, and the analog signal processing unit further comprises at least the radio frequency signal input to the receiving unit. A mixer pair for frequency-converting mutually orthogonal signals of an in-phase component and a quadrature component, and baseband filters respectively provided for an in-phase component channel and a quadrature component channel which are outputs of the mixer pair; Correction means, a receiver having a DC offset removal function provided at least in the preceding stage of the baseband filter to correct the DC offset generated in the analog signal processing unit,
A communication system comprising: A transmitter for transmitting a radio frequency signal composed of an information signal including sound and image,
A communication network for transmitting and receiving the radio frequency signal,
A receiving unit that receives the radio frequency signal; an analog signal processing unit that performs amplification, band conversion, and frequency conversion processing on the analog signal input from the receiving unit; and outputs an analog signal from the analog signal to a digital signal. An A / D converter for converting the signal into a signal; a digital signal processor for processing the digital signal converted by the A / D converter; and a DC offset provided in the digital signal processor and generated by the receiver or the frequency converter. an offset detecting means for detecting the signal, before Symbol offset holding means for holding said detected DC offset signal by the offset detecting means provided in the digital signal processing unit, the DC said detected by a digital signal processor A DA converter for converting an offset signal into an analog signal, and the analog signal And a first offset correction means for correcting the analog signal based on a DC offset signal converted into an analog signal by the DA conversion unit, and a first offset correction unit which is input to the analog signal processing unit. An analog signal non-input means for inputting no analog signal, wherein the offset detection means detects the DC offset when the analog signal is not input, based on the DC offset value detected at this time. The first offset correction unit corrects a DC offset, and the analog signal non-input unit is configured by a changeover switch provided between a radio frequency signal amplifier provided in the analog signal processing unit and the reception unit. The analog signal non-input means is configured to increase a radio frequency signal provided in the analog signal processing unit. An attenuator connected in parallel to the amplifier, four switches provided before and after the amplifier and the attenuator, respectively, and a fifth switch provided on a connection line in the preceding stage of the amplifier and the attenuator, Even if the signal supply path from the receiving unit to the analog signal processing unit is always connected, a receiver having a DC offset removal function that can put the analog signal processing unit into a non-input state,
A communication system comprising: A transmitter for transmitting a radio frequency signal composed of an information signal including sound and image,
A communication network for transmitting and receiving the radio frequency signal,
A receiving unit that receives the radio frequency signal; an analog signal processing unit that performs amplification, band conversion, and frequency conversion processing on the analog signal input from the receiving unit; and outputs an analog signal from the analog signal to a digital signal. An A / D converter for converting the signal into a signal; a digital signal processor for processing the digital signal converted by the A / D converter; and a DC offset provided in the digital signal processor and generated by the receiver or the frequency converter. an offset detecting means for detecting the signal, before Symbol offset holding means for holding said detected DC offset signal by the offset detecting means provided in the digital signal processing unit, the DC said detected by a digital signal processor A DA converter for converting an offset signal into an analog signal, and the analog signal And a first offset correction means for correcting the analog signal based on the DC offset signal converted to an analog signal by the DA conversion section. The DC offset is detected by a time average of the output of the unit, and the first offset correction unit subtracts the DC offset converted into an analog signal by the DA converter from the analog signal processed by the analog processing unit. The DC offset is corrected, and the offset detecting means detects the DC offset of the current reception slot with the time average value of the DC offset detected from the past reception slot in the time division multiple access system as an initial value, and detects the first offset. The correction means detects the DC offset of the detected current reception slot. The offset detection means comprises a cumulative addition circuit for cumulatively adding the digital signal input from the AD converter, and a division circuit for dividing the cumulatively added signal. A plurality of delay circuits for delaying the output of the offset detection means by a predetermined time, and a value delayed by the delay circuit multiplied by a weighting coefficient set so as to be heavier the closer to the DC offset, and output. A plurality of weighting circuits, an addition circuit that takes the sum of the outputs of the weighting circuits and outputs the value as a DC offset value, and a receiver having a DC offset removal function,
A communication system comprising:
A transmitter for transmitting a radio frequency signal composed of an information signal including sound and image,
A communication network for transmitting and receiving the radio frequency signal,
A receiving unit that receives the radio frequency signal; an analog signal processing unit that performs amplification, band conversion, and frequency conversion processing on the analog signal input from the receiving unit; and outputs an analog signal from the analog signal to a digital signal. An A / D converter for converting the signal into a signal; a digital signal processor for processing the digital signal converted by the A / D converter; and a DC offset provided in the digital signal processor and generated by the receiver or the frequency converter. an offset detecting means for detecting the signal, before Symbol offset holding means for holding said detected DC offset signal by the offset detecting means provided in the digital signal processing unit, the DC said detected by a digital signal processor A DA converter for converting an offset signal into an analog signal, and the analog signal And a first offset correction means for correcting the analog signal based on the DC offset signal converted to an analog signal by the DA conversion unit, and a band limitation of the analog signal processing unit. A test mode for testing a characteristic, the digital signal processing unit generates a test signal for testing the band limiting characteristic of the analog signal processing unit, and a test signal generator. An adder for adding the test signal output from a test signal generator to the DC offset signal, wherein the first correction unit converts the analog signal into an analog signal by the DA converter. DC offset removing function for supplying the output of the analog signal processing section as an input to a band limiting circuit provided in the analog signal processing section A receiver that includes,
A communication system comprising:

Images