JP2002094584A - Receiver and method for estimating timing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To estimate receiving timing with higher accuracy without increasing the sampling rate in an A/D converter and to reduce the power consumption and cost of a terminal in digital radio equipment. SOLUTION: Correlation value between digital I and Q signal strings stored in a received signal buffer 105 and a known symbol string inserted into a prescribed position is calculated in a vector operation, and receiving timing is first estimated in the sampling rate unit at a position where the value becomes maximum. The ratio of the estimated timing to the correlation value between the estimated timing and timing ahead the estimated timing by one sample is calculated, a position where difference becomes minimum is calculated by comparing the ratio with the table value of the value of the ratio that is preliminarily calculated in each small time interval, and the receiving timing is estimated more accurately than the sampling rate on the basis of the position.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver and a timing estimation method used in a digital radio communication system.

[0002]

2. Description of the Related Art In the field of wireless communication in recent years, with the progress of multimedia and the increase in communication traffic, it is desired to increase the transmission speed. The trend is similar.

On the other hand, as a wireless communication system, a system using a digital modulation / demodulation technique is predominant in terms of effective use of frequency and easiness of integration. A general configuration of a wireless device is such that a part of baseband signal processing is performed by digital processing, and frequency conversion and amplification with an RF signal are performed by analog processing. At this time, an analog / digital converter (hereinafter, A / D converter) and a digital / analog converter (hereinafter, D / A converter), which play a role of connecting the analog section and the digital section, are very important components. It is one of the
In order to configure a high-performance transceiver, it is desired to use an A / D or D / A converter having a high-precision bit resolution and sampling rate.

However, in the case of a configuration in which a small-sized and low-power-consumption configuration is prioritized, such as a portable terminal, an A / D converter having sufficient performance is not always used. In particular, when the transmission speed of communication is increased as seen in recent years, the sampling rate in the A / D converter becomes
In some cases, a value that is too large compared to the symbol rate cannot be obtained, and reception demodulation is performed using a signal sampled at a timing deviated from an ideal reception timing.

For example, when a digitally modulated signal transmitted by Nyquist is sampled at an oversampling rate twice as high as the symbol rate and used for receiving and demodulating, the maximum of ± Nyquist point timing with respect to the ideal receiving timing, that is, the timing of the Nyquist point. The reception demodulation is performed using the signal shifted by 1 / 4T.

Hereinafter, an example of a method for estimating a reception timing from data sampled in a conventional digital radio will be briefly described with reference to FIG.
The baseband signal that has been received, quadrature-demodulated, and sampled by the A / D converter is temporarily stored in the reception signal buffer 801. Here, the received digital modulation signal is
It is configured in burst units, and it is assumed that a known symbol sequence for synchronization is inserted at a predetermined position in the burst.

The known vector table 802 previously calculates and stores a complex conjugate vector sequence of a vector sequence to be obtained when the section of the known symbol sequence is sampled at an ideal timing. , Between the vector sequence stored in the table and the vector sequence of the I and Q signals stored in the reception buffer, a vector operation similar to equation (1) shown in the description of the first embodiment is performed. This is performed for each timing, and a value corresponding to the degree of correlation for each timing is obtained. Since the vector calculation result takes the maximum value when a vector sequence of the signal at the sampling timing closest to the ideal reception timing is used, the timing estimation circuit 804 outputs the signal whose calculation result takes the maximum value. By obtaining the position of the vector sequence, it is possible to detect the sampling timing closest to the ideal reception timing.

For example, when the sampling rate of the signal stored in the reception signal buffer 801 is twice as high as the symbol rate, ± 1 / 4T
(T is the symbol length), which enables estimation with accuracy. Based on the reception timing estimated by the present method, a reception vector is selected to perform symbol determination, or a transmission timing for transmission is determined. In a system in which there is no strict requirement on the receiving sensitivity characteristic or systematic transmission timing, it is considered that sufficient performance can be obtained by this method.

[0009]

However, when the present invention is applied to a terminal of a communication system that requires extremely high transmission / reception timing, the conventional reception timing estimating means as shown in FIG. Can not be obtained.

For example, in order to use a multi-level modulated signal in order to improve the frequency use efficiency or to receive a modulated signal in which a transmission band is narrower than the Nyquist condition without error, it is necessary to use a modulation signal. It is necessary to obtain sampling data close to the ideal reception timing.

Further, even when finer timing accuracy is required for the timing at the time of transmission, more accurate timing estimation is required. To improve the timing estimation accuracy, a method of increasing the sampling rate in the A / D converter is conceivable. However, this leads to an increase in power consumption in the terminal and an increase in the size of the circuit.

[0012] The present invention has been made in view of the above point, and it is possible to estimate the reception timing with higher accuracy without increasing the sampling rate in an A / D converter in a digital radio, and to reduce the consumption of a terminal. It is an object of the present invention to provide a receiver and a timing estimation method capable of reducing current and cost.

[0013]

According to the present invention, there is provided a receiving apparatus comprising: first timing estimating means for estimating a timing of a received signal at a specific sample timing and outputting a first timing estimation result; And a second timing estimating means for performing a timing estimation based on the correlation value ratio of the known signal between the samples and the first timing estimation result and outputting a second timing estimation result.

According to this configuration, the symbol timing can be estimated with a time resolution twice as long as the period of the sampling clock supplied to the A / D conversion circuit.

[0015] The receiving apparatus according to the present invention, in the above configuration,
A configuration including a propagation path estimating means for estimating a propagation path state and an updating means for updating the correlation value ratio based on the propagation path state is adopted.

According to this configuration, the propagation path environment can be reflected in the calculated value ratio, and even if the propagation path environment changes, highly accurate timing estimation can be performed and excellent reception performance can be exhibited.

The receiving apparatus according to the present invention is a storage means for storing filter tap coefficients each having a characteristic of removing intersymbol interference from a known signal in a received signal, which is sampled at a time unit finer than a specific sampling rate. An intersymbol interference filter that performs filtering on a received signal using the filter tap coefficients and outputs a plurality of filtering results, and a third timing estimating unit that performs timing estimation based on the plurality of filtering results; Is adopted.

According to this configuration, it is possible to estimate the reception timing when receiving and demodulating a digitally modulated signal with higher accuracy than the resolution of oversampling at the time of reception.

[0019] The receiving apparatus according to the present invention, in the above configuration,
A configuration is provided that includes a demodulation unit that performs demodulation processing on data in the received signal using the timing estimation result obtained by the third timing estimation unit.

According to this configuration, even if the oversampling timing at the time of reception deviates from the ideal reception timing, more accurate symbol determination can be performed.

The receiving apparatus according to the present invention includes a first timing estimating means for estimating a timing of a received signal at a specific sample timing and outputting a first timing estimation result, and a known signal between samples sampled at the sampling rate. A second timing estimating means for performing timing estimation based on the correlation value ratio and the first timing estimation result, and outputting a second timing estimation result;
An accumulating means for accumulating filter tap coefficients each having a characteristic of removing intersymbol interference from a known signal in a received signal sampled at a time unit finer than a specific sampling rate; An inter-symbol interference filter that performs filtering on a received signal using a filter tap coefficient selected using the obtained timing estimation result and outputs a filtering result is adopted.

According to this configuration, even if the oversampling timing at the time of reception deviates from the ideal reception timing, more accurate symbol determination can be performed.

The present invention is a communication terminal device provided with a receiving device, wherein the receiving device estimates a timing of a received signal at a specific sample timing and outputs a first timing estimation result. And second timing estimating means for performing timing estimation based on the correlation value ratio of a known signal between samples sampled at the sampling rate and the first timing estimation result and outputting a second timing estimation result. A communication terminal device is provided.

According to the present invention, there is provided a communication terminal apparatus provided with a receiving apparatus, wherein the receiving apparatus performs inter-symbol interference with a known signal in a received signal sampled at a time unit finer than a specific sampling rate. Accumulating means for accumulating a filter tap coefficient having a characteristic of removing the filter, an intersymbol interference filter for performing filtering on a received signal using the filter tap coefficient and outputting a plurality of filtering results, and the plurality of filtering results And a third timing estimating means for performing timing estimation based on the communication terminal device.

The present invention is a device having a memory storing a reception timing estimation program, wherein the reception timing estimation program estimates the timing of a received signal at a specific sample timing and outputs a first timing estimation result. And performing a timing estimation based on a correlation value ratio of a known signal between samples sampled at the sampling rate and the first timing estimation result and outputting a second timing estimation result. Provide a featured device.

According to the present invention, a reception timing estimating program and a filter tap coefficient having characteristics of removing intersymbol interference from a known signal in a received signal, which are sampled shifted by a time unit finer than a specific sampling rate, are stored. A device having a memory, wherein the reception timing estimation program performs a process of performing filtering on a received signal using the filter tap coefficients to output a plurality of filtering results, and a timing based on the plurality of filtering results. Performing the estimation.

According to the timing estimating method of the present invention, a first timing estimating step of estimating a timing of a received signal at a specific sample timing and outputting a first timing estimating result; A second timing estimation step of performing timing estimation based on the correlation value ratio of the signal and the first timing estimation result and outputting a second timing estimation result.

According to this method, it is possible to estimate the symbol timing with a time resolution twice as long as the period of the sampling clock supplied to the A / D conversion circuit.

The timing estimating method of the present invention accumulates filter tap coefficients each having a characteristic of removing intersymbol interference from a known signal in a received signal, which is sampled at a time unit finer than a specific sampling rate. A step of performing filtering on a received signal using the filter tap coefficients to output a plurality of filtering results, and a third timing estimating step of performing timing estimation based on the plurality of filtering results. Have.

According to this method, the reception timing at the time of receiving and demodulating a digitally modulated signal can be estimated with higher accuracy than the resolution of oversampling at the time of reception.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following embodiments, A
A case will be described where the reception timing can be estimated with higher accuracy without increasing the sampling rate in the / D conversion circuit, thereby reducing current consumption and cost of the terminal.

(Embodiment 1) In this embodiment, after rough timing estimation (low accuracy) is performed at a predetermined sampling rate, a correlation value ratio of a known signal between samples sampled at the sampling rate is determined. A case in which highly accurate timing estimation (fine adjustment) is performed based on the above will be described. In this case, the correlation value ratio of the known signal between the samples is obtained in advance.

FIG. 1 is a block diagram showing a configuration of a communication terminal apparatus provided with a receiving apparatus according to Embodiment 1 of the present invention. In FIG. 1, only the receiving system is shown, and the description of the transmitting system is omitted.

In the communication terminal apparatus shown in FIG. 1, a downlink signal (received signal) transmitted from the base station apparatus is received by quadrature detection circuit 102 via antenna 101. The quadrature detection circuit 102 performs quadrature frequency conversion on the received signal (digital modulation signal) to generate an in-phase signal (I signal) and a quadrature signal (Q signal) in a baseband, and A / D converts the I signal and the Q signal respectively. Output to circuits 103 and 104. The quadrature detection circuit 102 performs quadrature frequency conversion of the received signal (digital modulation signal) to generate an in-phase signal (I signal) and a quadrature signal (Q signal) in a baseband, and A / D converts the I signal and the Q signal respectively. Output to circuits 103 and 104. In the present embodiment, the modulation method of the digital modulation signal is not particularly limited. Before the received signal is input to the quadrature detection circuit 102, predetermined wireless reception processing (frequency conversion, amplification, removal (filtering) of signals in unnecessary frequency bands, etc.) has already been performed, and an appropriate Input level,
It is assumed that the frequency band is set.

The A / D conversion circuit 103 quantizes the I signal into a digital value based on the sampling clock, and converts the quantized digital I signal into a reception signal buffer 105.
Output to The A / D conversion circuit 104 has the same configuration as the A / D conversion circuit 103, and quantizes the Q signal.
The digital Q signal is output to the reception signal buffer 105. In the present embodiment, A / D conversion circuits 103 and 104
Is not particularly limited as long as it is determined from the system specifications.

In the present embodiment, the received signal is subjected to predetermined digital modulation, is converted into a downlink signal transmitted from the base station apparatus in a burst configuration, and a known symbol sequence, which is a known signal, is inserted into the burst. Suppose
However, the insertion position and number of known symbols are not limited in the present embodiment, and a configuration in which a sequence of several tens of symbols is inserted in the center of a burst may be inserted, or may be inserted at predetermined intervals in a burst. Here, the sampling rate is, for example, twice the symbol rate.

The reception signal buffer 105 buffers digital I and Q signals. For example, the reception signal buffer 105 includes a memory for storing quantized data having a length of one burst or more, a FIFO (First In First Out) buffer, and the like.

The known vector table 106 stores a complex conjugate vector sequence of a vector sequence obtained when sampling a known symbol sequence section inserted in a burst at an ideal timing. For example, the known vector table 106 is configured by a memory such as a RAM and a ROM. In the present embodiment, it is assumed that known vector table 106 stores a complex conjugate vector sequence corresponding to a case where a known symbol sequence section is oversampled twice.

The vector operation circuit 107 performs a vector operation using the digital I and Q signals stored in the reception signal buffer 105 and the known vector sequence stored in the known vector table 106, and stores the operation result in the operation result buffer. Output to 108. For example, the vector operation circuit 1
Reference numeral 07 denotes an arithmetic processing block constituted by logic and a DSP. Details of the calculation will be described later.

The operation result buffer 108 buffers the operation result from the vector operation circuit 107. For example, the operation result buffer 108 is configured by a memory such as a RAM or a FIFO buffer.

The timing estimating circuit 109 estimates the reception timing with a precision smaller than the oversampling interval by using the vector operation result of the sampled digital I and Q signal sequences and the known vector sequence. In the present embodiment, the timing estimation circuit 109 includes a low-accuracy timing estimation circuit 1091 and a high-accuracy timing estimation circuit 1092.

The low-precision timing estimating circuit 1091 uses the vector operation result stored in the operation result buffer 108 to estimate the reception timing with the same precision as the oversampling rate. That is, the low-accuracy timing estimation circuit 1091 performs the first-stage relatively coarse timing estimation. For example, the low-accuracy timing estimation circuit 109
Reference numeral 1 denotes a peak detection circuit that detects a timing at which the value of the operation result in the vector operation circuit 107 becomes maximum.

The high-precision timing estimating circuit 1092 estimates the reception timing with higher accuracy than the oversampling rate using the vector operation result stored in the operation result buffer 108 and the estimation result of the low-accuracy timing estimating circuit 1091. That is, the high-precision timing estimation circuit 1092 performs the second-stage high-precision timing estimation. For example, the high-accuracy timing estimating circuit 1092 includes an operation value ratio table 1093 and an operation value ratio determination circuit 1094.

The calculated value ratio table 1093 calculates in advance a calculated value ratio for each minute time unit, stores it as a table value, and reads out the table value as needed.

Here, the calculated value ratio is defined as a value obtained by performing the same calculation as the vector calculation circuit 107 on a signal sequence obtained by sampling the received signal at a timing shifted from the ideal reception timing by a very short time. Is obtained in advance, and the ratio between this value and the same calculated value one time before the previous sample is calculated. This calculated value ratio is obtained in advance for each time unit finer than the sampling rate. In the present embodiment, one-to-one symbol over a range of ± 1/4 symbol from the ideal reception timing.
The calculated value ratio for each / 16 symbol timing shift is calculated and stored as a table value.

The operation value ratio determination circuit 1094 performs highly accurate timing estimation using the low accuracy timing estimation result, the vector operation result stored in the operation result buffer 108, and the value of the operation value ratio table. Details of the operation will be described later. In this embodiment, it is assumed that the approximate position of the burst is unknown at the start of the reception timing estimation.

In the digital demodulation circuit 110, the quantized I signal, Q
Of the signal data, demodulation is performed using sample data of the I signal and Q signal closest to the signal point, and a demodulated data sequence (received data) is output.

The receiving operation in the communication terminal having the above configuration will be described. The digitally modulated I and Q signals are sampled at an oversampling rate twice the symbol rate, and a digital data sequence having a length of one burst or more is stored in the reception signal buffer 105.

In the vector operation circuit 107, the I and Q signal vector sequences R stored in the reception signal buffer 105
x (m) = {I (m), Q (m)} and the complex conjugate vector sequence of the known vector stored in the known vector table 106 Ref *
Using (i) = {Iref (i), Qref (i)}, the vector operation shown in Expression (1) is performed, and the C at each sample timing m is calculated.
The value of (m) is obtained, and the operation result is stored in the operation result buffer 10.
8 is stored.

(Equation 1) Equation (1) where N represents the number of known symbols inserted in the burst.

C (m) obtained by the equation (1) is shown in FIG.
As shown in (a), it is known that a received burst has a maximum value near a position where a known symbol is inserted. Therefore, by detecting the timing at which C (m) becomes maximum in the low-accuracy timing estimating circuit 1091, the timing at which the known symbol is inserted can be estimated with an accuracy within ± 1/2 symbol length. To estimate the timing of the burst.

FIG. 2A is a graph showing a calculation result when the vector calculation of Expression (1) is obtained in advance for each minute time unit. Further, FIG. 2B shows the calculated value ratio R (t) = C (t) / C (tT) between the preceding and succeeding samples, that is, between 1/2 symbols, for the calculation result shown in FIG. / 2) is a graph plotted. The calculated value ratio table 1093 stores R calculated for each 1/16 symbol timing calculated in advance.
The value of (t) is stored.

The operation value ratio determination circuit 1094 compares the vector operation result C (m) at the timing estimated by the low-precision timing estimating circuit 1091 with the vector operation result C (m-1) one-half symbol timing before. Ratio C (m) / C
(m-1) is calculated, and by detecting the position of the calculated value ratio table closest to this value, highly accurate timing is estimated.

For example, when the timing of double oversampling in the receiver is shifted by -2/16 symbol length from the ideal reception timing, that is, FIG.
Assuming the case of the timing of the ▼ mark in (a),
The process of timing estimation in that case will be described.

First, the low-accuracy timing estimation circuit 1091
T = -2 / 16T by detecting the peak of C (m)
Is obtained as a low-accuracy timing estimation result. Subsequently, in the calculated value ratio determination circuit 1094, R (t) = C (-2 / 16T) / C
(−2 / 16T−1 / 2T) ≒ 3.4 is calculated, and this value R (t) and FIG.
A comparison is made between the values of the calculated value ratio table 1093 as shown in FIG. In this case, since this value R (t) is closest to the table value when t = −2 / 16T, the current oversampling timing is further shifted by −2/16 symbol length from the ideal reception timing. Can be estimated.

As described above, according to the embodiment of the present invention, after performing coarse timing estimation at the sampling rate at the time of reception, high-precision timing estimation is performed based on the ratio between correlation values with respect to a known signal. Further, it is possible to estimate the reception timing when receiving and demodulating a digitally modulated signal with higher accuracy than the oversampling resolution at the time of reception. In particular, in the timing estimation in the high-precision timing estimation circuit, by using the ratio of the vector operation values, it is sufficient to consider not the absolute value of the received signal level but the relative ratio before and after. Influence can be prevented, and more accurate timing estimation can be performed.

In the present embodiment, the oversampling rate of the I and Q signals is set to twice the symbol rate,
Although the case has been described where the timing estimation accuracy estimated by the high-accuracy timing estimation circuit 1092 is 16 times the symbol rate, the present invention is not limited to this. In this case, the high-precision timing estimation circuit 1092 may set the time resolution of the table value obtained in advance to be higher than the oversampling rate.

Further, in this embodiment, a case has been described in which the equation (1) is used as the vector operation for obtaining the degree of correlation with the known vector sequence. However, the present invention is not limited to this. As shown in equation (2), the absolute value of the sum of the vector products may be used, or a value that does not square the length of the vector may be used to simplify the calculation. Further, if there is another operation that can obtain a result according to the degree of correlation, it may be used.

(Equation 2) Equation (2)

The case where the ratio R (t) to the vector operation result one sample before is used as a criterion used when estimating timing with high accuracy has been described. However, the present invention is not limited to this. The ratio to the vector operation result after one sample may be R '(t) = C (t) / C (t + T / 2) or R
The timing with the highest likelihood may be estimated using (t) and R '(t). Further, instead of using the calculated value ratio, the calculated values of several samples before and after may be stored in a table, and the timing at which the square error is minimized may be estimated.

The operation value ratio used in the high-precision timing estimation circuit 1092 in this embodiment may be based on a true value or a difference between logarithmic values.

If the filtering at the time of transmission and reception and the frequency / phase characteristics on the communication propagation path are known in advance, data of a known vector table including these characteristics may be generated and stored. . Further, as shown in FIG. 3, the propagation path estimation circuit 301 performs propagation path estimation from the received signal, and outputs the estimation result to the computed value ratio recalculation circuit 302, where the computed value ratio is recalculated and recalculated. The calculated value ratio may be output to the calculated value ratio table 1093, and the calculated value ratio table 1093 may be updated. As a result, the propagation path environment can be reflected in the calculated value ratio, and even if the propagation path environment changes, highly accurate timing estimation can be performed and excellent reception performance can be exhibited.

Further, in the present embodiment, description has been made on the assumption that the burst timing is unknown. However, the present invention is not limited to this. In this case, the vector operation may be performed only in the range of several symbols before and after this timing.

In this embodiment, only the method of estimating the reception timing with high accuracy has been described.
The present invention is not limited to this. For example, a configuration may be used in which the oversampling timing is corrected using the estimation result to obtain an ideal sample timing when the next burst is received. It may be used sometimes.

(Embodiment 2) In the present embodiment, a signal having the highest reliability (filtering result) is selected from signals filtered by an ISI removal filter composed of various filter taps, and A case where the corresponding timing is detected will be described.

FIG. 4 is a block diagram showing a configuration of a communication terminal apparatus having a receiving apparatus according to Embodiment 2 of the present invention. In the configuration shown in FIG. 4, the same parts as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and detailed description thereof will be omitted.

The received signal in the present embodiment is a signal subjected to predetermined digital modulation and transmitted in a burst configuration. Further, it is assumed that the digitally modulated signal has caused intersymbol interference (hereinafter, ISI) due to band-limited filtering at the time of transmission and influence on a transmission path. However, it is assumed that the interference characteristics can be assumed in advance on the receiving device side.

Also, as in the first embodiment, it is assumed that a known symbol sequence is inserted in a burst in a received signal, but the position and number of known symbols are not limited in the present embodiment. Also, the sampling rate is, for example, twice the symbol rate.

The reception signal buffer 105 buffers digital I and Q signals. For example, the reception signal buffer 105 is configured by a memory for storing quantized data of one burst length or more, a FIFO buffer, or the like.

The filter tap table 402 previously obtains a filter coefficient which is an inverse characteristic of ISI which is affected by a band limitation at the time of transmission and an influence on a transmission line, and stores the filter coefficient as a read table.

Here, it is assumed that a plurality of tap coefficients are prepared as follows. That is, the tap coefficient having the inverse characteristic to the digital modulation signal that is twice oversampled at a timing shifted by 1/16 symbol timing from the ideal reception timing is (−4/16
T, -3 / 16T, -2 / 16T, -1 / 16T, 0, + 1 / 16T, +2/16
T, + 3 / 16T, + 4 / 16T).

The tap coefficient need not have a completely inverse characteristic with respect to ISI. For example, it is sufficient if the tap coefficient has such a characteristic that ISI can be removed only at the sampling point closest to the ideal reception timing. . FIG. 5B shows an example of nine types of tap coefficients stored in the filter tap table when a filter having characteristics as shown in FIG. 5A is used as the band limiting filter at the time of transmission.

The ISI elimination filter 401 subjects the digital I and Q signals to filtering processing for ISI elimination, and outputs the result to the vector operation circuit 403. A plurality of tap coefficients are supplied from the filter tap table 402, and a filtering process result corresponding to each tap coefficient is output. The known vector table 404 stores the complex conjugate vector of the known symbol sequence section inserted in the burst. For example, the known vector table 404 is configured by a memory such as a RAM and a ROM. In the present embodiment, transmission filtering, transmission path characteristics, IS
The complex conjugate vector of the vector subjected to the I elimination filtering is stored at an interval of twice oversampling.

The vector operation circuit 403 stores the input digital I and Q signal data and the known vector table 40
Then, a vector operation is performed using the known vector sequence stored in No.4. For example, the vector operation circuit 403 is configured by an arithmetic processing block configured by logic or a DSP. The calculation is performed using equation (1) in the first embodiment.

The operation result buffer 405 buffers the operation result of the vector operation circuit 403. For example, the operation result buffer 405 is configured by a memory such as a RAM or a FIFO buffer.

The timing estimating circuit 406 estimates the reception timing at a resolution finer than the oversampling interval, using the operation result of the received I and Q signals and the known vector sequence, and outputs the estimation result. Details of the operation will be described later.

The operation of the communication terminal having the above configuration will be described in detail. The I and Q signals are sampled at an oversampling rate twice the symbol rate,
A digital data string having a length of one burst or more is stored in the reception signal buffer 105. Here, as an example, it is assumed that the sampling timing is shifted by −2 / 16T from the ideal reception timing.

The ISI elimination filter 401 performs a filtering process on the digital I and Q signal data strings stored in the reception signal buffer 105 using each of the nine types of filters supplied from the filter tap table 402. . This processing result is output to the vector operation circuit 403. Of the nine filter tap coefficients used at this time, only the result obtained when the tap coefficient calculated based on the timing of -2 / 16T is used,
A signal from which I is ideally removed is output.
When other tap coefficients are used, ISI is not completely removed, and in some cases, a distortion component due to ISI is further superimposed by filtering.

The vector operation circuit 403 performs the same vector operation as the equation (1) in the first embodiment on each of the nine filtering results output from the ISI removal filter 401. This operation result is output to the operation result buffer 405.

Nine types of operation results output to the operation result buffer 405 are obtained for each sample timing. The timing estimation circuit 406 detects a calculation result having the maximum value from the calculation results stored in the calculation result buffer 405. In the unit of double oversampling, the value becomes maximum when data closest to the position where the known vector sequence is inserted in the burst is used. Furthermore, 8 calculated at that timing
Of the calculation results by the filter tap coefficients
When the filter tap coefficient based on the timing is used for 6T, the calculation result becomes the maximum value. Therefore, it can be estimated that the sample timing having the maximum value is shifted by −2 / 16T from the ideal sample timing.

As described above, according to the embodiment of the present invention, the most probable operation result is selected from various operation results filtered by changing the filter tap coefficient corresponding to the deviation from the ideal sample timing, A deviation from an ideal sample timing corresponding to the calculation result is obtained. This makes it possible to estimate the reception timing when receiving and demodulating the digitally modulated signal with higher accuracy than the oversampling resolution at the time of reception.

In the present embodiment, the case where equation (1) is used as a vector operation for obtaining the degree of correlation with a known vector sequence is described. However, as in the first embodiment, the present invention is not limited to this. is not.

The nine tap coefficients having a resolution of 1/16 symbol in the filter tap coefficient table assumed in the present embodiment are merely examples, and the symbol resolution is made finer in accordance with the desired timing accuracy. The number of tables to be prepared may be increased accordingly, the symbol resolution may be reduced, and the number of tables to be prepared may be reduced accordingly.

In the present embodiment, the reception band limiting filter is not particularly specified. That is, the received signal may be filtered at the IF unit in the receiving device or at a time before sampling, or may be stored in the receiving buffer and then filtered at the previous stage of the ISI removing filter. The characteristic of band limitation may be obtained from the characteristic of (1).

(Embodiment 3) In this embodiment, a case will be described in which the data portion of a received signal is demodulated at the timing obtained by the method of Embodiment 2.

FIG. 6 is a block diagram showing a configuration of a communication terminal apparatus provided with a receiving apparatus according to Embodiment 3 of the present invention. In the configuration shown in FIG. 6, except that a data buffer 601, a selection circuit 602, and a symbol determination circuit 603 are provided,
This is the same as the configuration shown in FIG. Therefore, in FIG. 6, the same parts as those in FIG. 4 are denoted by the same reference numerals as in FIG. 4, and the detailed description thereof will be omitted.

The data buffer 601 buffers a plurality of types of filtering processing results output from the ISI removal filter 401. For example, the data buffer 601 includes a memory for storing quantized data having a length of one burst or more, a FIFO buffer, and the like.

The selection circuit 602 selects and outputs one of a plurality of ISI removal filter output results based on the timing estimation result. Symbol determination circuit 603
Performs symbol determination of a digitally modulated signal using I and Q signal data. In the present embodiment, QPSK
Assuming a case where quasi-synchronous detection is performed on a modulated signal, after performing phase correction using vector data in a section where a known symbol is inserted in a reception burst, the IQ plane is divided into four regions. To determine the symbol.

The operation of the communication terminal having the above configuration will be described. Since the operation of estimating the reception timing with high accuracy is the same as that of the second embodiment,
An operation in the case where a demodulation operation is performed in the receiving apparatus using the timing estimation result will be described.

In the selection circuit 602, based on the timing estimation result supplied from the timing estimation circuit 406,
A filter output signal of a matching timing is selected from the nine types of filter outputs stored in the data buffer 601 and output to the symbol determination circuit 603. This filter output signal is in a state where the ISI component has been removed by an ideal tap coefficient. Therefore, by performing symbol determination on this signal by the symbol determination circuit 603, a normal symbol determination result is obtained.

As described above, according to the embodiment of the present invention, the timing is estimated with higher accuracy than the resolution of the oversampling at the time of reception, and the timing deviation assumed based on the obtained timing estimation result is considered. A signal subjected to ISI removal filtering by a filter tap coefficient is selected to determine a symbol. Thereby, even if the oversampling timing at the time of reception deviates from the ideal reception timing, more accurate symbol determination can be performed.

In this embodiment, the data buffer 601 for storing the output of the ISI elimination filter is provided at the position shown in FIG. 6. However, the present invention is not limited to this. A structure provided between the circuits 403 may be employed. Further, in the present embodiment, the modulation scheme is QPSK as an example, but the present invention is not limited to this, and various modulation schemes can be applied.

(Embodiment 4) In this embodiment, a case will be described where highly accurate timing estimation is performed using an ISI removal filter in the reception operation described in Embodiment 1.

FIG. 7 is a block diagram showing a configuration of a communication terminal apparatus provided with a receiving apparatus according to Embodiment 4 of the present invention. In the configuration of FIG.
2, except that an ISI removal filter 401 and a symbol determination circuit 701 are provided.
Therefore, in the configuration shown in FIG. 7, the same parts as in FIG. 1 are denoted by the same reference numerals as in FIG. The timing estimating circuit 109 is different from the first embodiment.
Has the same configuration and operation as the timing estimation circuit described in FIG. Also in the present embodiment, the timing estimation circuit 109 uses digital I and Q signals obtained by quadrature demodulation and twice oversampling,
The reception timing is obtained in the unit of 1/16 symbol.

The filter tap table 402 is the same as the filter tap table described in the seventh embodiment, and has a filter coefficient which is the inverse characteristic of ISI in which a received digital modulation signal is affected by band limitation at the time of transmission or influence on a transmission path. Is obtained in advance and stored as a readout table. Here, as with the filter tap table 402, tap coefficients having inverse characteristics with respect to a digital modulation signal that is twice oversampled at a timing shifted by 1/16 symbol timing with respect to an ideal reception timing, similarly to the filter tap table 402. Is (-4 / 16T, -3
/ 16T, -2 / 16T, -1 / 16T, 0, + 1 / 16T, + 2 / 16T, +3/1
(T = 6T, + 4 / 16T), and one tap coefficient is selected and output as needed.

The ISI elimination filter 401 subjects the digital I and Q signals to filtering processing for ISI elimination, and outputs the result to the symbol determination circuit 701. That is,
The digital I and Q signals are filtered by the ISI elimination filter 401 using the filter tap coefficients from the filter tap table 402, and the result is output to the symbol determination circuit 701.

The symbol determination circuit 701 performs symbol determination of a digitally modulated signal using the I and Q signal data. In this embodiment, it is assumed that a quasi-synchronous detection is performed on a QPSK-modulated signal. After performing phase correction using vector data of a section in which a known symbol is inserted in a reception burst, an IQ plane The upper part is divided into four regions, and symbols are determined.

In the communication terminal having the above configuration,
The operation of estimating the reception timing with high accuracy is the same as that of the first embodiment. Here, the operation in the case where the demodulation operation is performed in the receiving apparatus using the timing estimation result will be described.

In the filter tap table 402, based on the timing estimation result output from the timing estimating circuit 109, an optimum filter tap coefficient is selected from nine stored filter tap coefficients, and I
Output to SI removal filter 401. For example, when the estimation result is that the timing estimation result is shifted from the ideal reception timing by −2 / 16T, a filter tap coefficient based on −2 / 16T is selected, and the filter tap coefficient is set to the ISI removal filter 401. Is output to

Since the ISI component has been removed from the result of the filtering process using the filter tap coefficients, a normal symbol determination result can be obtained by performing symbol determination on this signal in the symbol determination circuit 701.

As described above, according to the embodiment of the present invention, the timing is estimated with higher accuracy than the resolution of the oversampling at the time of reception, and the timing deviation assumed based on the obtained timing estimation result is considered. A signal subjected to ISI removal filtering by the filter tap coefficient is selected to determine a symbol. Thereby, even if the oversampling timing at the time of reception deviates from the ideal reception timing, more accurate symbol determination can be performed.

The receiving apparatuses according to Embodiments 1 to 4 are as follows.
All or part of the configuration may be configured as software using a DSP, a CPU, or the like. For example, the program for estimating the reception timing is stored in a ROM,
The program may be configured to operate according to an instruction from the CPU according to the program. Alternatively, the program for estimating the reception timing may be stored in a computer-readable storage medium, and the program in the storage medium may be recorded in the RAM of the computer, and may be operated according to the program. In such a case, the same operation and effect as those of the first to ninth embodiments are exhibited.

For example, a device storing a reception timing estimation program in a memory, wherein the reception timing estimation program estimates the timing of a received signal at a specific sample timing and outputs a third timing estimation result; Performing a timing estimation based on a correlation value ratio of a known signal between samples sampled at the sampling rate and the third timing estimation result, and outputting a fourth timing estimation result;
May be included.

Further, a memory for storing a reception timing estimating program and filter tap coefficients having characteristics of removing intersymbol interference from known signals in the received signal, which are sampled with a time unit finer than a specific sampling rate, are stored in a memory. The device, wherein the reception timing estimation program performs a procedure for performing filtering on the received signal using the filter tap coefficients to output a plurality of filtering results, and performs timing estimation based on the plurality of filtering results. And a procedure to be performed.

As described above, according to the present invention, A
The sampling period of the / D conversion circuit or the D / A conversion circuit can be reduced from that required from the system accuracy specification, and the current consumption and cost of the terminal can be reduced.

Further, according to the present invention, it is possible to estimate the reception timing when receiving and demodulating a digitally modulated signal with higher accuracy than the oversampling resolution at the time of reception.

In the first to fourth embodiments, the communication terminal device including the receiving device or the transmitting / receiving device according to the present invention has been described. Can also be mounted on the base station device.

[0106]

As described above, according to the present invention, it is possible to estimate the reception timing when receiving and demodulating a digitally modulated signal with higher accuracy than the oversampling resolution at the time of reception. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a communication terminal device including a receiving device according to Embodiment 1 of the present invention.

FIG. 2 is a diagram illustrating an example of a calculation result in the receiving device according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing another example of a communication terminal device including the receiving device according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a communication terminal device including a receiving device according to Embodiment 2 of the present invention.

5A is a diagram illustrating a transmission band limiting filter characteristic according to Embodiment 2 of the present invention. FIG. 5B is a diagram illustrating an ISI removal filter tap coefficient in the receiving apparatus according to Embodiment 2 of the present invention.

FIG. 6 is a block diagram showing a communication terminal device including a receiving device according to Embodiment 3 of the present invention.

FIG. 7 is a block diagram showing a communication terminal device including a receiving device according to Embodiment 4 of the present invention.

FIG. 8 is a diagram for explaining timing estimation in a conventional receiving apparatus.

[Explanation of symbols]

 Reference Signs List 101 Antenna 102 Quadrature detection circuit 103, 104 A / D conversion circuit 105 Received signal buffer 106 Known vector table 107 Vector calculation circuit 108 Calculation result buffer 109, 406 Timing estimation circuit 301 Propagation path estimation circuit 302 Calculation value ratio recalculation circuit 401 ISI Elimination filter 402 Filter tap table 403 Vector operation circuit 404 Known vector table 405 Operation result buffer 601 Data buffer 602 Selection circuit 603, 701 Symbol judgment circuit 1091 Low-precision timing estimation circuit 1092 High-precision timing estimation circuit 1093 Operation value ratio table 1094 Operation value Ratio judgment circuit

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jobmusya 3-10-1 Higashi-Mita, Tama-ku, Kawasaki-shi, Kanagawa F-term in Matsushita Giken Co., Ltd. 5J022 AA01 BA01 BA10 CA07 CA10 CE03 5K004 AA05 FA03 FE11 FG04 FH01

Claims (11)

[Claims] A first timing estimating unit for estimating a timing of a received signal at a specific sample timing and outputting a first timing estimation result; and a correlation value ratio of a known signal between samples sampled at the sampling rate. And a second timing estimating means for performing timing estimation based on the first timing estimation result and outputting a second timing estimation result. 2. The receiving apparatus according to claim 1, further comprising: a channel estimating unit for estimating a channel state; and an updating unit for updating the correlation value ratio based on the channel state. . 3. A storage means for storing filter tap coefficients each having a characteristic of removing inter-symbol interference from a known signal in a received signal, sampled at a time unit finer than a specific sampling rate, and said filter tap An inter-symbol interference filter that performs filtering on a received signal using a coefficient and outputs a plurality of filtering results, and a third timing estimation unit that performs timing estimation based on the plurality of filtering results. Characteristic receiving device. 4. The receiving apparatus according to claim 3, further comprising a demodulation unit that performs a demodulation process on data in the received signal using the timing estimation result obtained by the third timing estimation unit. . 5. A first timing estimating means for estimating a timing of a received signal at a specific sample timing and outputting a first timing estimation result, and a correlation value ratio of a known signal between samples sampled at the sampling rate. And a second timing estimating means for performing a timing estimation based on the first timing estimation result and outputting a second timing estimation result, and a known signal in the received signal sampled shifted by a time unit finer than a specific sampling rate. A storage means for storing filter tap coefficients each having a characteristic of removing intersymbol interference, and a filter tap coefficient selected by using a timing estimation result obtained by the second timing estimation means. Filtering and filtering results And an inter-symbol interference filter that outputs a signal. 6. A communication terminal device including a receiving device, wherein the receiving device estimates a timing of a received signal at a specific sample timing and outputs a first timing estimation result, Second timing estimating means for performing timing estimation based on a correlation value ratio of a known signal between samples sampled at the sampling rate and the first timing estimation result and outputting a second timing estimation result. A communication terminal device characterized by the above-mentioned. 7. A communication terminal device comprising a receiving device, wherein the receiving device removes inter-symbol interference from a known signal in a received signal sampled at a time unit finer than a specific sampling rate. Accumulating means for accumulating a filter tap coefficient having characteristics of performing filtering, an intersymbol interference filter for performing filtering on a received signal using the filter tap coefficient and outputting a plurality of filtering results, and based on the plurality of filtering results. And a third timing estimating means for performing timing estimation by using a communication terminal apparatus. 8. A device having a memory storing a reception timing estimation program, the reception timing estimation program performing timing estimation of a reception signal at a specific sample timing, and outputting a first timing estimation result. Performing a timing estimation based on a correlation value ratio of a known signal between samples sampled at the sampling rate and the first timing estimation result and outputting a second timing estimation result. Device. 9. A memory storing a reception timing estimation program and a filter tap coefficient having characteristics of removing inter-symbol interference with respect to known signals in a received signal, which are sampled with a time unit finer than a specific sampling rate. A device having
The reception timing estimation program includes: a step of performing filtering on a reception signal using the filter tap coefficients to output a plurality of filtering results; and a step of performing timing estimation based on the plurality of filtering results. A device, characterized in that: 10. A first timing estimation step of performing timing estimation of a received signal at a specific sample timing and outputting a first timing estimation result, and a correlation value ratio of a known signal between samples sampled at the sampling rate. And a second timing estimation step of performing timing estimation based on the first timing estimation result and outputting a second timing estimation result. 11. An accumulating step of accumulating filter tap coefficients each having a characteristic of removing intersymbol interference from a known signal in a received signal, sampled at a time unit finer than a specific sampling rate, and said filter tap A filtering step of performing filtering on a received signal using a coefficient to output a plurality of filtering results, and a third timing estimating step of performing timing estimation based on the plurality of filtering results. Timing estimation method.