JP3502397B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used in a large scale integrated circuit.

[0002]

2. Description of the Related Art A large-scale integrated circuit is manufactured by integrating many semiconductor elements, and by increasing the degree of integration, the speed of circuit operation is improved, the reliability is improved, and the manufacturing cost is reduced. Hitherto, high integration has been achieved by miniaturizing individual semiconductor elements constituting an integrated circuit, and has been realized by integrating a large number of fine semiconductor elements having uniform element characteristics with the development of precision fine processing technology. It was

As an element structure for realizing high performance of a fine semiconductor element, instead of a structure for forming a MIS type semiconductor element on a semiconductor substrate, that is, a bulk MIS structure, a MIS type semiconductor element is formed on a semiconductor layer on an insulating film. Has been proposed, ie a SOIMIS structure. Field effect transistor with SOIMIS structure (SOIMISFET)
Then, the thickness (tsoi) of the semiconductor layer is set to a field effect transistor (bulk MISFET) having a bulk MIS structure.
By making it thinner than the maximum depletion layer width (dmax) in the channel inversion layer.
It has been considered that the size can be reduced as compared with the case of ET, the mobility of the inversion layer carrier can be made higher than that of the bulk MISFET, and a high-speed large-scale integrated circuit can be realized.

Among the precision microfabrication techniques, impurities used for optimizing the electrical characteristics of semiconductor elements used in integrated circuits are given their concentration distribution by thermal diffusion accelerated by ion implantation or heating, Since the processing technology itself is based on a statistical process, it is inevitable that the concentration value has statistical fluctuation. In the conventional large-scale integrated circuit using the bulk MISFET, the statistical fluctuation of the impurity concentration is not large enough to affect the device operation, and the electrical characteristics of the semiconductor device are less affected by the statistical fluctuation. The ratio of the variation of the threshold voltage in the current-voltage characteristic to the reading margin value of the signal reading element in the integrated circuit was also a negligible value. However, as the scale of integrated circuits has increased and the miniaturization of semiconductor devices has progressed, the size of a single device has become extremely small, and the number of impurities giving an impurity distribution in the device has been decreasing. For this reason, it is necessary to design the structure of the fine semiconductor element in consideration of the influence of the statistical variation of the impurity concentration on the electrical characteristics of the semiconductor element according to the element structure.

Although the influence of the statistical fluctuation of the impurity concentration on the electrical characteristics, particularly the threshold voltage, in the fine semiconductor device having the SOIMIS structure has not been clarified hitherto, the fluctuation caused by the fluctuation in the threshold voltage has a bulk MIS structure. by according it became clear that even greater than in the case of fine semiconductor devices, the following SOIMI
It has become possible to provide a fine semiconductor device having an S structure. You
That is, the semiconductor layer of a predetermined thickness formed on the insulating film
A pair of high-concentration impurity diffusions separated by a fixed distance
Region and gate on the channel region sandwiched by the diffusion region
MI having a gate electrode formed through an insulating film
In the S-type semiconductor device, many MIS-type semiconductor devices are used.
The current-voltage characteristics of the MIS type semiconductor device when individually created
The variation of the threshold voltage in the semiconductor layer depends on the impurity concentration of the semiconductor layer.
Provided on a semiconductor substrate having the same impurity concentration as
A pair of high-concentration impurities separated by the same distance
An object diffusion region and the channel region sandwiched by the diffusion region
Through the gate insulating film on the channel area with the same area
MIS type semiconductor device having a formed gate electrode
Same or smaller than variation in threshold voltage
MIS-type semiconductor device including a semiconductor layer having a predetermined thickness
And more preferably, the thickness tsoi of this semiconductor layer is
The condition of the formula (1) is satisfied.

[Equation 1] Here, dmax is the maximum chirp in the bulk MISFET.
Channel depletion layer width, L is channel length, W is channel width, N
A is the impurity concentration of the substrate or the semiconductor layer. dmax
Is given by the following equation (2). However, εsi is the substrate or
Is the dielectric constant of the semiconductor layer, and φs is the substrate surface after channel formation.
And q is the elementary charge.

[Equation 2] Generally, the threshold voltage Vth of the MISFET is expressed by the following equation. Vth = qφ's + Vox + Vfb (3) where Vox = tox · Eox (4) where Vox is the potential difference generated in the oxide film,
Vfb is the flat band voltage, φ's is the potential difference generated on the substrate surface when the gate voltage changes from the flat band state to the threshold voltage, tox is the gate insulating film thickness, and Eox is the gate insulating film at the threshold voltage. Is the electric field. The magnitude of the threshold voltage variation between the bulk MISFET and the SOIMISFET is as long as the substrate impurity concentration of the bulk MISFET and the impurity concentration of the semiconductor layer of the SOIMISFET are the same and the gate insulating film thickness is the same (4 ) Can be evaluated in the Eox part. Eo
x is

[0006]

[Equation 3] Is expressed as Here, εox is the dielectric constant of the gate insulating film. The magnitude of the fluctuation of NA is proportional to the square root of NA,
It is inversely proportional to the square root of the volume of the channel depletion layer. Due to the variation of NA, bulk MISFET and SOIM
In any case of the ISFET, the threshold voltage varies. However, its dependence on the value of NA is different. In the case of the bulk MISFET, dmax also depends on NA, and dmax is expressed by equation (2). That is, d
max decreases with increasing NA. Therefore, bulk M
In ISFET, when NA increases due to statistical fluctuation, d
The decrease in max suppresses the increase in Eox. When NA decreases, dmax increases and Eox decreases. On the other hand, in the case of SOIMISFET, ts
The magnitude of oi is constant regardless of NA, and the fluctuation of NA causes the variation of Eox with the same magnitude.
The variation of Eox is multiplied by tox, resulting in variation of the threshold voltage. In the SOIMIS structure semiconductor element, a structure for suppressing the variation given to the fluctuation threshold voltage is particularly necessary.

[0007]

The object of the present invention is to reduce the SO
Clarifying the conditions to be satisfied by the structure of the SOIMIS structure semiconductor element so as to reduce the influence of the statistical fluctuation of the impurity concentration in the IMIS structure semiconductor element on the electrical characteristics of the semiconductor element, a semiconductor device having such a condition is provided. The purpose of the present invention is to realize a semiconductor device having a SOIMISU structure having sufficiently uniform electric characteristics for realizing a large scale integrated circuit.

[0008]

In order to solve the above problems, the present invention provides a semiconductor layer formed on an insulating film, and a semiconductor layer formed on the semiconductor layer.
A source region and a drain region formed in the body layer;
Impurities formed between the source region and the drain region
With a channel region having a material concentration of 1 × 10 ¹⁸ (cm ⁻³ ),
4 nm thick gate insulating film formed on the channel region
And a gate electrode formed on this insulating film.
Of the gate electrode of the channel through the gate insulating film
The area of the region facing the region is 10 ⁴ nm ² ,
The thickness of the channel region is 10 nm or less,
And a more preferable structure,
The channel length and channel width of the channel region are 0.1 μm
A semiconductor device characterized by the above. Also, FIG.
The basic characteristics of the structure of the SOIMIS structure semiconductor device that realizes the effects of the present invention are shown in FIG. 2 is the SOIMIS of FIG.
FIG. 3 shows a conventional SOIMIS structure semiconductor device corresponding to the structure semiconductor device, and FIG. 3 shows a bulk MIS structure semiconductor device corresponding to the SOIMIS structure semiconductor devices of FIGS. 1 and 2.

In order to achieve the above-mentioned object, the semiconductor device of the present invention is a single SOIMISFFE having an SOIMIS structure.
At T, depending on the impurity concentration of the channel portion 15 of the semiconductor layer and the area of the channel portion, the semiconductor layer 12
Of the maximum depletion layer width dma in the bulk MISFET having the same L, W and NA as the SOIMISFET.
It is sufficiently thinner than x, and the magnitude of the threshold voltage variation due to the statistical variation of the impurity concentration is larger than that of the bulk MISF.
It is characterized by being smaller than the case of ET.

[0010]

The variation of the threshold voltage in SOIMISFET is expressed by the following equation.

[0011]

[Equation 4]

As can be seen from (7), SOIMISF
The smaller the tsoi, the smaller the variation in the threshold voltage at ET becomes. In FIG. 4, L = W = 0.1 μm, tox = 4n
m, substrate concentration 1 × 10 18 cm -3, SOIMIS
It shows the dependence of the threshold voltage variation of the FET on t soi. The magnitude of the threshold voltage variation of the bulk MISFET is also shown by the dotted line in the figure. tsoi is dm
In a wide region close to ax, the threshold voltage variation of the SOIMISFET is larger than the threshold voltage variation of the bulk MISFET, and the conventional SOIMISFET structure cannot realize a MISFET having a small threshold voltage variation.

FIG. 5 illustrates the variation of the threshold voltage using the band diagram of the channel portion of the SOIMISFET of FIG. FIG. 6 shows a conventional SOIMISFET using the channel band structure of the SOIMISFET of FIG.
This is a description of the variation in the threshold voltage at. The operation of the present invention for suppressing the threshold voltage variation will be described with reference to FIGS. 5 and 6.

At the channel surface 51 in FIG. 5, which is the channel band structure of the SOIMISFET in FIG. 1,
A variation δEox of the electric field Eox, that is, 53 is generated due to the variation of the space charge amount due to the variation of the impurity distribution in the channel depletion layer portion 52. The variation of Eox is multiplied by tox through the gate insulating film portion 54, and the variation δVox of potential drop δVox in the insulating film, that is, 55 is generated, and combined with the variation δφ of potential on the channel surface 51,
Variation δVt of the threshold voltage Vth in the gate electrode portion 56
has occurred h. On the other hand, as shown in FIG.
In the case of the IMISFET, the channel depletion layer portion 62 is formed due to the thick channel depletion layer portion 25 formed by the thick semiconductor layer 22.
Has a large space charge amount, which causes a large Eox variation 63, which is caused by the tox via the gate insulating film portion 64.
Multiplied by a large variation of the potential drop in the insulating film δVo
x65, which causes a large variation in threshold voltage. In the SOIMISFET of FIG. 1, due to the action of using the thin semiconductor layer, a small δVox is generated and a small threshold voltage variation is generated.

The smaller the tsoi, the smaller the variation in the threshold voltage. In order to suppress the variation in the threshold voltage, it is necessary to prevent the circuit operation from being disturbed. The tsoi is sufficiently thin according to the magnitude of the variation in the threshold voltage. It is necessary to use.

From FIG. 2, it is necessary to use tsoi thinner than 10 nm in the SOIMISFET in this case in order to realize a variation smaller than the threshold voltage variation in the case of the bulk MISFET. SOI that gives a variation smaller than the threshold voltage variation of a bulk MISFET for arbitrary L, W, and NA
It is given by the condition (1) for tsFET of MISFET.

FIG. 7 shows tsoi when the threshold voltage variation δVth due to the fluctuation of the impurity distribution in the case of L = W = 0.5 μm is made equal to or smaller than the threshold voltage variation in the bulk MOSFET. Upper limit t
The NA dependence of soi (c) is determined by the SOI of tox = 20 nm.
It is shown about MOSFET. tsoi
(c) By using the following semiconductor layer thickness, bulk M
In case of OSFET, SOIMISF having the following δVth
ET can be realized.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention.
In the embodiment shown in FIG. 1, a silicon layer 1 having a thickness of 40 nm and a boron concentration of 1 × 10 16 cm −3 is formed on the silicon dioxide layer 11.
2, a pair of high-concentration arsenic regions are provided at a distance of 0.5 μm from each other, and a source region 13 and a drain region 14 are provided.
And a channel region 15 having a channel length of 0.5 μm is formed. A gate electrode 17 is provided on the channel region 15 sandwiched between the source region and the drain region with a 20 nm gate insulating film 16 interposed therebetween. A device isolation region 18 made of silicon dioxide having a thickness of 400 nm is provided so as to surround a device region made up of a channel portion, a source portion, and a drain portion so as to form a channel width W = 0.5 μm. In the embodiment of FIG. 1, the thickness of the silicon layer required to sufficiently reduce the variation in the threshold voltage, which is determined by the impurity concentration of the channel portion, the channel length, the channel width, and the thickness of the gate insulating film, is set. SOI used
A MISFET is formed. Bulk MISF in Figure 3
The fluctuation of the threshold voltage due to the fluctuation of the impurity distribution in ET is about 10 mV, which is small, but the fluctuation of the threshold voltage due to the fluctuation of the conventional SOIMISFET of FIG. 2 is about 15 mV, and the bulk MISF is large.
Greater than for ET. The SOIMISFET using the sufficiently thin semiconductor layer of FIG. 1 realizes a smaller threshold voltage variation than that of the bulk MISFET,
The variation in threshold voltage is suppressed to about 8 mV.

[0020]

As described above, according to the present invention, it is possible to realize the SOIMISFET in which the variation in the electrical characteristics of the semiconductor element used in the large-scale integrated circuit has a sufficiently small value that does not hinder the circuit operation. it can.

[Brief description of drawings]

FIG. 1 is an embodiment of the present invention, an SOI having a semiconductor layer that is thin enough to provide small threshold voltage variations.
The figure which showed MISFET.

FIG. 2 is a diagram showing a structure of a SOIMISFET.

FIG. 3 is a diagram of a bulk MISFET corresponding to the SOIMISFETs of FIGS. 1 and 2.

FIG. 4 L = W = 0.1 μm, tox = 4 nm, NA
= 10 ¹⁸ cm ^-3, the dependence of the threshold voltage variation on the semiconductor layer thickness tsoi in the case of SOIMISFET is shown by a solid line, and the dotted line shows the magnitude of the threshold voltage variation in the case of a bulk MISFET.

5 is a band diagram in the depth direction of the channel substrate for explaining the magnitude of variation in threshold voltage in the SOIMISFET of FIG.

6 is a band diagram in the depth direction of the channel substrate for explaining the magnitude of variation in threshold voltage in the conventional SOIMISFET shown in FIG.

FIG. 7: SOIMIS when L = W = 0.5 μm
The figure which shows the channel impurity concentration dependence of the upper limit of the semiconductor layer thickness such that the variation in the threshold voltage of the FET becomes smaller than that in the case of the bulk MISFET, in the case of tox = 20 nm.

[Explanation of symbols]

11 ... Insulator layer 12 ... Semiconductor layer 13 ... Source 14 ... Drain 15 ... Channel 16 ... Gate insulating film 17 ... Gate electrode 18 ... Element isolation region 21 ... Insulator layer 22 ... Semiconductor layer 23 ... Source 24 ... Drain 25 ... Channel 26 ... Gate insulating film 27 ... Gate electrode 28 ... Element isolation region 32 ... Silicon substrate 33 ... Source 34 ... Drain 35 ... Channel 36 ... Gate insulating film 37 ... Gate electrode 38 ... Element isolation region 39 ... Channel depletion layer edge 51 ... Channel depletion layer substrate surface 52 ... Channel depletion layer 53 ... Variation in electric field in gate insulating film 54 ... Gate insulating film portion 55 ... Variation in potential drop of gate insulating film 56 ... Gate electrode part 61 ... Channel depletion layer substrate surface 62 ... Channel depletion layer portion 63 ... Electric field variation in gate insulating film 64 ... Gate insulating film part 65 ... Variation in potential drop in gate insulating film 66 ... Gate electrode part

Claims (2)

(57) [Claims] 1. A semiconductor layer formed on an insulating film, and a source region and a drain region formed on the semiconductor layer.
And between the source region and the drain region
A channel region having an impurity concentration of 1 × 10 ¹⁸ (cm ⁻³ ) and a gate region having a thickness of 4 nm formed on the channel region are isolated.
An edge film and a gate electrode formed on the insulating film, and the channel of the gate electrode via the gate insulating film.
The area of the region facing the channel region is 10 ⁴ nm ² , and the thickness of the channel region is 10 nm or less.
Semiconductor device to collect. 2. The channel length and channel of the channel region
The ruled width is 0.1 μm.
Semiconductor device.