JP3489673B2 - Integrated process RTL description generation method - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an integrated process RTL.
Regarding the description generation method, in particular, from the behavior description of a process to the RTL (Register Transfer L) of the process.
and an integrated process RTL description generation method in high-level synthesis for generating a description.

[0002]

2. Description of the Related Art High-level synthesis is conversion of hardware specifications described at a behavioral level in a behavioral description language into RTL description while maintaining consistency (for high-level synthesis, McFarland et al. Tutoria
l on High-level Synthesis ",
Processedings of 25th ACM / IE
EE Design Automation Con
f. , 1988, and Devadas et al., "Algori."
thms For Hardware Allocati
on in Data Path Synthesis ",
IEEE Trans. onCAD, Vol. 8, N
o. 7, 1989). In a behavioral description language, a unit that performs a certain series of behaviors is called a process, and generally, a set of processes constitutes the entire circuit.

Data exchange between cooperating processes includes a method of directly passing a signal and a method of passing a signal through a register or a memory. The former requires the transmitter and the receiver to be completely synchronized, which complicates the design, while the latter does not need to be completely synchronized.
It is practical because data can be exchanged by simple control such as reading. Here, the register used for data exchange is called a shared register.

The shared register is a register shared between processes, and when writing is simultaneously performed by a plurality of processes, some kind of exclusive control is required. Generally, there are methods such as completely coordinating related processes so that simultaneous writing never occurs, or methods in which each process performs its own write right acquisition judgment processing. Was burdened by a lot of people.

For example, in Japanese Patent Laid-Open No. 11-213024, a variable which is not processed at the same timing is searched from the behavioral description, and when the number of bits of the variable is insufficient with respect to the number of bits of the register to be shared, a code is added. A method is described in which the same data as the sign bit is added to the variable of No. and the same data as the sign bit is given to the variable of no sign, and the specified data is added to the variable without sign, and then the register is shared. Has been done. However, although this method shares registers, it is not intended for exclusive control and cannot prevent simultaneous writing from occurring.

[0006]

The problem of the above-mentioned conventional technique is that a great burden is imposed on the designer in order to prevent simultaneous writing from occurring at the time of data exchange using the shared register. That is to say. The reason is that the designer needs to design so that the related processes are perfectly coordinated, or that each process performs its own write right acquisition determination processing.

An object of the present invention is to automatically create an RTL description that implements exclusive control with priority when writing to a shared register by incorporating two priorities, a static process priority and a dynamic write priority level. Integrated process R designed to improve design efficiency
It is to provide a TL description generation method.

Another object of the present invention is to automatically generate an RTL description that implements exclusive control with priority when writing to a shared register by incorporating two priorities, a process priority and a write priority level. Shared register exclusive control R designed to improve design efficiency
It is to provide a TL description generation method.

[0009]

The integrated process R of the present invention
The TL description generation method divides the behavioral description of a process into behavioral descriptions of each process and
The create request signal writes <br/> If a write description part of the shared register, before writing to shared register
Change to issue a write request signal to the process
If the write priority level is specified in the behavior description of
If a write request signal is set to a write priority level and issued, a process conversion means for changing the write description part to the shared register and the process divided by the process conversion means and changed. High-level synthesis means for converting the behavioral description into the RTL description of each process, and reading the shared register name and process priority order for analysis
Of the shared register name and writing to the shared register
Generate process priority as process priority list
Was divided and changed by the process conversion means.
The behavior description of each process is read, and each process actually
Extract which shared register you are writing to
Generate a shared register list for each process and
Refer to the shared register list for each
From the process priority list for each
Redundancy removed by removing processes that do not write to
Only process priority list is generated and the redundancy is removed.
A shared register processing unit that compares shared write priority levels of write request signals in the order of process priority according to the process priority list and generates a shared register exclusive control RTL description that exclusively controls writing to the shared register.
RTL integration means for integrating the RTL description of each process and the shared register exclusive control RTL description to generate an integrated process RTL description.

Further, in the integrated process RTL description generation method of the present invention, the shared register processing unit reads and analyzes the shared register name and the process priority , and the shared register
Process priority for writing to the stack name and shared register
A process priority analysis means for generating a priority as a process priority list, divided by the process conversion unit
And read the behavior description of each changed process,
Which shared register the process actually writes to
Extract the squid and generate a shared register list for each process.
A shared register write process analysis means for forming, the
Refer to the shared register list for each process to share
From the process priority list for each register,
Redundant by eliminating the process that does not write to the register
Generate a list of removed process priorities and
A shared register RT that generates a shared register exclusive control RTL description that exclusively controls write to the shared register by comparing the write priority levels of the write request signals in the order of process priority according to the removed process priority list.
And L output means.

Further, according to the integrated process RTL description generation method of the present invention, the behavioral description of a process is divided into behavioral descriptions of each process, and if there is a write description part in a shared register in the behavioral description of a process, it is written. Create request signal and write before writing to shared register
Only the request signal is issued, and the process operation record is changed.
Write if the write priority level is specified in the description
Set the priority level for writing to the request signal and issue
And a high-level synthesis means for converting the behavioral description of each process divided and modified by the process conversion means into the RTL description of each process, and the shared register name. And process priorities are read and analyzed and shared
Process name for register name and write to shared register
The process priority analysis means for generating the priorities as a process priority list and the process conversion means
Read the behavior description of each process that has been split and changed,
Which shared register each process actually writes to
The common register list for each process
A shared register write process analysis unit to be generated, before
Refer to the shared register list for each process
Yes Shared from the process priority list for each register
Remove the process that does not write to the register
Generate a long-removed process priority list for redundancy
Shared register R for generating a shared register exclusive control RTL description for exclusive control of writing to the shared register by comparing the write priority levels of write request signals in the order of process priority according to the removed process priority list
It is characterized by having TL output means and RTL integration means for integrating the RTL description of each process and the shared register exclusive control RTL description to generate an integrated process RTL description.

Further, according to the shared register exclusive control RTL description generation method of the present invention, the shared register name and the process priority are read and analyzed, and the shared register name and the process priority are analyzed.
Process priority analysis means for generating the process priority order of writing to the shared register as a process priority order list , and the process priority conversion means for dividing and changing the process priority order.
The behavior description of each process
At which shared register is being written
And a shared register writing process analyzing means for generating a shared register list for each process, and
For each shared register, refer to the shared register list.
Actually write to the shared register from the process priority list
Remove redundant processes to eliminate redundant processes
Process priority list and generate the redundant-removed process.
Shared register RTL output means for generating a shared register exclusive control RTL description for exclusive control of writing to the shared register by comparing the write priority levels of the write request signals in the order of process priority according to the priority list. Characterize.

[0013]

[0014]

The computer-readable recording medium of the present invention divides the behavior description of a process into behavior descriptions of each process in the computer, and further describes the behavior description of the process.
If there is a written description portion of the share register during the predicate
Create a write request signal is written to the shared register
Change to issue a write request signal before
There is a write priority level specified in the behavior description of the process.
Write request to the shared register so that the write request signal is issued with the write priority level set.
A process converting means for changing the minutes, and a high-level synthesizing means for converting the behavioral description of each process divided and changed by the process converting means into the RTL description of each process,
Solution reads the shared register name and process priority
And write to shared register name and shared register
Process priorities as a process priority list
And is divided and changed by the process conversion means.
The behavior description of each process is read, and each process is actually
Which shared register is being written to
To generate a shared register list for each process,
Refer to the shared register list for each process
From the process priority list for each star, it is actually a shared register
Redundant processes by removing the processes that do not write
Generated process priority list and removed redundancy
A shared register processing unit that compares shared write priority levels of write request signals in order of process priority according to the process priority list to generate a shared register exclusive control RTL description for exclusive control of writing to the shared register, and each of the processes. The RTL description and the shared register exclusive control RTL description are integrated, and a program for functioning as an RTL integrating means for generating an integrated process RTL description is recorded .

The computer-readable recording medium of the present invention divides a computer operation description into process operation descriptions, and at the same time , a process operation description.
If there is a written description portion of the share register during the predicate
Create a write request signal is written to the shared register
Change to issue a write request signal before
There is a write priority level specified in the behavior description of the process.
Write request to the shared register so that the write request signal is issued with the write priority level set.
A process converting means for changing the minutes, and a high-level synthesizing means for converting the behavioral description of each process divided and changed by the process converting means into the RTL description of each process,
Solution reads the shared register name and process priority
And write to shared register name and shared register
Process priority analysis means for generating the process priority order of the above as a process priority list , and the process conversion
Behavior description of each process divided and changed by means
And each process actually writes to which shared register
Shared cash register for each process by extracting whether or not
Refer to the shared register writing process analysis means for generating a star list and the shared register list for each process
The process priority list for each shared register
Process that does not actually write to the shared register.
Generates a process priority list that has been stripped to remove redundancy
Then, according to the redundancy-removed process priority list, the write priority levels of the write request signals are compared in the order of process priority order to generate a shared register exclusion control RTL description for exclusive control of writing to the shared register. Shared register RTL output means and RTL of each process
It is characterized in that a program is recorded for causing the description and the shared register exclusive control RTL description to be integrated to function as an RTL integration means for generating an integrated process RTL description.
And

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(1) First Embodiment FIG. 1 is a block diagram showing the configuration of an integrated process RTL description generation system according to the first embodiment of the present invention. The integrated process RTL description generation method according to the present embodiment is
A data processing device (computer) 1 that operates by program control and a storage device 2 that stores information form the main part thereof.

The data processing device 1 includes process conversion means 1
0, high-level synthesis means 11, process priority analysis means 12, shared register writing process analysis means 13
And a shared register RTL output means 14 and an RTL integration means 15. The process priority analysis means 1
2, the shared register writing process analysis unit 13 and the shared register RTL output unit 14 form a shared register processing unit.

The storage device 2 has a shared register name / process priority 21, a process behavior description 22, an internal table 23, a process RTL description 24, a shared register exclusive control RTL description 25, and an integrated process RTL description. 26 and are stored. The process behavior description 22 is
Behavioral descriptions 22A, 22B of each process A, B, C, D,
22C, 22D, RTL description of process 24
Is the RTL description 24A, 2 of each process A, B, C, D
It consists of 4B, 24C and 24D.

Referring to FIG. 2, in the process of the integrated process RTL description generation method according to the first embodiment, a process division / modification step S1, an RTL description conversion step S2, a shared register name and a process priority order. It comprises an analysis step S3, a shared register write process analysis step S4, a redundancy removal step S5 from the process priority list, a shared register exclusive control RTL description output step S6, and an RTL description integration step S7.

Shared register name / process priority 21
Consists of the shared register name and the process priority of the process that may write to the shared register.
The process priority is a static priority given to the writing process for each shared register preset by the designer.

FIG. 3 is a diagram showing an example of the shared register name / process priority 21. In this example, procA,
This is a case where there are four processes procB, procC, procD and four shared registers Reg1, Reg2, Reg3, Reg4, and the process priority is procB>procC>procA> proc.
The order is cD.

The process behavior description 22 is a description of each process A, B, C, D at the behavior level.
Every time a designer writes to a shared register in the behavioral description 22 of a process, the designer, if necessary, writes a dynamic priority when the process actually goes to write data to the shared register. You can specify the time priority level.

FIG. 4 is a diagram showing an example of the behavioral description 22 of the process. In this example, a plurality of processes A, B, C, D
The behavior description of is summarized. The shared register needs to be declared by an extern statement in the behavioral description 22 of the process. For example, procA represents writing to the shared registers Reg1 and Reg2.

The shared register name / process priority 21 and the process behavior description 22 may be integrated into one file.

The process converting means 10 reads the operation description 22 of the process and divides it into individual files as the operation descriptions 22A, 22B, 22C and 22D of the processes A, B, C and D, respectively. At the same time, the process conversion means 10
Changes the part of the description written to the shared register.
Specifically, a write request signal to the shared register is newly created, and the operation description 22 of each process A, B, C, D is created.
It is inserted in the write description part of A, 22B, 22C and 22D. Further, when the write priority level is designated, the process conversion means 10 sets the write request signal to the write priority level. It should be noted that the process behavior description 22 is the behavior description 22A of each process A, B, C, D.
The division into 22B, 22C, and 22D is performed because the high-level synthesis means 11 performs synthesis in process units.

FIG. 5 shows the behavioral description 22A of the process A.
It is a figure which shows an example before the change of the write description part to a shared register.

FIG. 6 shows the behavioral description 22A of the process A.
It is a figure which shows an example after the conversion of the write description part to a shared register.

The high-level synthesis means 11 is the process conversion means 1
Each process A, B, C, divided and modified by 0
Each of the behavioral descriptions 22A, 22B, 22C, and 22D of D is read one by one, and each process A having the same logic inside,
B, C, D RTL descriptions 24A, 24B, 24C, 24
Convert to D and output.

RTL description 2 of each process A, B, C, D
4A, 24B, 24C, and 24D are operation descriptions 22A and 2 of the processes A, B, C, and D by the high-level synthesis means 11.
2B, 22C and 22D are the results converted into the RTL description.

FIG. 7 is a diagram showing an example of the RTL description 24A of the process A. RTL description 24A of process A
Are described in the form of state transition, LOCK_and_WT indicates a write right acquisition and write phase, and RELEASE indicates a write right release phase. Both cannot be executed at the same time, so it is divided into two phases.

The process priority order analysis means 12 reads the shared register name / process priority order 21, analyzes the process priority order described in a specific format, and stores it in the internal table 23 as a process priority order list for each shared register. To do.

Shared register writing process analysis means 1
3 is the behavioral description 22A, 22 of each process A, B, C, D divided and modified by the process conversion means 10.
B, 22C, 22D are read, and each process A, B,
Internal table 2 is used as a shared register list for each process by analyzing the shared registers that C and D actually write.
Save to 3. Further, the shared register writing process analysis unit 13 refers to the shared register list for each process, deletes the process that does not actually write to the shared register from the process priority list for each shared register, and eliminates redundancy. It is stored in the internal table 23 as a priority list.

The internal table 23 temporarily stores the shared registers, the processes that actually write to the shared registers, and the priorities of these processes as a process priority list for each shared register. Further, the internal table 23 temporarily stores the process name and the shared register name written by the process as a shared register list for each process.

The shared register RTL output means 14 refers to the shared register list for each process and the redundancy-removed process priority list for each shared register stored in the internal table 23, and outputs the write request signals in the order of process priority. A shared register exclusive control RTL description 25 is generated which compares the write priority levels and exclusively controls the writing to the shared register.

The shared register exclusive control RTL description 25 is
The shared register RTL output means 14 outputs an RTL description for performing exclusive control of writing to the shared register based on the shared register list for each process and the process priority list for each shared register in the internal table 23. . Shared register exclusive control RTL description 25
Compares the write priority levels of the two processes and performs exclusive control so that the data of the process having the higher write priority level is written to the shared register. When the priority levels at the time of writing are the same, the write request signal of the process having the higher process priority is accepted, and exclusive control is performed so that the data from the process having the higher process priority is written to the shared register.

FIG. 8 shows an example of the shared register exclusive control RTL description 25 in the shared register Reg1 of the processes A, C and D (process priority C>A> D) (Ve in this case).
(using rilog HDL). Note that process B
Assumed that the shared register Reg1 is not written. In FIG. 8, Reg1_procA0,
Reg1_procC0, Reg1_procD0
Is a write request signal, and is a signal issued by each of the processes A, C, and D to obtain the right to write before directly writing to the shared register Reg1. The write request signal has a write priority level represented by an integer of 0 or more. When 0, there is no write request, and when 1 or more, the higher the value, the higher the priority.

The RTL integrating means 15 includes the processes A,
B, C, D RTL descriptions 24A, 24B, 24C, 24
D and shared register exclusive control RTL description 25 are integrated,
Output as the integrated process RTL description 26.

The integrated process RTL description 26 is the RTL of each process A, B, C, D by the RTL integrating means 15.
The descriptions 24A, 24B, 24C and 24D and the shared register exclusive control RTL description 25 are integrated.

FIG. 9 is a diagram showing an example of the integrated process RTL description 26 for the shared register Reg1. This integrated process RTL description 26 is the RTL of process A.
It is composed of a description part and a shared register exclusive control RTL description part.

FIG. 10 is a diagram showing an example of a circuit image of the integrated process RTL description 26. In this example, the shared register exclusive control R in which the shared register Reg1 is described
There are a circuit of the TL description 25, an RTL description 24A of the process A, an RTL description 24C of the process C, and a circuit of the RTL description 24D of the process D that write to the shared register Reg1. RTL description 24 of process A
When there is a write request signal to the shared register Reg1 from each circuit of the RTL description 24C of A, the process C, and the RTL description 24D of the process D, the circuit of the shared register exclusive control RTL description 25 performs exclusive control, and the write priority Considering the level and process priority, the data from the process with the higher priority is shared by the register Reg1.
Write in.

Next, the operation of the integrated process RTL description generation method according to the first embodiment configured as described above will be described in detail with reference to FIGS.

First, the process converting means 10 reads the behavioral description 22 of the process, and the behavioral description 22 of the read process is the behavioral description 22 of each process A, B, C, D.
It is divided into A, 22B, 22C and 22D. At that time, when the operation description 22 of the process includes a write description part to the shared register, the process conversion means 10 creates a write request signal and issues a write request signal before writing to the shared register. To do. Further, the process conversion unit 10 sets the write priority level in the write request signal and issues the write request signal when the write priority level is specified in the process behavior description 22. Is changed (step S
1).

For example, the process converting means 10 is shown in FIG.
The behavioral description 22A of the process A illustrated in FIG. 6 is changed to the behavioral description 22A of the process A illustrated in FIG. In the operation description 22A of the process A illustrated in FIG. 5, since the shared registers Reg1 and Reg2 are declared, the description portion "Reg1: = AA" for writing the data AA in the shared register Reg1 is "/ * LVL.
The write priority level is set to 3 by the description part "= 3 * /". Therefore, the process conversion means 10 uses the shared register declaration description part of the shared register name / process priority 21 illustrated in FIG. As shown in FIG. 6, a write request signal Reg1_procA0 that requests writing to the shared register Reg1 and a write data signal Reg1 that is the write data itself.
Create _procA. When writing, the priority level is
It is reflected in the write request signal Reg1_procA0. Here, since the write priority level is set to 3, the write request signal Reg1_procA
A description part that puts 3 into 0 "Reg1_procA0:
= 3; "is generated. When writing to the shared register Reg1, first, the write priority level 3 designated in the write request signal Reg1_procA0 is set, and the data is written to the write data signal Reg1_procA. The data writing is completed. Then, the write request signal Reg1_procA0 is set to 0, and the shared register R
Release eg1 to another process.

Next, the high-level synthesis means 11 uses the respective process A divided and changed by the process conversion means 10.
Behavioral description 22A, 22B, 22C, 22D of B, C, D
Is read and the operation description is converted into the RTL description internally, and the RTL description 24A of each process A, B, C, D is read.
24B, 24C, and 24D are output (step S2).

On the other hand, the process priority analysis means 12 is
The shared register name / process priority 21 is read and analyzed, and the shared register name and the process priority of writing to the shared register are stored in the internal table 23 as a process priority list (step S3).

For example, the shared register name shown in FIG.
For process priority 21, the process priority list is as follows:

Reg 1: procB → procC → procA
→ procD; Reg2: procB → procC → procA
→ procD; Reg3: procB → procC → procA
→ procD; Reg4: procB → procC → procA
→ procD;

Next, the shared register writing process analysis means 13 operates the operation descriptions 22A, 22A of the respective processes A, B, C, D divided and changed by the process conversion means 10.
22B, 22C, 22D are read, and each process A,
Which shared register B, C, D is actually writing is extracted and the shared register list for each process is stored in the internal table 23 (step S4).

For example, in the operation description 22 of the process shown in FIG. 4, the shared register list for each process A, B, C, D is as follows.

ProcA: Reg1, Reg2 procB: Reg2, Reg4 procC: Reg1, Reg2, Reg3 procD: Reg1, Reg2, Reg3, R
eg4

Subsequently, the shared register RTL output means 14
Are processes A, B, stored in the internal table 23,
With reference to the shared register list for each of C and D, the shared registers Reg1, Reg2 saved in the internal table 23
A process that does not actually write to the shared register is removed from the process priority list for each of Reg3 and Reg4, and stored in the internal table 23 as a redundancy removed process priority list (step S5).

For example, each of the above processes A, B,
Shared register list and shared register Re for each C and D
In the case of the process priority list for each of g1, Reg2, Reg3 and Reg4, the redundancy removed process priority list is as follows.

Reg 1: procC → procA → procD
; Reg2: procB → procC → procA
→ procD; Reg3: procC → procD; Reg4: procB → procD;

Next, the shared register RTL output means 14
Reads the redundancy-removed process priority list of the internal table 23, compares the write-request priority levels of the write request signals in the order of process priority according to the redundancy-removed process priority list, and exclusively controls writing to the shared register. Shared register exclusive control RTL description 2
5 is generated and output to the storage device 2 (step S6).

For the shared register Reg1, for example, the shared register RTL output means 14 outputs the shared register exclusive control RTL description 25 as shown in FIG.

Specifically, the shared register RTL output means 1
4, the shared register Reg1 is first procA, pr
Since writing is performed from ocC and procD, three write data signals Reg1_procA and Reg1 are written.
_ProcC, Reg1_procD and three write request signals Reg1_procA0, Reg1_p
It is described that it has rocC0 and Reg1_procD0.

Next, the shared register RTL output means 14
Are write request signals Reg1_procA0, Re
When g1_procC0 and Reg1_procD0 are all 0, that is, when there is no write request to the shared register Reg1, a process of doing nothing is described (see FIG. 9-).

Then, the shared register RTL output means 14
The write request signal Reg1_procC0 is equal to or more than the write request signal Reg1_procA0, and the write request signal Reg1_procC0 is the write request signal R.
A process of writing the write data signal Reg1_procC to the shared register Reg1 when the value is equal to or more than eg1_procD0 will be described (see FIG. 9-).

Next, the shared register RTL output means 14
Is the shared register Reg1 when the write request signal Reg1_procA0 is larger than the write request signal Reg1_procC0 and the write request signal Reg1_procA0 is equal to or larger than the write request signal Reg1_procD0.
The process of writing to the memory is described (see FIG. 9-).

Finally, the shared register RTL output means 14
When the write request signal Reg1_procD0 is larger than the write request signal Reg1_procC0 and the write request signal Reg1_procD0 is larger than the write request signal Reg1_procA0, the write data signal Reg1_procD is shared register Re.
The process of writing to g1 is described (see FIG. 9-).

In FIG. 9-, it is determined which one of the processes A, C, and D has the highest write request priority level. If the write request signal has the same write priority level, the if-else statement is issued. Is arranged, that is, the process priority of each process C, A, D is reflected.

The other shared registers Reg2, Reg
For 3 and Reg4, the same processing as that of the shared register Reg1 is performed.

Finally, the RTL unifying means 15 has the processes A, B, C and D generated by the high-level synthesizing means 11.
The RTL descriptions 24A, 24B, 24C, and 24D are shared with the shared register exclusive control RTL description 25 and output as an integrated process RTL description 26 (step S7).

As a result, regarding the shared register Reg1, the integrated process RTL description 26 as illustrated in FIG.
Is obtained. In addition, other shared registers Reg2 and Reg
Also for 3 and Reg4, the integrated process RTL description 26 similar to the shared register Reg1 is obtained as one.

In the shared register exclusive control description portion of the integrated process RTL description 26, the priority levels at the time of writing are first compared, the larger one is prioritized, and if the priority levels at the time of writing are the same, the process priority order is applied. , Write exclusive control.

For example, write request signals Reg1_procA0 and Reg1_procC0 of write priority level 1 from process A and process C, respectively.
Is received (from process D, write priority level 0
Of the write request signal Reg1_procD0) is true, the write from the process C having a high process priority is always prioritized.
Further, the write request signal Reg1_procA0 of the write priority level 2 from the process A and the write request signal Reg1_proc of the write priority level 1 from the process C.
When procC0 arrives, is true, and the writing from the process A is prioritized.

(2) Second Embodiment FIG. 11 is a block diagram showing the configuration of the integrated process RTL description generation method according to the second embodiment of the present invention.
The integrated process RTL description generation method according to the present embodiment is the same as the integrated process RTL description generation method according to the first embodiment shown in FIG. A recording medium 100 recording an integrated process RTL description generation program that realizes the means 12, the shared register write process analysis means 13, the shared register RTL output means 14, the RTL integration means 15, and the process conversion means 10. is there. The recording medium 100 may be a magnetic disk, a semiconductor memory, or another recording medium. Note that other configurations are exactly the same as those in the integrated process RTL description generation method according to the first embodiment, and therefore, corresponding parts will be denoted by the same reference numerals and detailed description thereof will be omitted. .

In the integrated process RTL description generation method according to the second embodiment as described above, the integrated process RTL description generation program is read from the recording medium 100 into the data processing device 1, and the high-level synthesis means 11 and the process priority analysis are performed. It operates as a unit 12, a shared register writing process analysis unit 13, a shared register RTL output unit 14, an RTL integration unit 15, and a process conversion unit 10.
The detailed operation of each of these means is exactly the same as that in the integrated process RTL description generation method according to the first embodiment, so a detailed description thereof will be omitted.

[0071]

The first effect is that it is possible to reduce the burden on the designer regarding exclusive control of the shared register.
The reason is that the exclusive control of writing to the shared register can be performed easily and flexibly by combining the two priorities of the static process priority and the dynamic write priority level.

The second effect is that the process priorities can be easily changed during design. The reason is that it is not necessary to directly change the behavioral description language by separating the process priority declarative description from the process behavioral description.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an integrated process RTL description generation system according to a first exemplary embodiment of the present invention.

FIG. 2 is a flowchart showing processing of an integrated process RTL description generation method according to the first exemplary embodiment.

FIG. 3 is a diagram showing an example of shared register names and process priorities in FIG.

4 is a diagram showing an example of a behavioral description of a process in FIG.

5 is a diagram showing an example of a behavioral description of a process A in FIG. 1 before a write description part to a shared register is changed.

FIG. 6 is a diagram showing an example of a behavior description of process A in FIG. 1 after a write description part to a shared register is changed.

FIG. 7 is a diagram showing an example of an RTL description of process A in FIG.

8 is a diagram showing an example of a shared register exclusive control RTL description in FIG. 1. FIG.

9 is a diagram showing an example of an integrated process RTL description in FIG. 1. FIG.

10 is an image diagram of a circuit for writing to a shared register Reg1 according to the integrated process RTL description in FIG.

FIG. 11 is a block diagram showing a configuration of an integrated process RTL description generation method according to a second exemplary embodiment of the present invention.

[Explanation of symbols]

1 Data processing device (computer) 2 storage devices 10 Process conversion means 11 High-level synthesis means 12 Process priority analysis means 13 Shared register writing process analysis means 14 Shared register RTL output means 15 RTL integration means 21 Shared register name / process priority 22 Process behavior description 22A Behavior description of process A 22B Behavioral description of process B 22C Behavior description of process C 22D Behavior description of process D 23 Internal table RTL description of 24 processes 24A Process A RTL description 24B Process B RTL description 24C Process C RTL description 24D Process D RTL description 25 Shared register exclusive control RTL description 26 Integrated process RTL description 100 recording media

Claims (6)

(57) [Claims] The method according to claim 1 The process of operation described in conjunction with dividing the operation description of each process, if during the operation description of the process a write description part of the shared register creates a write request signal is written in the shared register Write before
Only the request signal is issued, and the process operation record is changed.
Write if the write priority level is specified in the description
Set the priority level for writing to the request signal and issue
And a high-level synthesis means for converting the behavioral description of each process divided and modified by the process conversion means into the RTL description of each process, and the shared register name and the solution reads the process priority
And write to shared register name and shared register
Process priorities as a process priority list
And is divided and changed by the process conversion means.
The behavior description of each process is read, and each process is actually
Which shared register is being written to
To generate a shared register list for each process,
Refer to the shared register list for each process
From the process priority list for each star, it is actually a shared register
Redundant processes by removing the processes that do not write
Generated process priority list and removed redundancy
A shared register processing unit that compares shared write priority levels of write request signals in order of process priority according to the process priority list to generate a shared register exclusive control RTL description for exclusive control of writing to the shared register; Integrated process RTL description generation method, characterized in that the integrated process RTL description generation system and the shared register exclusive control RTL description are integrated to generate an integrated process RTL description. 2. The shared register processing unit reads and analyzes the shared register name and the process priority, and a shared register
Process name for register name and write to shared register
The process priority analysis means for generating the priorities as a process priority list and the process conversion means
Read the behavior description of each process that has been split and changed ,
Which shared register each process actually writes to
A shared register list for each process or by being extracted and
A shared register write process analysis unit to be generated, before
Refer to the shared register list for each process
Yes Shared from the process priority list for each register
Remove the process that does not write to the register
Generate a long-removed process priority list for redundancy
Shared register R for generating a shared register exclusive control RTL description for exclusive control of writing to the shared register by comparing the write priority levels of write request signals in the order of process priority according to the removed process priority list
The integrated process RTL description generation method according to claim 1, comprising an TL output means. The 3. A process of operation described in conjunction with dividing the operation description of each process, if there is write description part of the shared register during operation description of a process to create a write request signal, before writing to shared register Write in
Change to issue a request signal and describe the process behavior
If the priority level for writing is specified, write
Issued by setting the writing during the priority level to only request signal
And a high-level synthesis means for converting the behavioral description of each process divided and modified by the process conversion means into the RTL description of each process, and the shared register name and Read process priority and solve
And write to shared register name and shared register
Process priority analysis means for generating the process priority order of each process as a process priority list , and each process divided and changed by the process conversion means.
Process behavior description and how each process actually
Extract whether you are writing to the shared register and
Shared register writing process analysis means for generating a shared register list for each process, and a shared register for each process.
Process for each shared register with reference to a star list
Actually write to the shared register from the priority list.
Redundancy removal already seen the process priority to remove the s not process
Generates a priority list, and the redundancy-removed process priority order
Shared register exclusive control RTL for exclusive control of writing to shared registers by comparing the write priority levels of write request signals in the order of process priority according to the order list
An integrated process comprising: a shared register RTL output means for generating a description; and an RTL integration means for integrating the RTL description of each process and the shared register exclusive control RTL description to generate an integrated process RTL description. RTL description generation method. 4. A shared register name and the process priority
Read and parse, shared register name and shared register
Process priority analysis means for generating the process priority order of writing into the process priority list , and each process divided and changed by the process conversion means.
Process behavior description and how each process actually
Extract whether you are writing to the shared register and
Shared register writing process analysis means for generating a shared register list for each process, and a shared register for each process.
Process for each shared register with reference to a star list
Actually write to the shared register from the priority list.
Remove redundant processes to eliminate redundant processes. Prioritize processes.
Generates a priority list, and the redundancy-removed process priority order
Shared register exclusive control RTL for exclusive control of writing to shared registers by comparing the write priority levels of write request signals in the order of process priority according to the order list
A shared register exclusive control RTL description generation method comprising: a shared register RTL output means for generating a description. 5. A computer divides a behavioral description of a process into behavioral descriptions of each process, and
There was a description part to write to the shared register during the description .
If creating a write request signal, written in the shared register
Change to issue a write request signal before writing,
The priority level for writing is specified in the behavior description of the process.
If there is, set the write request signal to the write priority level and issue the write request to the shared register.
A process conversion means for changing the predicate portion, a high-level synthesis means for converting the behavioral description of each process divided and changed by the process conversion means into an RTL description of each process, a shared register name and a process priority order are read.
And write to the shared register name and shared register
Included process priorities in the process priority list
Generated and divided and modified by the process conversion means
The behavior description of each process
Select which shared register is actually writing
To generate a shared register list for each process,
Refer to the shared register list for each process to share
From the process priority list for each register,
Redundant by eliminating the process that does not write to the register
Generate a list of removed process priorities and
A shared register processing unit for generating a shared register exclusive control RTL description for exclusive control of writing to a shared register by comparing the write priority levels of write request signals in the order of process priority according to the removed process priority list, and A computer-readable recording medium in which a program for causing an RTL description of a process and the shared register exclusive control RTL description to be integrated to function as an RTL integrating means for generating an integrated process RTL description. 6. The computer divides a behavioral description of a process into behavioral descriptions of each process, and
There was a description part to write to the shared register during the description .
If creating a write request signal, written in the shared register
Change to issue a write request signal before writing,
The priority level for writing is specified in the behavior description of the process.
If there is, set the write request signal to the write priority level and issue the write request to the shared register.
A process conversion means for changing the predicate portion, a high-level synthesis means for converting the behavioral description of each process divided and changed by the process conversion means into an RTL description of each process, a shared register name and a process priority order are read.
And write to the shared register name and shared register
The write of the process priority to the process priority list
And a process priority analysis means for generating the process
Operation of each process divided and changed by the conversion means
Read the description and see which shared register each process actually has
Shared to each process by extracting whether writing to
A shared register write process analysis means for generating a register list and a shared register list for each process
Referring to the process priority list for each shared register,
Process that does not actually write to the shared register.
To remove the redundant process list
Generated and according to the process list for removing the redundant process.
Therefore, the shared register RTL output means for comparing the write priority levels of the write request signals in the order of the process priority to generate the shared register exclusive control RTL description for exclusive control of writing to the shared register, and R of each process.
Compilation which records a program for functioning as RTL integration means integrates TL described as a the shared register exclusive control RTL description to generate an integration process RTL description
Computer readable recording medium.