JP3705772B2 - Electronic circuit design support method in C ++ language - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method and apparatus for assisting electronic circuit design using an H / W description language in electronic circuit design.
[0002]
[Prior art]
Conventional electronic circuit design has been performed by drawing a dedicated description language or C / C ++ language for H / W design, or a circuit diagram.
[0003]
Next, the operation will be described. When the electronic circuit design is performed in the C ++ language, a description representing the operation and a class definition description unique to the C ++ language are performed. Based on these descriptions, the electronic circuit is generated by converting into physical information of the electronic circuit.
In addition, when describing the behavior of a synchronous circuit that can be converted into a physical circuit by H / W description in C ++ language, a description that considers the operation clock is given, or an abstract description is given. A physical circuit is created by an EDA tool that can be converted into physical information.
[0004]
[Problems to be solved by the invention]
In the conventional H / W description design using the C ++ language, both a description file indicating the operation and a file describing the class definition must be created. In the class definition file of the function describing the operation, the input / output port of the function and the information of the internal variable are defined. Furthermore, in the class definition file of the upper layer function that connects these functions, in addition to the input / output ports and internal variables of the upper layer function, the correspondence condition between the function and class to be called in that layer (function) and the function relation You must declare the connection signal name. If the I / O port or internal variable changes in a lower-level function, change the I / O port or internal variable declaration in the class definition file for each function, and change the function to the class definition file for the higher-level function. Since it is necessary to change the contents of the definition file of the connection signal names between them, there is a problem that the work load due to the design change is large.
[0005]
Furthermore, in the final H / W description design when designing a synchronous circuit, it is necessary to make a description in consideration of the clock, but in general, in the C ++ language, there are many cases where the design is based on an operation description that is not aware of the clock. After evaluating the algorithm of the circuit, it is rewritten to a description that is conscious of the clock. In this method, when the number of clock stages is changed due to a change in the circuit algorithm, there is a problem that it is necessary to change the description in consideration of the clock again.
[0006]
In addition, when designing a multiplier or the like, in the H / W design using the C ++ language, the design considering the H / W performance (design considering the number of pipeline stages) is generally not performed. In addition, redesign is performed with the number of pipeline stages in mind. At this time, increasing the number of pipeline stages by one means adding a flip-flop function in H / W. When there are many functions that require the addition of flip-flop functions, or when there are many pipeline stages in one function, the amount of change in the C ++ language description accompanying the change in the number of pipeline stages is large. Performance adjustments cannot be made immediately. In addition, when the number of pipeline stages is added, it is necessary to add a flip-flop in order to adjust the timing of the peripheral circuit, and there is a problem that a description change error is likely to occur.
[0007]
The present invention has been made to solve the above-mentioned problems. First, in an electronic circuit description in C ++ language, a system for reducing the workload for describing class definitions and improving the design efficiency is obtained.
[0008]
[Means for Solving the Problems]
  An electronic circuit design assistance method using a high-level language according to the present invention is as follows:In a method of assisting electronic circuit design by executing on a computer,
A module class definition generation step for identifying and extracting an internal output for each module based on a list in which the function of the circuit module is described as a function name in C ++ language;
  Based on the connection description file that describes the connection status between the modules, extract the connection point between modules as internal output of the upper hierarchy, and combine and describe modules that sort and cite functions that share common functions. Module connection information detection / upper layer class definition file generation step to obtain upper layer class definition file,
  Extract the required number of class definition files for the module obtained in the class definition generation step for the module above, and synthesize the module connection information and the class definition for the upper hierarchy obtained in the class definition file generation step for the upper hierarchy. And a class definition synthesis step for obtaining a synthesis class definition file.The above steps are executed by a computer..
[0009]
Furthermore, the connection description file describing the connection status between modules is described in C ++, and the module connection information detection / upper layer class definition file generation step is a member having a common function described in the connection description file. Added linkage to functions.
[0010]
Furthermore, a pipeline stage number detection step for detecting the number of pipeline stages from a list in which the function of the circuit module is described as a function name in C ++ language is provided.
The module class definition file now identifies pipeline output as internal output.
[0011]
Furthermore, a device type detecting step for detecting a device type from a list in which the function of the circuit module is described as a function name in C ++ language;
An LSI dependent reference table, and a pipeline stage number detecting step for determining the number of pipeline stages of the device type detected by referring to the LSI dependent reference table,
The module class definition file now identifies pipeline output as internal output.
[0012]
Furthermore, when the determined number of pipeline stages is added, paying attention to the output of the added specific module, the same number of pipeline stages is added to other modules that are input to the output module of the specific module. A peripheral circuit pipeline adding step is provided.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
Embodiment 1 of the hardware design assistance method according to the high-level language of the present invention will be described below with reference to the drawings.
1 obtains a class definition file of each module as an element from a description of a circuit algorithm in a high-level language, particularly C ++, and obtains a class definition file of an upper layer from a description of connections between modules constituting the circuit, Furthermore, it is a flowchart showing a system design flow in which these are combined to obtain a composite class definition file. It should be noted that the hardware design can be easily performed by writing in the C ++ language by using the synthetic class definition file obtained in this way and the module circuit operation description algorithm, but this part is out of the scope of the present invention, so it is described here. do not do.
[0015]
In FIG. 1, reference numeral 1 denotes a list described in the form of an algorithm in a C ++ language using functions of a module as a unit circuit, that is, functions described in relational expressions. 2 is an input / output port / internal register specifying process (step), 3 is a module class definition generating process, and a module class definition file of 4 is generated by these.
5 is a connection description file between modules in C ++ language, 6 is a circuit diagram editor, 7 is a netlist obtained thereby, 8 is a function connection information detection step for detecting connection information between modules, and any connection description file 5 or the netlist 7 detects module connection information, and in particular extracts the internal output. 9 is a class definition file generation process for an upper layer function. When a plurality of modules are connected to form an upper layer composite circuit, an internal output defined between the modules included in the upper layer (described as an internal variable) A class definition file of this higher hierarchy including is generated.
Further, 11 is a class definition synthesis step for combining a class definition file of an upper layer and a class definition file of a plurality of modules forming the upper layer, and 12 is a synthesized class definition file obtained as a result.
[0016]
FIG. 2 is a list described in the form of an algorithm in the C ++ language, and shows an example of the algorithm description file 1 in FIG. In the figure, module function (function) definitions are described as input, output, and function. In the example of this figure, the input is expressed as “type name input name” (int in-a, etc.), and the output is expressed as “type name output name” (int & out). Further, internal operations are described (if etc.) in the function description. FIG. 3 is a diagram showing an operation flow performed by the input / output port / internal register specifying process 2 and the module class definition generating process 3 and an example of the module class definition file 4 obtained as a result.
FIG. 4 is a diagram showing a composite circuit, that is, a connection example of the upper layer when a plurality of modules are connected to form an upper layer composite circuit, and an example of a connection description file 5 in which this connection is described in the C ++ language. It is. FIG. 5 is a diagram showing an operation flow performed by the inter-module connection information detection step 8 and the upper layer class definition file generation step 9, and an example of the upper layer class definition file 10 obtained as a result. FIG. 6 is a diagram showing an operation flow performed by the class definition synthesis step 11 and an example of the synthesis class definition file 12 obtained as a result.
[0017]
The operation in each step of FIG. 1 will be described.
In the input / output port / internal register specifying process 2, a variable as an input is searched from the algorithm description file 1 as an input, and a function name, an input port, an output port, and an internal register are specified. That is, an argument (variable) name declared as “type name input port name” in the function factor declaration is searched for as an input port. Similarly, the argument name declared as “type name output port name” in the function argument declaration is searched for as an output port. This is indicated by S21 in FIG. The output used in the function is searched, and the functions that are expressed in particular (= display) and those other than those identified as output ports are internal registers such as flip-flops that are intermediate outputs. Is done. This is the operation shown in S22.
In the module class definition generation step 3, the internal output is labeled as private from the searched input port name, output port name, and internal output, and the module member function declaration is labeled public. In S23, the relationship with the module is described as void var, and the module class definition file 4 is generated. In the figure, class func represents a module class definition file.
[0018]
On the other hand, one piece of connection information between the modules is obtained from the connection description file 5 shown as an example in FIG. 4B in which module connections are described in C ++ language. This example describes the connection relationship of the upper layer composite circuit composed of five hardware modules in FIG.
FIG. 4B shows that there are two upper-level input variables, a and b, from which an upper-layer output can be finally obtained. More specifically, as a connection relationship between lower modules, a function belonging to class F_A (for example, division) has func_A, and a function belonging to class F_B (for example, multiplication) has func_B0 and func_B1. Each input is, for example, a and c in func_A, and the output is d.
From this input file, the connection information detection step 8 performs an operation based on the flow of FIG. That is, in S31, the output port is extracted by the argument name of the function in the connection description file 5. Next, in S32, those other than the output port are extracted and set as internal variables (output). In the class definition file generation step 9 of the upper hierarchy, these are labeled as private, and the same member function (for example, class = F_B in the figure) is used as a comment in the connection description file described in the C ++ language by the sort operation in S33. Are combined and described as func_B0, func_B1, and the like. In S34, a void bar declaration that associates the algorithm description with the class definition file is made, and the upper layer class definition file 10 of FIG. 5B is obtained.
[0019]
Another method for obtaining inter-module connection information is to obtain information from the netlist 7 generated by the circuit diagram editor 6. Also in this case, since the relationship between the class and the function is defined by the attributes defined in the net list, a list corresponding to FIG. 4B is finally obtained, and the operation corresponding to FIG. As a result, the upper layer class definition file 10 is obtained.
In the class definition synthesis step 11, a plurality of files are combined as shown in FIG. That is, in S41 of FIG. 6B, modules described from the algorithm description file expressing the upper hierarchy are extracted, and the class definition files of these modules are stored in the memory. Further, in S42, the class definition file 10 of the upper hierarchy is extracted and combined with the class definition files of a plurality of modules previously stored in the memory to generate the combined class definition file 12 of FIG. .
[0020]
Even if the class definition file is completed in this way, for example, a new module may be added between modules or a new signal may be added to change the design. In such a case, as a matter of course, it is necessary to recreate the class definition file based on the design change.
To apply a design change to this embodiment, the designer changes both the class definition file and the connection description file. Even in such a case, according to the method of the present embodiment, it will be explained that if the original connection description is changed, the class definition file is changed based on the change.
FIG. 7A is a diagram for explaining the connection state of the upper hierarchy in FIG. 4A. In the case where a new module 13 is added and the design is changed to connect the output to the module B0 and the module B1. It is the original connection change figure. FIG. 7B is a diagram showing the definition files of the modules B0 and B1 before the design change, and FIG. 7C is a diagram showing the class definition file after the change.
[0021]
As an operation, first, the module definition file 4 is incremented by one, so c is added. In the connection diagram of FIG. 7A, the signal name of the added input is z. However, in the lath definition file 4 in C ++, the input signal is determined sequentially, so it is not necessary to name z. . FIG. 8A shows the connection description file 5 before the change, which becomes the description of FIG. 8B by adding the module of FIG. 7A. That is, a new module z is added, and the intermediate output z is connected to each input of the modules func_B0 and func_B1.
Although the detailed description is omitted, the connection information detection step 8, the upper layer class definition file generation step 9, and the class definition synthesis step 11 operate as described above by these inputs, and the design change of FIG. A synthetic class definition file 12 corresponding to is generated.
Even when the connection information is changed by the circuit diagram editor 6, the user can obtain a new netlist 7 based on the connection information, and can easily extract a new module and a change in connection relation as compared with the netlist before the design change. That is, if there is an addition, a description is added, and if there is a deletion, the corresponding module is deleted or the connection description is reduced.
[0022]
Embodiment 2. FIG.
FIG. 9 is a flowchart showing the flow of the H / W design method using the C ++ language in the present embodiment. This is an additional operation flow before the creation of the module class definition file 1 in the first embodiment. In the present embodiment, the number of pipeline stages to be inserted is defined for the module function description described in C ++ with an abstraction level that is not aware of the clock, and the C ++ description in which the pipeline is adjusted based on the information is defined. A generation method will be described.
[0023]
For a multi-bit multiplier or the like, the processing result may not be in time due to timing constraints unless some stages of pipeline processing are inserted depending on the contents of the logic circuit or the device performance of the hardware. Therefore, in the H / W description in the C ++ language, the number of pipeline stages to be inserted into a multiplier circuit or the like existing inside the module function is defined in the program file 13 describing the circuit operation of the module function. FIG. 10 shows a description example. In this example, “#pragma cycle (number of inserted pipeline stages)” is declared. That is, in the example of FIG. 10, the insertion pipeline has two stages.
[0024]
In the detection step 15a, the number of pipeline stages such as an arbitrary multiplier circuit is specified by searching the number of pipeline stages declared in the program file 13 by the user. Then, flip-flop module functions are added to the output of the function of the multiplier circuit or the like for the number of pipeline stages defined. As a method of adding, first, a function output port such as a multiplier circuit is connected, and the output port name of the flip-flop function is changed to the output port name of the multiplier circuit before the change. As a result, a one-stage flip-flop circuit is inserted.
When adding a flip-flop function with two or three stages, change the output port name of the flip-flop function at the final stage and connect the input port of the flip module function to be added. Then, the output port of the added flip-flop function is changed to the output port of the multiplier circuit before the description change.
[0025]
Further, a flip-flop module function is added correspondingly to a circuit existing around a multiplier circuit to which a flip-flop is added, thereby avoiding a timing error of the entire circuit. As an example, the relationship between the multiplier module and peripheral circuits is shown in FIG. When a flip-flop module is added to the multiplier module 20a, the flip-flop module is added to the output of the peripheral circuit A 20b in order to match the timing of the entire circuit. This eliminates the timing difference between the output signal of the multiplier module 20a input to the circuit B20c and the output signal of the circuit A20b module. The search method of the circuit A first searches for the function B connected to the output port of the multiplier module. Next, the port name input from other than the multiplier module at the input port of the function B is searched. Then, by detecting a function having the same connection signal as the port name, the peripheral circuit A to which the flip-flop module is added is determined. In the method of adding a flip-flop module to the peripheral circuit A, the output port name of the peripheral circuit A is changed and connected to the input port of the flip-flop function to be added. Then, the output signal of the flip-flop function is changed to the final output port name of the peripheral circuit A.
Thus, the module circuit operation algorithm description program 1b in the C ++ language to which the flip-flop function is added is generated. Since the module class definition file creation process using the circuit operation algorithm description file 1b follows the flow of FIG. 1, description thereof is omitted.
[0026]
If the LSI device type to be designed is determined and the number of pipeline stages is set according to the device type, the user defines the device type, function name, and pipeline stage number in the LSI dependent reference table 16. Then, the user declares the LSI device name in the program file 13 by a “pragma” declaration or the like. FIG. 12 shows an example of the program file 13 and FIG. 13 shows a description example of the LSI-dependent reference table 16. This is in the LSI dependence reference table 16 of FIG. 9, and the number of stages is determined empirically corresponding to the device and the number of multiplication bits. In the description example of the program file 13, the declaration of the device name is referred to as “#pragma dev_type type device name”. The LSI dependent reference table 16 defines “(device name) − (function name) − (number of pipeline stages)”. First, the device type of the LSI is extracted from the program file 13 by the device detector 14. Next, the number of pipeline stages to be inserted into the target function is determined using the function name of the multiplier circuit or the like called in the program file 13 and the extracted device name as keys.
[0027]
Embodiment 3 FIG.
FIG. 14 is a flowchart showing the flow of the H / W design method using the memory in the C ++ language in the present embodiment. Similarly to the second embodiment, this is an additional operation flow in the first stage of creating the module class definition file 1 in the first embodiment. In the present embodiment, the memory read and write access processing generates the C ++ language description 1c in consideration of the clock in the same manner as the multiplier and the like.
[0028]
The user sets the access timing for reading and writing memory data in the program 21 in which the operation description is unaware of the memory access timing, and uses the “pragma” declaration in the description. Define. A description example is shown in FIG. This access timing information is extracted, and a flip-flop function is added before and after the memory module function to generate a C ++ language description 1c that takes into account the memory read and write access timings. Since subsequent operations follow the operation flow of FIG. 1, detailed description is omitted.
[0029]
In the description of FIG. 15, the number of delay stages is 1. In order to delay the access timing for the memory read by one cycle, it can be realized by adding a one-stage flip-flop to the read data and the read address of the memory. As a method for adding the flip-flop function, the number of read delay stages set by the “pragma” declaration is extracted from the program file 21. In the description example of FIG. 15, “#pragma (function name) -R- (number of pipeline stages)”. Then, the signal name of the read address input to the memory is changed and connected to the input port of the flip-flop function. The output port of the flip-flop function module is changed to the signal name of the read address before the change. To delay the multi-stage access timing, a plurality of flip-flop circuits are added simultaneously.
[0030]
The access timing for memory write can be delayed by one cycle by adding a one-stage flip-flop to the memory write data and write address. As a method for adding a flip-flop function, the number of read delay stages set by a “pragma” declaration or the like is extracted from the program file 21. In this description example, “#pragma (function name) −W− (number of pipeline stages)” is set. Then, the data output from the memory and the signal name of the write address are changed and connected to the input port of the flip-flop function. In order to delay the multi-stage access timing in which the output port of the flip-flop function module is changed to the signal name of the write data and write address before the change, a plurality of flip-flop circuits are similarly added.
[0031]
In addition, the relationship between the memory access timing and the memory type can be defined by the user in the memory timing reference table 30. The memory timing reference table 30 defines memory access timing, the number of read delay stages, and the number of write delay stages. An example is shown in FIG. In this example, “(memory type) −R / W− (number of stages)” is defined. If mem_A and mem_B are memory types and R-1 is set, one stage of flip-flop is added to the read timing. If it is R-2, a two-stage flip-flop is added. If it is W-1, one stage flip-flop is added to the write timing, and if it is W-2, two stages flip-flop is added. It is measured whether the function used in the program file 21 matches the “memory type” in the memory timing reference table. In the case of matching, the number of read and write stages for the target memory type is extracted from the memory timing. Then, a C ++ language that takes into account the intended access timing is generated.
[0032]
【The invention's effect】
As described above, according to the present invention, the class definition file necessary for hardware circuit design using the C ++ language is created from the circuit operation description algorithm, so that the designer's circuit design load is reduced.
[Brief description of the drawings]
FIG. 1 is an operation flowchart of a hardware design assistance method according to Embodiment 1 of the present invention.
FIG. 2 is a diagram showing an example of an algorithm description list in C ++ language according to the first embodiment.
FIG. 3 is a diagram illustrating an operation of an input / output port / internal register specifying step 2 and a module class definition generating step 3 and an example of a module class definition file obtained as a result thereof;
FIG. 4 is a diagram illustrating an example of connection between modules and a connection description file between modules described in a C ++ language.
FIG. 5 is a diagram illustrating an operation of an inter-module connection information detection step 8 and an upper layer class definition file generation step 9 and an example of an upper layer class definition file obtained as a result.
FIG. 6 is a diagram illustrating an operation of an upper layer class definition synthesis step 11 and an example of a resultant synthesis class definition file.
7 is a diagram showing an example of adding a module in the first embodiment and a change of a class definition file of the module based on the example. FIG.
FIG. 8 is a diagram showing a change in an inter-module connection description file and a change in a synthesis class definition file by adding a module in the first embodiment.
FIG. 9 is an operation flowchart of pre-processing of a module circuit operation description file according to the second embodiment of the present invention.
FIG. 10 is a diagram illustrating an example of a circuit algorithm description file that is not conscious of pipelines in the second embodiment.
FIG. 11 is a diagram for explaining the operation of a peripheral circuit pipeline addition step 18 in the second embodiment.
12 is a diagram illustrating an example of a circuit algorithm description file that is not conscious of other pipelines in Embodiment 2. FIG.
FIG. 13 is a diagram showing an example of an LSI dependence reference table 16 in the second embodiment.
FIG. 14 is an operation flowchart of preprocessing of a module circuit operation description file according to the third embodiment of the present invention.
FIG. 15 is a diagram illustrating an example of a circuit algorithm description file that is not conscious of pipelines in the third embodiment.
FIG. 16 illustrates an example of a memory timing reference table 30 according to the third embodiment.
[Explanation of symbols]
1, 1a, 1b Description file of circuit operation algorithm in module in C ++ language, 2 Input / output port / internal register specifying processing step (process), 3 Module class definition generating step (process), 8 Inter-module connection information detecting step (Process), 9 Upper layer class definition file generation step (Process), 11 Upper layer class definition synthesis step (Process), 14 Device type detection step (Process), 15a, 15b Pipeline stage number detection step (Process), 16 LSI dependent reference table, 17 pipeline stage number addition step (process) to module, 18 pipeline stage number addition step (process) to peripheral circuit, 30 memory timing reference table.

Claims (5)

In a method of assisting electronic circuit design by executing on a computer,
A module class definition generation step for identifying and extracting an internal output for each module based on a list in which the function of the circuit module is described as a function name in C ++ language;
Based on the connection description file that describes the connection status between the modules, extract the connection point between modules as internal output of the upper hierarchy, and combine and describe modules that sort and cite functions that share common functions. Module connection information detection / upper layer class definition file generation step to obtain upper layer class definition file,
Extract the required number of class definition files for the module obtained in the class definition generation step for the module above, and synthesize the module connection information and the class definition for the upper hierarchy obtained in the class definition file generation step for the upper hierarchy. And a class definition synthesis step for obtaining a synthesis class definition file, and executing the above steps by a computer.   The connection description file describing the connection status between modules is described in C ++ language, and the module connection information detection / upper layer class definition file generation step is performed with member functions having common functions described in the connection description file. 2. The electronic circuit design assisting method according to claim 1, wherein the connection description is made for the C ++ language. If the list describing the function of the circuit module as a function name by C ++ language pipeline connections are described detects the number of stages of the pipeline from the list describing the function name function of the circuit modules by the C ++ language A pipeline stage number detection step is provided.
2. The electronic circuit design assistance method according to claim 1, wherein the module class definition file specifies the output of the pipeline as an internal output. When pipeline connection is described in a list in which the function of the circuit module is described as a function name in the C ++ language, device type detection for detecting the device type from the list in which the function of the circuit module is described as a function name in the C ++ language Steps,
Provided LSI dependent reference table, the pipeline stage number detection step by referring to the LSI dependent reference table determines the number of stages of the pipeline device type described above detected, includes a city,
2. The electronic circuit design assistance method according to claim 1, wherein the module class definition file specifies the output of the pipeline as an internal output.   When the determined number of pipeline stages is added, paying attention to the output of the added specific module, the same number of pipeline stages is also added to other modules input to the output destination module of the specific module. 5. The electronic circuit design assisting method according to claim 3 or 4, further comprising a peripheral circuit pipeline adding step.

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