JP5211776B2 - Behavioral synthesis apparatus, behavioral synthesis method, and program - Google Patents

Description

  The present invention relates to a behavioral synthesis apparatus, a behavioral synthesis method, and a program for realizing these on a computer suitable for suppressing the number of registers when generating a register transfer level description from the behavioral level description of a semiconductor integrated circuit. About.

  Due to advances in computer technology, it has become common to design, analyze, and evaluate logic circuits using a CAD (Computer-Aided Design) system. This CAD system includes, for example, a behavioral synthesis tool and a logic synthesis tool.

  When performing behavioral synthesis using a behavioral synthesis tool, it is necessary to prepare a description written in a behavioral level description language that includes information necessary for H / W conversion such as the input port and bit width of variables. is there. The behavioral synthesis tool outputs a description in an RTL (Register Transfer Level) description language by performing behavioral synthesis based on the description written in the behavioral level description language. A behavioral synthesis technique using a behavioral synthesis tool is disclosed in Patent Document 1, for example.

  The behavioral synthesis procedure disclosed in Patent Document 1 will be briefly described below.

  First, the behavioral synthesis tool parses a description written in a behavioral level description language. Subsequently, the behavioral synthesis tool realizes the variable being described by a register (or memory). Then, the behavioral synthesis tool generates a control data flow graph (hereinafter referred to as CDFG).

Next, the behavioral synthesis tool performs resource binding and scheduling based on the CDFG. Then, the behavioral synthesis tool synthesizes a circuit by mapping and sharing arithmetic units, registers, multiplexers, and the like based on the circuit frequency and arithmetic unit constraints, which are synthesis constraints. Finally, the behavioral synthesis tool outputs the synthesized circuit configuration as a description in an RTL description language that can be directly input to the logic synthesis tool, and ends the behavioral synthesis.
JP 2007-272671 A

  Usually, the behavior description is composed of a data input stage description, a process body description, and a data output stage description. In the circuit synthesized by the behavioral synthesis procedure disclosed in Patent Document 1, it is necessary to prepare as many registers as the number of data input at the input stage and the number of data output at the data output stage. For this reason, when the number of variables increases, it is necessary to prepare as many registers as there are.

  The present invention has been made in view of the above problem, and a behavioral synthesis apparatus and behavioral synthesis method suitable for suppressing the number of registers when generating a register transfer level description from a behavioral level description of a semiconductor integrated circuit. Another object of the present invention is to provide a program for realizing these on a computer.

In order to achieve the above object, a behavioral synthesis device according to a first aspect of the present invention includes a reception unit, a division unit, a schedule unit, and a generation unit, and is configured as follows.
First, the accepting unit accepts an operation level description that describes the operation of the semiconductor integrated circuit as a single process .
Next, the dividing unit converts the received behavior level description into a data input stage description, a process body stage description as each of a plurality of processes based on a predetermined pragma included in the behavior level description, Divide into data output stage descriptions.
Furthermore, the schedule unit schedules input / output and calculation timings for each of the input stage description, the main body stage description, and the output stage description.
Then, the generation unit generates a register transfer level description that describes the configuration, arrangement, and wiring of the semiconductor integrated circuit based on the input stage description, the main body stage description, the output stage description, and the timing.
In addition, the generation unit
(A) When the output timing of the input stage description and the input timing of the main body stage description match, the output and the input are directly connected. When they do not match, a register circuit is connected between the output and the input. And place
(B) When the output timing of the main body stage description and the input timing of the output stage description match, the output and the input are directly connected. When they do not match, a register circuit is connected between the output and the input. Place.

In order to achieve the above object, a behavioral synthesis method according to another aspect is a behavioral synthesis method executed by a behavioral synthesis device including a reception unit, a division unit, a schedule unit, and a generation unit, and includes a reception step, a division step, A schedule step and a generation step are provided and configured as follows.
That is, in the accepting step, the accepting unit accepts an operation level description that describes the operation of the semiconductor integrated circuit as a single process .
In the dividing step, the dividing unit converts the received behavior level description into a data input stage description and a processing body as each of a plurality of processes based on a predetermined pragma included in the behavior level description. Divide into stage description and data output stage description.
Further, in the scheduling step, the scheduling unit schedules input / output and operation timing for each of the input stage description, the main body stage description, and the output stage description.
In the generation step, the generation unit generates a register transfer level description that describes the configuration, arrangement, and wiring of the semiconductor integrated circuit based on the input stage description, the main body stage description, the output stage description, and the timing. Generate.
Furthermore, in the generation step, the generation unit
(A) When the output timing of the input stage description and the input timing of the main body stage description match, the output and the input are directly connected. When they do not match, a register circuit is connected between the output and the input. And place
(B) When the output timing of the main body stage description and the input timing of the output stage description match, the output and the input are directly connected. When they do not match, a register circuit is connected between the output and the input. Place.

In order to achieve the above object, a program according to another aspect causes a computer to function as a reception unit, a division unit, a schedule unit, and a generation unit as follows.
First, the accepting unit accepts an operation level description that describes the operation of the semiconductor integrated circuit as a single process .
Next, the dividing unit converts the received behavior level description into a data input stage description, a process body stage description as each of a plurality of processes based on a predetermined pragma included in the behavior level description, Divide into data output stage descriptions.
Furthermore, the schedule unit schedules input / output and calculation timings for each of the input stage description, the main body stage description, and the output stage description.
Then, the generation unit generates a register transfer level description that describes the configuration, arrangement, and wiring of the semiconductor integrated circuit based on the input stage description, the main body stage description, the output stage description, and the timing.
In addition, the generation unit
(A) When the output timing of the input stage description and the input timing of the main body stage description match, the output and the input are directly connected. When they do not match, a register circuit is connected between the output and the input. And place
(B) When the output timing of the main body stage description and the input timing of the output stage description match, the output and the input are directly connected. When they do not match, a register circuit is connected between the output and the input. Place.

  According to the present invention, when generating a register transfer level description from a behavior level description of a semiconductor integrated circuit, a behavioral synthesis apparatus, a behavioral synthesis method, and the like suitable for suppressing the number of register circuits are realized on a computer. A program can be provided.

  The behavioral synthesis device according to the present embodiment will be described below with reference to the drawings.

  First, the configuration of the behavioral synthesis device according to the present embodiment will be described with reference to FIG.

  As shown in FIG. 1, the behavioral synthesis device 100 physically includes a CPU (Central Processing Unit) 11, a ROM (Read Only Memory) 12, a RAM (Random Access Memory) 13, a hard disk device 14, An input device 15 and a display device 16 are provided. Each component included in the behavioral synthesis device 100 is connected via a bus.

  The CPU 11 controls the overall operation of the behavioral synthesis device 100 in accordance with a program stored in the hard disk device 14. The CPU 15 is connected to each component via a bus and exchanges control signals and data.

  The ROM 12 stores an IPL (Initial Program Loader) that is executed immediately after the power is turned on. After the IPL is executed, the CPU 11 reads the program stored in the hard disk device 14 to the RAM 13 and executes it.

  The RAM 13 temporarily stores data and programs. The RAM 13 temporarily stores a program read from the hard disk device 14, data necessary for behavioral synthesis processing, and the like.

  The hard disk device 14 stores a program executed by the CPU 11.

  The input device 15 receives input of parameters and the like necessary for behavioral synthesis from the user under the control of the CPU 11 and accepts requests such as a behavioral synthesis start request from the user. The input device 15 is composed of a keyboard and a mouse, for example.

  Under the control of the CPU 11, the display device 16 displays a screen for receiving a request such as input of a parameter or a request from a user, a behavioral synthesis start request, a screen for displaying a behavior level description, and a register transfer level description. Display a screen for the purpose. The display device 16 is composed of, for example, a liquid crystal display device.

  Next, a basic configuration of the behavioral synthesis device 100 according to the present embodiment will be described.

  FIG. 2 is a block diagram showing a basic configuration of the behavioral synthesis device 100 according to the present embodiment. As shown in FIG. 2, the behavioral synthesis device 100 functionally includes a receiving unit 20, a dividing unit 30, a scheduling unit 40, and a generating unit 50.

  The accepting unit 20 accepts a behavior level description. The receiving unit 20 is realized by the CPU 11 cooperating with the ROM 12, the RAM 13, and the input device 15.

  The dividing unit 30 divides the behavior level description into descriptions for each processing stage. Specifically, the dividing unit 30 divides the behavior level description stored in the RAM 13 into a data input stage description, a process main body stage description, and a data output stage description. The dividing unit 30 is realized by the CPU 11 cooperating with the ROM 12 and the RAM 13.

  The schedule unit 40 schedules input / output and calculation timings for each of the input stage description, the body stage description, and the output stage description. The schedule unit 40 is realized by the CPU 11 cooperating with the ROM 12 and the RAM 13.

  The generation unit 50 generates an RTL (Register Transfer Level) description that describes the configuration, arrangement, and wiring of the semiconductor integrated circuit based on the input stage description, the body stage description, the output stage description, and the timing. To do.

  Specifically, when the output timing of the input stage description matches the input timing of the main body stage description, the generation unit 50 directly connects the output and the input, and when they do not match, the generation unit 50 registers between the output and the input. Arrange the circuit. The generation unit 50 directly connects the output and the input when the output timing of the main body stage description and the input timing of the output stage description match, and arranges the register circuit between the output and the input when they do not match. To do.

  Next, the behavioral synthesis process executed by the behavioral synthesis device 100 according to the present embodiment will be described with reference to FIGS. 3 and 4.

  As shown in FIG. 3, the behavioral synthesis device 100 further includes a CDFG (Control Data Flow Graph) generation unit 35 in addition to the basic configuration shown in FIG. Further, the generation unit 50 includes a processing stage-specific RTL description generation unit 51, a communication path generation unit 52, and an all RTL description generation unit 53.

  As illustrated in FIG. 3, the behavioral synthesis device 100 behaviorally synthesizes the behavioral level description stored in the behavioral level description storage unit 111 provided in the storage device 110, and the RTL description provided in the storage device 110 includes the obtained RTL description. The data is stored in the storage unit 112. In this embodiment, the configuration is described in which the storage device 110 is provided outside the behavioral synthesis device 100, but the behavioral synthesis device 100 may include the storage device 110. In the configuration in which the behavioral synthesis device 100 includes the storage device 110, for example, the hard disk device 14 configures the storage device 110.

  Here, the behavior level description is a description in which the circuit operation to be designed is expressed using C language, C ++ language, JAVA (registered trademark) language, or the like. In the behavior level description, the timing from the reference point is specified for each input / output using a pragma. The RTL description is a description that embodies the generated circuit to be designed to the operation for each clock.

  FIG. 4 is a flowchart showing the behavioral synthesis process executed by the behavioral synthesis device 100 according to the present embodiment.

  For example, when the behavioral synthesis apparatus 100 receives a request for behavioral synthesis of a predetermined behavior level description from the user via the input device 15, the behavioral synthesis process starts.

  First, the CPU 11 initializes data used in the behavioral synthesis process (step S11). The CPU 11 initializes data stored in the RAM 13.

  When the CPU 11 completes initialization, the receiving unit 20 receives a behavior level description (step S12). First, the accepting unit 20 accepts specification of a behavioral level description to be synthesized and parameter specification from a user. Then, the receiving unit 20 reads out the behavior level description designated by the user from the behavior level description storage unit 111 and stores the behavior level description in the RAM 13 and also stores the parameter designated by the user in the RAM 13.

  Next, the dividing unit 30 divides the behavior level description into descriptions for each processing stage (step S13). Specifically, the dividing unit 30 divides the behavior level description stored in the RAM 13 into a data input stage description, a process main body stage description, and a data output stage description. The dividing unit 30 divides the behavior level description with reference to, for example, an input / output port definition part or pragma in the behavior level description.

  Next, the CDFG generation unit 35 generates a CDFG for each processing stage (step S14). Specifically, the CDFG generation unit 35 generates a CDFG for input processing based on the input stage description, generates a CDFG for main body processing based on the main body stage description, and generates a CDFG for output processing based on the output stage description. Generate. The CDFG generation unit 35 is realized by the CPU 11 cooperating with the ROM 12 and the RAM 13.

  Next, the schedule part 40 schedules each process step (step S15). Specifically, the scheduling unit 40 obtains the number of arithmetic units and the number of steps necessary for the input processing based on the CDFG of the input processing, and the number of arithmetic units and the number of steps necessary for the main body processing based on the CDFG of the main body processing. And the number of computing units and the number of steps necessary for the output process are obtained based on the CDFG of the output process. Note that the schedule unit 40 schedules based on the designation of the timing described as a pragma in the behavior level description, for example.

  Next, the RTL description generating unit 51 for each processing stage generates an RTL description for each processing stage (step S16). Specifically, the RTL description generating unit 51 for each processing stage generates an RTL description corresponding to the input circuit in the input processing stage based on the processing schedule result in the input processing stage, and generates the schedule result in the main body processing stage. Based on this, an RTL description corresponding to the main circuit in the main processing stage is generated, and an RTL description corresponding to the output circuit in the output processing stage is generated based on the schedule result of the processing in the output processing stage.

  Next, the communication path generation unit 52 generates a communication path between the circuits based on the RTL description and schedule result of each processing stage (step S17). The communication path generation process executed by the communication path generation unit 52 will be described in detail with reference to the flowchart shown in FIG.

  First, the communication path generation unit 52 selects data from data transferred between circuits (step S21). Here, the data transferred between the circuits is, for example, data supplied from the input circuit to the main circuit or data supplied from the main circuit to the output circuit.

  Next, the communication path generation unit 52 determines whether or not the timing at which the transfer source circuit outputs the selected data is different from the timing at which the transfer destination circuit inputs the selected data (step S22). For example, when the selected data is data supplied from the input circuit to the main circuit, the communication path generation unit 52 determines whether the timing at which the input circuit outputs this data is different from the timing at which the main circuit inputs this data. Determine whether or not.

  Here, each circuit does not need to input data until data is used. For this reason, the schedule part 40 shall schedule the timing which uses data as a timing which inputs data. In the following description, it is assumed that the data input timing is the same as the data use timing.

  When determining that the timing is different (step S22: YES), the communication path generation unit 52 prepares a register corresponding to the selected data (step S23). On the other hand, when it is determined that the timing is not different (step S22: NO), the communication path generation unit 52 does not prepare a register corresponding to the selected data.

  When the communication path generation unit 52 determines that the timing is not different (step S22: NO) or completes the preparation of the register corresponding to the selected data (step S23), the data transferred between the circuits is stored. It is determined whether or not all have been selected (step S24).

  If the communication path generation unit 52 determines that not all data has been selected (step S24: NO), it selects data that has not yet been selected from among the data transferred between the circuits, and repeats the same processing. (Steps S21 to S23). On the other hand, if it is determined that all the data has been selected (step S24: YES), the communication path generation unit 52 selects the data from the data for which the register is prepared (step S25).

  After selecting data from the data for which the register is prepared (step S25), the communication path generation unit 52 determines whether there is data whose transfer timing does not overlap with the transfer timing of the selected data (step S26). Note that the communication path generation unit 52 targets only data output from the circuit that outputs the selected data among the data for which the corresponding register is prepared in step S23. That is, the communication path generation unit 52 does not target data for which no register is prepared or data output from a circuit other than the circuit that outputs the selected data.

  If it is determined that there is data whose transfer timing does not overlap with the transfer timing of the selected data (step S26: YES), the communication path generation unit 52 is prepared corresponding to the data whose transfer timing does not overlap with the selected data. The register and the register prepared corresponding to the selected data are shared (step S27).

  Specifically, for example, the communication path generation unit 52 deletes a register prepared corresponding to the selected data, and shares the register prepared corresponding to the data whose transfer timing does not overlap with the selected data. .

  If the communication path generation unit 52 determines that there is no data whose transfer timing does not overlap with the transfer timing of the selected data (step S26: NO) or completes register sharing (step S27), a register is prepared. It is determined whether or not all the selected data has been selected (step S28).

  If the communication path generation unit 52 determines that not all the data has been selected (step S28: NO), the communication path generation unit 52 selects data that has not yet been selected from among the data for which the registers are prepared, and repeats the same processing ( Step S25 to Step S27). On the other hand, when it is determined that all the data has been selected (step S28: YES), the communication path generation unit 52 generates communication path information (step S29).

  Specifically, the communication path generating unit 52 generates information associating data transferred between circuits and registers as communication path information (step S29).

  When the communication path generation unit 52 ends the generation of the communication path information (step S29), the communication path generation process ends.

  When the communication path generation unit 52 completes the communication path generation process (step S17), the RTL description generation unit 53 includes the RTL description of each processing stage generated by the RTL description generation part 51 for each processing stage, and the communication path generation unit 52. The RTL description corresponding to all the descriptions of the behavior level description received by the receiving unit 20 is generated based on the communication path information generated by (Step S18).

  Finally, the all RTL description generation unit 53 stores all the RTL descriptions in the RTL storage unit 112, and ends the behavioral synthesis process (step S19).

  Next, how the behavioral synthesis device 100 according to the present embodiment generates the RTL description based on the behavior level description will be described with a specific example.

  FIG. 6 shows an example of behavior level description expressed in the SystemC language. The behavior level description shown in FIG. 6 is an example of a description expressing the behavior of the module gcd3 that calculates and outputs the greatest common divisor of three supplied input data. FIG. 6 shows only the portions necessary for explaining the present invention.

  As shown in the second to fifth lines, the module gcd3 has two input terminals start and in_dat and two output terminals out_dat and done. Here, the input terminal start is a terminal to which a signal (start signal) for instructing start of data input is supplied, and the input terminal in_dat is a terminal to which input data is supplied. The output terminal out_dat is a terminal that outputs data, and the output terminal done is a terminal that outputs a signal (done signal) indicating that the output data is valid.

  When the module gcd3 determines that the start signal is supplied to the input terminal start, the module gcd3 takes in three pieces of data from the input terminal in_dat. The module gcd3 obtains the greatest common divisor of the fetched three data, outputs the obtained result from the output terminal out_dat, and then outputs a done signal from the output terminal done.

  The operation description of the module gcd3 has two functions entry () and gcd2 (). The function entry () is a function that expresses an operation of taking input data from the outside, calling the function gcd2 () to calculate the greatest common divisor, and outputting the calculation result to the outside. The function gcd2 () is a function that expresses the operation of calculating the greatest common divisor of two given numbers using the Euclidean algorithm.

  The function entry () describes three processes: an input process, a main body process, and an output process.

  In the input processing, first, the process waits until the value read from the input terminal start becomes “1” (line 13). When the value read from the input terminal start becomes “1”, the input data is fetched from the input terminal in_dat, and the value is stored in the local variable dat []. The fetching of input data from the input terminal in_dat is executed three times in succession, and the first, second and third input data are stored in local variables dat [0], dat [1] and dat [2], respectively. (Line 14 to 17). In the following description, in order to facilitate understanding, local variables dat [0], dat [1], and dat [2] are converted into data dat [0], dat [1], dat [ 2].

  In the twelfth line, a pragma burst_interface is designated that indicates that this input process is a process to be executed in a burst manner without handshaking for each data. Note that the pragma burst_interface is not defined in the specification of SystemC.

The following (1) and (2) are specified by the pragma burst_interface.
(1) Data fetch from the input terminal start is executed every clock cycle.
(2) When the data supplied to the input terminal “start” becomes “1”, the data is fetched from the input terminal in_dat in the next clock cycle, and the next clock cycle (2 Data is taken in from the input terminal in_dat continuously in the clock cycle) and the next clock cycle (third clock cycle).

  In the main process, the function gcd2 () is called to calculate the greatest common divisor of the three numbers (from the 20th line to the 21st line). First, the function gcd2 () is called with the data dat [0] input first time and the data dat [1] input second time as arguments, and the greatest common divisor of these data is calculated (line 20). ). Next, by calling the function gcd2 () with the result and the data dat [2] inputted for the third time as an argument, the greatest common divisor of the three data is calculated and stored in the local variable ret (line 21). Eye).

  In the output process, the greatest common divisor stored in the local variable ret is output to the output terminal out_dat, and the signal level of the done signal is set to “1” and output from the output terminal done (from the 22nd line to the 24th line). Then, in the next clock cycle, the signal level of the done signal is returned to “0” and output from the output terminal done (from the 25th line to the 26th line).

  The function gcd2 () is given two numbers as arguments x and y, calculates the greatest common divisor of the two numbers using the Euclidean algorithm, and returns it as a return value. Specifically, the following procedure is executed. First, x and y are compared, and if the values are different, the larger of x and y is updated with the difference (from the 32nd line to the 35th line). When the values of x and y become the same, the repetition is terminated, and the value of x is returned as the return value as the greatest common divisor.

  An example of the schedule result of the behavioral description shown in FIG. 6 is shown in FIGS. 7A, 7B, 8A, and 8B. FIG. 7A is a diagram illustrating an example of a schedule result of input processing. FIG. 7B and FIG. 8A are diagrams showing an example of a schedule result of the main body process. FIG. 8B is a diagram illustrating an example of a schedule result of output processing.

  As shown in FIG. 7A, input processing is scheduled from state 1 to state 4 in accordance with the designation of the pragma burst_interface. In state 1, a value is read from the input terminal start, and state 1 is repeated while the value is “0”. When the value of the input terminal start becomes “1”, state 2 is executed in the next clock cycle. In states 2, 3, and 4, values are read from the input terminal in_dat, and values are stored in local variables dat [0], dat [1], and dat [2], respectively.

  Further, as shown in FIGS. 7B and 8A, the main body process is scheduled from the state 3 to the state 7. In the state 3, the values of the first data dat [0] and the second data dat [1] are stored in x and y, respectively. In states 4-1, 4-2, 4-3-1 and 4-3-2, the process of the function gcd2 () is executed.

  In state 4-1, the values of x and y are compared, and if the values are the same, the value of x is stored in t as the greatest common divisor and the state transitions to state 5. In state 4-2, the values of x and y are compared, and if the value of x is large, the state transitions to state 4-3-1, and if the value of y is large, the state transitions to state 4-3-2. In the state 4-3-1, the difference between y and x is stored in y. In the state 4-3-2, the difference between x and y is stored in x. And each returns to the state 4-1. These are repeated while the values of x and y are different. In state 5, the greatest common divisor t of data dat [0] and data dat [1] and the third data dat [2] are stored in x and y, respectively. In the states 6-1, 6-2, 6-3-1 and 6-3-2, the process of the function gcd2 () is executed again. The operation is the same as in states 4-1 to 4-3-2. Finally, in state 7, the return value of the function gcd2 () is stored in the local variable ret.

  As shown in FIG. 8B, output processing is scheduled from state 7 to state 8. In the state 7, the greatest common divisor of the three inputs stored in the local variable ret is output from the output terminal out_dat, and “1” is output from the output terminal done. In the next state 8, “0” is output from the output terminal done.

  In the example of the schedule result, the state 3 in FIG. 7A and the state 3 in FIG. 7B are executed simultaneously. Further, the state 7 in FIG. 8A and the state 7 in FIG. 8B are executed simultaneously.

  FIG. 9 illustrates a block diagram of the synthesized input circuit 121, main body circuit 122, output circuit 123, overall control circuit 124, and register 125. The behavioral synthesis device 100 creates a communication path based on the schedule result as follows.

  The input circuit 121, the main body circuit 122, and the output circuit 123 are circuits expressed by RTL descriptions at respective processing stages generated by the processing stage-specific RTL description generating unit 51. The overall control circuit 124 is a circuit that controls the input circuit 121, the main body circuit 122, and the output circuit 123.

  First, the timing at which the input circuit 121 outputs data and the timing at which the main circuit 122 uses data are compared, and if they are different, a register is prepared for the communication path. In the same case, no register is prepared for the communication path. As described above, the description will be made assuming that the timing for using data and the timing for inputting data are the same timing.

  Specifically, for data dat [0], a register 125 is prepared because the timing at which the input circuit 121 outputs data and the timing at which the main body circuit 122 uses the data are different. Since the data dat [1] has the same timing when the input circuit 121 outputs data and the timing when the body circuit 122 uses data, no register is prepared. For data dat [2], a register 125 is prepared because the timing at which the input circuit 121 outputs data is different from the timing at which the main body circuit 122 uses data.

  Next, the period until the timing at which the input circuit 121 outputs data and the timing at which the main body circuit 122 uses data is compared for each signal, and register sharing is determined. If the periods do not overlap, the registers are shared, and if the periods overlap, the registers are not shared. Since the timings of data dat [0] and data dat [2] do not overlap, the register 125 is shared.

  Next, a communication path between the input circuit 121 and the output circuit 123 is generated. A communication path to be connected without using a register is generated for the data dat [1]. A communication path connected through the shared register 125 is generated for the data dat [0] and dat [2].

  A communication path between the main circuit 122 and the output circuit 123 is generated in the same manner.

  Finally, an RTL description corresponding to the generated communication path is created and stored in the storage device.

  In the circuit synthesized by the behavioral synthesis procedure disclosed in Patent Document 1, the process of the body stage description cannot be started until the process of the input stage description is completed, and until the process of the body stage description is completed. Could not start processing the data output stage description.

  However, as described above, according to the behavioral synthesis device 100 according to the present embodiment, the process of the body stage description can be started without waiting for the completion of the process of the input stage description, and further, the process of the body stage description can be waited for completion. Output stage description processing can be started.

  Specifically, before the input circuit 121 executes the state 4 and completes reception of all input data, the main body circuit 122 starts its processing. The same applies between the main body circuit 122 and the output circuit 123.

  Furthermore, according to the behavioral synthesis device 100 according to the present embodiment, the number of register circuits can be suppressed when generating the register transfer level description from the behavior level description of the semiconductor integrated circuit.

  Specifically, when the timing at which the input circuit 121 outputs data coincides with the timing at which the main body circuit 122 uses data, the communication path for transferring the data is directly connected without using a register. Therefore, the number of registers on the communication path between the input circuit 121 and the main body circuit 122 can be reduced as compared with the case where all registers are prepared corresponding to the transferred data. The same applies to the register on the communication path between the main circuit 122 and the output circuit 123.

  Further, the period until the timing at which the input circuit 121 outputs data and the timing at which the main circuit 122 uses data is compared for each signal, and if the periods do not overlap, the register is shared. For this reason, the number of registers on the communication path between the input circuit 121 and the main body circuit 122 can be further reduced. The same applies to the register on the communication path between the main circuit 122 and the output circuit 123.

  In the above-described embodiment, the input / output timing is specified using the pragma, but the input / output timing can also be specified by other specification methods.

  FIG. 10 shows an example of behavioral description when the input / output timing is designated by a comment. The behavioral description of FIG. 10 differs from FIG. 6 in that the declaration of the input signal in_dat on the second line is the declaration of the input signals a, b, and c (lines 2a, 2b, and 2c), and the eleventh line. The difference is that reading from the input terminal in_dat on the 19th line is reading from the input terminals a, b, c (13th line, 15a, 15b, 15c, 16th line). Also, the input timing is specified as a comment of the input signal, not a pragma.

  FIG. 11A shows an example of an operation description when the input / output timing is specified separately from the operation description. In the behavioral description in FIG. 11A, the input timing is not designated as a comment as compared with FIG. Instead, as shown in FIG. 11B, input signal and timing pairs are specified in a table format. As described above, the method for designating the input / output timing is arbitrary.

  In the above-described embodiment, the program has been described as being stored in the storage device in advance. However, a program for causing the behavioral synthesis device to operate as the whole or a part of the device, or to execute the above-described processing is stored on a flexible disk, a CD-ROM (Compact Disk Read-Only Memory), a DVD (Digital Versatile Disk). ), Stored in a computer-readable recording medium such as MO (Magneto Optical Disk), distributed, installed on another computer, operated as the above-mentioned means, or may be executed the above-mentioned steps .

  Furthermore, the program may be stored in a disk device or the like of a server device on the Internet, and may be executed by being superimposed on a carrier wave and downloaded to a computer.

  As described above, according to the behavioral synthesis device 100 according to the present embodiment, it is possible to start the process of the body stage description without waiting for the completion of the process of the input stage description, and without waiting for the completion of the process of the body stage description. The processing of the output stage description can be started. Furthermore, according to the behavioral synthesis device 100 according to the present embodiment, the number of register circuits can be suppressed when generating the register transfer level description from the behavior level description of the semiconductor integrated circuit.

It is a block diagram which shows the structure of the behavioral synthesis apparatus which concerns on embodiment of this invention. It is a block diagram which shows the basic composition of a behavioral synthesis apparatus. It is a block diagram for demonstrating a behavioral synthesis process. It is a flowchart which shows a behavioral synthesis process. It is a flowchart which shows the communication-path production | generation process shown in the flowchart of FIG. It is a 1st figure which shows an example of a behavior level description. (A) is a figure showing an example of a schedule result of input processing. (B) is a 1st figure showing an example of a schedule result of main part processing. (A) is a 2nd figure which shows an example of the schedule result of a main body process. (B) is a figure showing an example of a schedule result of output processing. It is a block diagram for demonstrating a communication path | route production | generation process. It is a 2nd figure which shows an example of a behavior level description. (A) is a 3rd figure which shows an example of a behavior level description. (B) is a diagram showing the relationship between the input signal and the timing.

Explanation of symbols

11 CPU
12 ROM
13 RAM
14 hard disk device 15 input device 16 display device 20 receiving unit 30 dividing unit 35 CDFG generating unit 40 scheduling unit 50 generating unit 51 RTL description generating unit by processing stage 52 communication path generating unit 53 all RTL description generating unit 100 behavioral synthesis device 110 storage Device 111 Behavior Level Description Storage Unit 112 RTL Description Storage Unit

Claims (7)

A reception unit for receiving an operation level description describing the operation of the semiconductor integrated circuit as a single process ;
The received behavior level description is divided into a data input stage description, a processing body stage description, and a data output stage description as each of a plurality of processes based on a predetermined pragma included in the behavior level description. Splitting part,
A schedule unit that schedules input / output and operation timing for each of the input stage description, the main body stage description, and the output stage description;
A generation unit that generates a register transfer level description that describes the configuration, arrangement, and wiring of the semiconductor integrated circuit based on the input stage description, the main body stage description, the output stage description, and the timing;
With
The generator is
(A) When the output timing of the input stage description and the input timing of the main body stage description match, the output and the input are directly connected. When they do not match, a register circuit is connected between the output and the input. And place
(B) When the output timing of the main body stage description and the input timing of the output stage description match, the output and the input are directly connected. When they do not match, a register circuit is connected between the output and the input. To place,
A behavioral synthesis device characterized by that. The behavioral synthesis device according to claim 1,
The generating unit rearranges so that register circuits that do not overlap the input / output timing of the arranged register circuits are shared.
A behavioral synthesis device characterized by that. The behavioral synthesis device according to claim 1 or 2,
The scheduling unit schedules based on a predetermined pragma included in the behavior level description.
A behavioral synthesis device characterized by that. The behavioral synthesis device according to claim 1 or 2,
The scheduling unit schedules based on a predetermined comment included in the behavior level description.
A behavioral synthesis device characterized by that. The behavioral synthesis device according to claim 1 or 2,
The reception unit further receives additional information for the behavior level description,
The scheduling unit schedules based on the additional information.
A behavioral synthesis device characterized by that. A behavioral synthesis method executed by a behavioral synthesis device including a reception unit, a division unit, a schedule unit, and a generation unit,
An accepting step for accepting an operation level description in which the accepting unit describes the operation of the semiconductor integrated circuit as a single process ;
The dividing unit converts the received behavior level description into a data input stage description, a process body stage description, and a data description as each of a plurality of processes based on a predetermined pragma included in the behavior level description . A split step to split into output stage descriptions,
A scheduling step in which the scheduling unit schedules input / output and operation timing for each of the input stage description, the main body stage description, and the output stage description;
A generating step for generating a register transfer level description that describes a configuration, arrangement, and wiring of a semiconductor integrated circuit based on the input stage description, the main body stage description, the output stage description, and the timing;
With
In the generation step, the generation unit includes:
(A) When the output timing of the input stage description and the input timing of the main body stage description match, the output and the input are directly connected. When they do not match, a register circuit is connected between the output and the input. And place
(B) When the output timing of the main body stage description and the input timing of the output stage description match, the output and the input are directly connected. When they do not match, a register circuit is connected between the output and the input. To place,
A behavioral synthesis method characterized by the above. Computer
A reception unit for receiving an operation level description describing the operation of the semiconductor integrated circuit as a single process ;
The received behavior level description is divided into a data input stage description, a processing body stage description, and a data output stage description as each of a plurality of processes based on a predetermined pragma included in the behavior level description. Splitting part,
A schedule unit that schedules input / output and operation timing for each of the input stage description, the main body stage description, and the output stage description;
A generation unit that generates a register transfer level description that describes the configuration, arrangement, and wiring of the semiconductor integrated circuit based on the input stage description, the main body stage description, the output stage description, and the timing;
A program that functions as
The generator is
(A) When the output timing of the input stage description and the input timing of the main body stage description match, the output and the input are directly connected. When they do not match, a register circuit is connected between the output and the input. And place
(B) When the output timing of the main body stage description and the input timing of the output stage description match, the output and the input are directly connected. When they do not match, a register circuit is connected between the output and the input. To place,
A program characterized by that.

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