JP3488907B2 - Synchronization circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing circuit, and more particularly, to a synchronizing circuit between same frequencies in a logic circuit for device-to-device transmission using a high-speed serial transfer technology such as Fiber Channel.

[0002]

2. Description of the Related Art There are several proposals as a conventional technique for such a synchronizing circuit. For example, in the "jitterless optical transmission method" disclosed in JP-A-2-142231, a read side clock is transmitted to the write side, and data is sent in a state where the write side clock is adjusted to the read side by a PLL (phase locked loop). , Disclose synchronization techniques.

The "synchronization circuit" of Japanese Patent Laid-Open No. 2-56111 prepares a plurality of types of read-side clocks according to the write-side clocks, and selects an optimum read-clock from the clocks for synchronization. Is disclosed.

Further, "FIFO register and data repeater" disclosed in Japanese Patent Laid-Open No. 8-340326 discloses a technique for synchronizing the clock data on the read side, the clock data on the write side, etc. with a high-speed system clock of 6 times or more. .

[0005]

However, in the above-mentioned conventional technique, data is garbled in the case of synchronizing the same frequency, which causes a malfunction. The reason is 2
This is because there is a risk of overtaking or delaying on either the writing side or the reading side due to the difference in accuracy of the two frequencies, resulting in duplicate reading of previous data.

SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable synchronizing circuit which can surely synchronize data even if there is a difference in frequency accuracy in synchronizing data between the same frequencies.

Another object of the present invention is to provide a synchronizing circuit having a simple circuit configuration as compared with the prior art.

[0008]

In order to solve the above-mentioned problems, the synchronizing circuit according to the present invention adopts the following characteristic structure.

(1) A write pointer for receiving a write clock, a register for storing write data based on the output of the write pointer and the write clock, and "H" or "H" depending on the presence of the read clock and the write data.
Valid to receive a valid signal to change to "L"
A signal synchronization circuit, a read pointer that receives the output of the valid signal synchronization circuit and the read clock, and a selector that receives a plurality of outputs of the register and selects the output of the read pointer to output read data. A synchronization circuit provided.

(2) The synchronizing circuit according to (1), wherein the write pointer and the read pointer are counters for counting the write clock and the read clock, respectively.

[0011]

( 3 ) The valid signal synchronizing circuit is
The synchronization circuit according to (1) or (2) above, which is a circuit that outputs a synchronization signal delayed by a plurality of clocks of the read clock from the leading edge of the valid signal.

( 4 ) The write data is the valid
Input to the register via a signal and an AND gate,
The synchronizing circuit according to (1), (2) or (3) above, wherein the read pointer is supplied with a plurality of output stages of the valid signal synchronizing circuit via an OR gate.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION A preferred embodiment of a synchronizing circuit of the present invention will be described in detail below with reference to the accompanying drawings, particularly FIG.

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of each part of the synchronizing circuit of FIG.

First, referring to FIG. 1, the structure of the first embodiment of the synchronizing circuit of the present invention will be described. This synchronization circuit includes a write pointer 11 to which a write clock is input,
A register 13 to which a write clock and write data are input together with the output of the write pointer 11, valid
A valid signal synchronizing circuit 14 to which a signal is input, a read pointer 12 to which a read clock is input together with an output of the valid signal synchronizing circuit 14 and an output of the read pointer 12 and an output of the register 13 are input to read data. The selector 15 for outputting is provided.

Here, the write pointer 11 receives the write clock and the valid signal and outputs the write pointer to the register 13. On the other hand, the read pointer 12
The read pointer is output to the selector 15 in response to the read clock and the valid signal passed through the valid signal synchronization circuit 14. The register 13 has a write clock,
Write data is input together with the write point from the write pointer 11. A plurality of registers 13 are prepared according to the number of pointers indicated by the write pointer 11. v
Valid signal synchronization circuit 1 to which an valid signal is input
4 outputs the synchronized signal to the read pointer 12. The selector 15 receives the data from the register 13 and, by the read point from the read pointer 12,
Select the data from register 13.

Next, the operation of each part of the synchronizing circuit of FIG. 1 will be described with reference to the timing chart of FIG. Figure 2
(A) is a write clock, (b) is write data,
(C) is a valid signal, (d) is a write pointer,
(E) is a read clock, (f) is a synchronized vali
The d signal and (g) indicate the read pointer, respectively. Here, it is assumed that the time lag between the rising edge of the writing clock and the rising edge of the reading clock is always constant.

The valid signal (see FIG. 2 (c)) indicates the validity / invalidity of the data, and the period "L" indicates that the data to be transferred is invalid or does not exist, and "H".
Is the period during which valid data exists.

The write pointer 11 of FIG. 1 is a counter that operates by a write clock and advances the count while the valid signal is valid (that is, during the period of "H"). When there is no write data (when the valid signal is "L"), the counter is reset and returned to 0. This counter starts counting from 0, progresses to 0, 1, 2, 3 and returns to 0 at about 3 or 7, and the valid signal is "H".
During the period, the count-up is continued with 1, 2, 3 ... Normally, it is composed of a binary counter of 2 or 3 bits (see (d) of FIG. 2).

The register 13 is capable of writing and holding data at the position indicated by the write point which is the output of the write pointer 11, and writing is performed based on the write clock. This part can also be composed of a memory. In addition, there are as many light point positions as indicated by the write pointer 11. The bit width of the register 13 depends on the device used. For example, Fiber
A device using the channel has 4 or 8 stages of 10 bits.

The valid signal synchronizing circuit 14 is a clock signal changing circuit for a valid signal indicating a period in which write data exists. The valid signal is a signal synchronized with the write clock and cannot be used as it is on the reading side. For this reason, the read side clock is re-cut three times or more. This re-cutting is performed by a flip crop circuit (not shown), the output of the previous stage is connected to the input of the next stage, and further connected to the next stage (see FIG. 2 (f)).

All the data held by the register 13 is connected to the selector 15, but the read pointer 1
Only the data at the position indicated by 2 is selected and output to be read data. The data is written in the register 13 at the position indicated by the write pointer 11 at the write clock during the period when the valid signal is "H", and is accumulated at each write clock.

On the other hand, as shown in the latter half of the timing chart of FIG. 2, the valid signal is converted by the valid signal synchronizing circuit 14 into a signal synchronized with the read clock (see FIG. 2E). The read pointer 12 advances the read point while the synchronized valid signal (see FIG. 2 (f)) is "H". The selector 15 selects the data at the position indicated by the read pointer 12 from the register 13 and outputs it.

As can be seen from the above description, the data sent in synchronization with the write clock (see FIG. 2A) is temporarily stored in the register 13 and then read with the read clock (see FIG. 2E). It is synchronized by being selectively output.

Next, the configuration and operation of the second embodiment of the synchronizing circuit according to the present invention will be described with reference to FIGS. FIG. 3 is a block diagram showing the configuration, and the elements corresponding to the elements in FIG. 1 are designated by the same reference numerals for convenience. FIG. 4 is a timing chart explaining the operation of each part of the synchronization circuit of FIG.

The synchronization circuit of FIG. 3 has a write pointer 1
1, a read pointer 12, a register 13, a valid signal synchronization circuit 14 and a selector 15 are included in FIG.
It is the same as the synchronizing circuit of. However, in the synchronizing circuit of FIG. 3, an AND gate 21 and an OR gate 22 are further provided in the preceding stage of the register 13 and the preceding stage of the read pointer 12, respectively. That is, the write data is input to the AND gate 21 together with the valid signal, and the output of the AND gate 21 is input to the register 13. Further, the signals of several stages after being synchronized by the valid signal synchronizing circuit 14 are ORed (logical sum) by the OR gate 22 and input to the read pointer 12.

In the first embodiment shown in FIGS. 1 and 2, the phase difference between the write-side clock and the read-side clock is known. However, in the second embodiment, both phases are known. This is the case when the clock phase shift is unknown. Here, “unknown” means that the time difference between the rising of the write clock and the rising of the read clock is unknown although the frequencies are the same.

Next, the operation of the synchronizing circuit shown in FIG. 3 will be described with reference to FIG. (A) is a read clock, (b) is a valid signal A, (c) is a valid signal B, (d).
Is a signal C obtained by synchronizing the valid signal A, and (e) is va.
A signal D obtained by synchronizing the lid signal A, (f) is valid
Signals E and (g) in which the signal B is synchronized indicate a signal F in which the valid signal B is synchronized.

If the phase shift is unknown, the leading edge (edge) is almost the same as the read clock (a).
There are a case like the d signal A (see FIG. 4B) and a case like the valid signal B (see FIG. 4C) whose trailing edges are almost the same.

When the edges of the read clock and the valid signal are substantially the same, the setup and hold times are not satisfied in the normal flip-flop and the valid signal is valid.
There are cases where the signal A can be shuffled and cases where it cannot be shuffled.

When the valid signal A can be re-turned, the valid signal is synchronized to obtain a signal C (see FIG. 4D). On the other hand, if it cannot be re-turned, it becomes like a synchronized signal D (see FIG. 4 (e)). Similarly, if the valid signal B is valid,
Signal E that synchronizes signal B (see FIG. 4 (f)) or val
The synchronization signal F is obtained by synchronizing the id signal B (see FIG. 4 (g)).

In the case of the signal C in which the valid signal A is synchronized, the width of the signal after being synchronized is one clock larger than the width of the original valid signal A. Val after synchronization
Since the read pointer 12 is counting with the id signal, the count is increased and correct data output is not performed.
Further, when both the leading edge and the trailing edge become substantially the same as the read clock, the width becomes wider or narrower, and the read pointer 12
The count may increase or decrease.

Therefore, in the synchronizing circuit of the second embodiment shown in FIG. 3, the AND gate 21 is used,
When there is no valid write data during the period when the d signal is "L", 0 is written in the register 13.

Similarly, the valid signal synchronization circuit 14
Is a clock transfer circuit for a valid signal indicating a period in which write data exists. 3 on the read side clock
Although the re-cutting is performed more than once, it is re-cut by several steps, and the synchronized signals of the third and subsequent steps are ORed by the OR gate 22 to widen the width of the original valid signal and write on the writing side. Read for longer than the period. At this time, the data set to 0 by the AND gate 21 is output during the period other than the original data. Therefore, it should be noted that there is no possibility that old data on the writing side remains on the reading side and erroneous data is output as it is.

Although the preferred embodiment of the synchronizing circuit of the present invention has been described above, this is merely an example, and it is needless to say that various modifications can be made according to a specific application.

[0037]

As can be understood from the above description, according to the synchronizing circuit of the present invention, by resetting the write pointer and the read pointer when there is no data, the influence of the frequency accuracy difference can be eliminated. Data can be transferred reliably by synchronizing between the same frequencies. Further, since there is no need for strict design conditions when using a PLL, a plurality of types of clocks, a high-speed clock circuit of 6 times or more as in the prior art, there is a practically remarkable effect that the configuration is simple.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of a synchronizing circuit of the present invention.

FIG. 2 is a timing chart explaining the operation of each part of the synchronization circuit of FIG.

FIG. 3 is a block diagram showing a configuration of a second exemplary embodiment of a synchronizing circuit of the present invention.

4 is an explanatory diagram of the operation of the synchronization circuit of FIG.

[Explanation of symbols]

11 Light pointer 12 Read pointer 13 registers 14 valid signal synchronization circuit 15 selector 21 AND gate 22 OR gate

Continuation of the front page (56) Reference JP-A-5-14325 (JP, A) JP-A-4-373336 (JP, A) JP-A-1-255335 (JP, A) JP-A-2-56111 (JP , A) JP 8-340326 (JP, A) JP 2-142231 (JP, A) JP 9-135236 (JP, A) Actually open 2-118341 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 7/00

Claims (4)

(57) [Claims] 1. A write pointer that receives a write clock, a register that stores write data based on the output of the write pointer and the write clock, and "H" or "L" depending on the presence of the read clock and the write data.
And a valid signal synchronization circuit which receives the valid signal changes, the read pointer for receiving the output and the read clock of the valid signal synchronization circuit, a plurality of outputs of said register are entered to select the output of the read pointer And a selector that outputs read data. Wherein said write pointer and read pointer are serial to claim 1, characterized in that a counter for counting each said write clock and read clock
On-board synchronization circuit. 3. The valid signal synchronization circuit comprises:
Multiple clocks of the read clock from the leading edge of the alid signal.
Is a circuit that outputs a synchronization signal delayed by
The synchronization circuit according to claim 1 or 2 . 4. The write data is the valid signal together with the valid signal.
Input to the register via an AND gate,
The valid pointer includes a plurality of valid signal synchronization circuits.
The stage output is input through an OR gate.
The synchronization circuit according to claim 1, 2 or 3.