JP3484914B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates also relates to a semiconductor device,
In particular, the present invention relates to a technique for connecting wirings and the like that require a large amount of current to flow.

[0002]

2. Description of the Related Art Since a large amount of current flows in a power supply wiring or the like, it is necessary to reduce contact resistance, and therefore it is necessary to provide a large number of contact holes in one connection region.

On the other hand, in order to reduce the parasitic capacitance between the upper and lower wirings to reduce the signal transmission delay, it is necessary to make the interlayer insulating film thick. However, if the film thickness is thick, the aspect ratio of the contact hole becomes large. , Step coverage of metals such as aluminum deteriorates. As a countermeasure against this, it is often practiced to use both wet etching and dry etching (two-step etching), provide a wide hole in the surface portion, and then form a thin vertical hole by dry etching.

However, the inventors of the present invention have found that when a large number of contact holes are formed in the connection portion of the above-mentioned power supply wiring or the like by using the two-stage etching technique in the VLSI, a problem occurs in forming the contact holes. It became clear by.

[0005]

That is, for example, in the case of forming a large number of contact holes in the connection portion of the above-mentioned power supply wiring or the like under the minimum design rule, if a photoresist mask is formed and wet etching is performed. The wide holes formed by the wet etching are connected to each other, and as a result, the portion supporting the photoresist mask is lost, and the portion is lifted and peeled off. In this case, in the portion where the resist is peeled off, even if dry etching is performed thereafter, accurate hole formation cannot be performed.

The above situation can be avoided by easing the design rules and arranging contact holes with more margin. Therefore, although partial peeling of the photoresist mask can be prevented, it is against the miniaturization of IC. However, the degree of integration is reduced.

Therefore, an object of the present invention is to form a plurality of contact holes by using the two-step etching without causing a decrease in the degree of integration, and to enable a good connection such as wiring having a high current capacity. is there.

[0008]

The present invention for solving the above-mentioned problems has the following configuration.

(1) A semiconductor device according to a first aspect of the present invention comprises an insulating film provided on a semiconductor substrate, and a plurality of contact holes provided so as to penetrate a part of the insulating film. The plurality of contact holes are arranged with a two-dimensional spread, and each contact hole has a cross-sectional shape in which a wide hole and a narrower hole are connected, and the two-dimensional spread is provided. In the above, there is a portion where the wide holes of the adjacent contact holes are connected to each other and a portion where the surface portion of the insulating film is continuously left without being connected. .

The remaining portion of the insulating film supports the photoresist when the wide hole is opened, and as a result, partial peeling of the photoresist is prevented.

That is, according to the experiments by the present inventor, even if the wide holes formed by wet etching are partially connected, there is a certain degree of periodicity in the remaining portions which are not connected and are not connected. It was found that, if so, it is possible to prevent the photoresist from falling and to form a desired contact hole. Therefore, while keeping the design rules, devise the formation position of the contact hole, that is,
By introducing a partial irregularity in the arrangement, it is possible to form a good contact hole.

In this specification, the term "contact hole" includes both a hole for connection between wirings and a hole for connection between wirings and a semiconductor element (diffusion layer formed on a substrate). Used in a broad sense. That is, the “contact hole” is a concept including “via hole” and “through hole”.

(2) The present invention according to claim 2 provides the contact hole according to claim 1, wherein the contact holes arranged in a two-dimensional manner are connected to a power supply wiring or a ground wiring and a semiconductor element or another wiring. It is used for.

The present invention is applied to a power supply line or the like having a high current capacity that requires a large amount of current to flow.

(3) The present invention according to claim 3 relates to connection of wirings or semiconductor elements belonging to different layers,
In the connection region, a contact hole having a cross-sectional shape described in (1) below is arranged by the method described in (2) below. (1) Shape of Contact Hole The contact hole has a cross-sectional shape in which a wide hole and a narrower hole are connected.

(2) Method A matrix is constructed by virtual m (m is a natural number of 2 or more) X grids and virtual k (k is a natural number of 2 or more) Y grids. Here, the intersections of the X and Y grids indicate the positions where the contact holes can be arranged.

Interval (pitch) between X and Y grids
Is set so that when the contact holes are arranged at the adjacent intersections of the matrix, the wide holes of both contact holes are connected to each other.

When arranging the contact holes at the intersections of the X and Y grids, the contact holes are appropriately thinned in order to prevent the wide holes from being completely connected. Deploy. At this time,
The intersections where the contact holes are thinned are at least locally continuous.

A method for realizing the structure according to claim 1 is provided. The contact hole position is defined by virtual X and Y grids, and at least locally continuous points are targeted for thinning, whereby a continuous portion of the insulating film is left.

(4) The present invention according to claim 4 is characterized in that, in claim 3, thinning of the contact holes is periodically performed.

The stability of supporting the photoresist is ensured by periodically leaving the continuous portion of the insulating film. Also, layout design becomes easy.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

(1) Shape of Contact Hole Used in this Embodiment In this embodiment, as shown in FIG. 6A, a contact hole is formed by two-step etching. In FIG. 6, reference numeral 200 is a semiconductor substrate, and reference numeral 60
Reference numeral 610 is a photoresist, reference numeral 610 is a wide hole formed by isotropic etching such as wet etching, and reference numeral 620 is dry etching (RIE).
It is a thin hole formed by anisotropic etching such as.

(2) Examples of locations where contact holes are formed FIG. 4 shows an example of places where contact holes are formed.

In FIG. 4, the wirings drawn from the power supply pad 100 and the ground pad 110 are the aluminum wirings of the first layer, and the wirings 150a and 150 shown by the thick lines.
b and 150c are aluminum wiring of the second layer, contact holes K1 to K3 are contact holes for connecting the power wiring of the first layer and the power wiring of the second layer,
The contact hole K4 is a contact hole for connecting the first-layer ground wiring and the second-layer ground wiring.

The contact holes Q1 to Q4 are C
This is a contact hole for connecting the diffusion layer forming the MOS inverter (consisting of the p-type MOSFET 130 and the n-type MOSFET 120) and the aluminum wiring.

As shown by the one-dot chain line on the right side of FIG. 4, the contact holes K3 (K1 to K4 are the same),
In order to carry a large amount of current, it is actually formed as a large number of sets of contact holes (Pi) of the same size. On the other hand, contact hole Q3 (same for Q1, Q2, Q4)
Consists of one contact hole (Pi). IC is based on the standardized contact hole (Pi)
This is because it is desirable that common design rules be applied in the design of.

(3) Description of Design Rule The design rule indicates a rule in IC design. The minimum line width, the allowable current density, the diameter of the contact holes, the distance between the contact holes, etc. Stipulated. As a general rule, the design rule is commonly applied without distinguishing the power supply line section and the internal logic section.

For example, as shown in FIG. 5, as a result of applying the common design rule, contact holes (Pi) are formed.
The widths L1 to L7 are the same. The reference numbers of the devices in FIG. 5 are the same as the reference numbers of the portion surrounded by the alternate long and short dash line on the right side of FIG. 4 and the reference numbers of the transistors forming the CMOS inverter. Reference numeral 200 is a semiconductor substrate, reference numeral 300 is a surface protective film, and reference numerals 400 and 500 are interlayer insulating films.

(4) Arrangement example of a plurality of contacts on the power supply line and the ground line As a method for determining the positions of a plurality of contacts, for example,
As shown in FIG. 1A, a matrix (a grid having a two-dimensional spread) consisting of vertical and horizontal grids is formed on a computer screen, and contact points can be arranged at intersections of the grids. There is a method for designing the layout as a place. In this embodiment, using this method,
Determine the placement of multiple contacts on the power and ground lines. The interval (pitch) of each grid is appropriately set according to the applied design rule.

In the case of FIG. 1 (a), four grids x1 to x4 in the horizontal direction and nine grids y1 to y9 in the vertical direction define the positions where contacts can be arranged, and the positions of the intersections. Contact holes are arranged without exception. That is, white circles attached to the intersections of the grids in FIG. 1A indicate that contact holes are formed.

As described above, when the contact holes are arranged at all the intersections of the grids and the minimum design rule is applied to improve the integration degree, the pitch between the grids becomes narrow. In some cases, wide holes formed by wet etching are connected to each other. At this time, as shown in FIG.
In some cases, the photoresist 600 may fall (or float up), resulting in defective patterning in the subsequent dry etching process. Reference numerals 622a and 622b in FIG. 6B show examples of the patterning-defective holes generated in this manner. Reference numeral 622a is an example where the diameter of the contact hole is too large, and reference numeral 622b is an example where the diameter of the contact hole is too small. Although not shown, the contact hole may be displaced due to the deformation of the photoresist described above.

If the design rule is relaxed in order to avoid the above-mentioned inconvenience, the degree of integration will decrease. Therefore, in the present embodiment, as shown in FIG.
Contact holes are periodically thinned. That is,
The contact holes in the grids y3, y6, y9 are thinned out. In FIG. 1B, the black circles at the intersections of the grids indicate that the contact holes are thinned out.

The lower part of FIG. 1B shows a schematic sectional shape of the device in the vicinity of the intersection of the vertical grids y2, y3, y4 and the horizontal grid x4. In the figure, reference numeral 20 is an insulating film, and reference numeral 32
a and 32b are contact holes corresponding to the grids y2 and y4, respectively, and the reference numeral 100 remains without connecting the wide holes by thinning the contact holes at the intersections of the grid y3 and the grid x4. It shows the part where The remaining portion 100 without connecting the wide holes effectively supports the photoresist, which prevents the photoresist from falling.

FIG. 2 is a schematic perspective view of the insulating film 20 after the contact holes are formed. The hatched portions (100a, 100c) on the surface of the insulating film indicate the continuous portions remaining after etching. Note that reference number 1
00b indicates a portion remaining in a portion sandwiched by wide holes (32h, 32i, etc.).

As described above, even if the wide holes formed by wet etching are partially connected, as long as the remaining portions which are not connected and have a certain periodicity, the photoresist is It is possible to form a desired contact hole by preventing the contact hole from falling. Further, a desired design rule can be applied to form a plurality of high current capacity contact holes at high density.

Modifications are shown in FIGS. 3 (a), 3 (b) and 3 (c). In FIG. 3, the arrangement of contact holes is shown by a 4 × 4 matrix. Similar to the above example, white circles indicate positions where contact holes are formed, and black circles indicate positions where contact holes are thinned.

In FIG. 3A, the contact holes are thinned out every two rows. In FIG. 3B, two thinning points (points indicating thinning positions of contact holes) are paired to perform periodic thinning. In FIG. 3C, each grid is alternately thinned out one by one, that is, in a so-called staggered pattern. It should be noted here that in each of the examples, the thinning points are at least locally continuous. The fact that the thinning points are continuous means that the surface of the insulating film remaining without connecting the wide holes is at least locally continuous, as illustrated in FIG.

On the other hand, when the thinning points are independent and do not satisfy the local continuity, and the thinning points are isolated, it is impossible to reliably prevent the photoresist from dropping or rising. .

FIG. 3 merely shows a model of thinning points, and the grid to be thinned or the continuity or period of the thinning points can take various modes depending on the device.

As described above, according to the present invention, a plurality of contact holes are formed by using the two-step etching without deteriorating the degree of integration, and good connection such as wiring with high current capacity is realized. To be done.

[0042]

[Brief description of drawings]

FIG. 1A is a diagram showing an example in which contact holes are arranged at every intersection of grids, and FIG. 1B is a diagram showing an example in which contact holes are periodically thinned and arranged.

FIG. 2 is a diagram schematically showing a state of an insulating film when the contact holes shown in FIG. 1 (b) are thinned out.

3A to 3C are diagrams schematically showing another example of arrangement of contact holes.

FIG. 4 is a diagram showing an example of a formation location of a contact hole.

FIG. 5 is a diagram showing a cross-sectional structure of a semiconductor device.

6A is a diagram showing a cross-sectional shape of a contact hole formed by two-step etching, and FIG. 6B is a diagram for explaining the inconvenience made clear by the present inventor.

[Explanation of symbols]

20 Insulating films 32a, 32b Contact holes 100 Portions x1 to x4, y1 to y9 which are not removed by wet etching and remain continuously Grid

Claims (2)

(57) [Claims] 1. An insulating film provided on a semiconductor substrate, and a plurality of contact holes provided through a part of the insulating film, wherein the plurality of contact holes have a two-dimensional spread. Arranged, each contact hole has a wide hole,
It has a cross-sectional shape that connects with a thinner hole, and
Within the two-dimensional spread, there are a portion where the wide holes of the adjacent contact holes are connected to each other and a portion where the surface portion of the insulating film is continuously left without being connected. A semiconductor device characterized by the above. 2. The semiconductor according to claim 1, wherein the contact holes arranged with the two-dimensional expansion are used for connecting a power supply wiring or a ground wiring to a semiconductor element or another wiring. apparatus.