JP3482744B2 - Image collection device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image collecting apparatus for sampling an image signal representing a still image and collecting digital-valued image information, and in particular, image data whose original image has high resolution (high dot clock). The present invention relates to an image acquisition device that enables acquisition.

[0002]

2. Description of the Related Art In recent medical systems, MRI is used.
Various image diagnostic apparatuses such as a CT scan, an ultrasonic diagnostic apparatus, and an ultrasound diagnostic apparatus are used. If the diagnostic images of the same subject obtained from a plurality of types of diagnostic devices can be centrally managed, more efficient diagnosis can be performed.

Therefore, it is considered to construct a system in which a plurality of types of diagnostic devices are connected to a computer that manages images and the diagnostic images collected from the diagnostic devices are accumulated in the image management computer. However, many existing diagnostic devices do not have digital outputs. Therefore, in order to construct a system as described above using a diagnostic device without digital output, the monitor output of the diagnostic device (analog video output for displaying an image on a monitor display connected to each diagnostic device) It is necessary to have a device that takes in the data, performs AD conversion, and outputs it to the computer system.

A video capture board compatible with so-called NTSC composite signals and YC separation signals is known as a device for sampling analog video signals and AD-converting them to obtain digital image data. This board is connected to a bus such as a personal computer, and in the case of a composite signal, it is separated into a luminance signal and a chrominance signal (Y
In the case of a C separated signal, Y corresponds to a luminance signal and C corresponds to a chrominance signal and is supplied as a separated signal from the beginning), respectively, AD converted, converted into a format such as RGB and stored in a memory. . The stored image data is transferred to the video memory via the bus and displayed.

[0005]

[Problems to be Solved by the Invention] NTSC as described above
In a video capture board that handles image data of signals, a sampling frequency (hereinafter referred to as a dot clock frequency) required to obtain a resolution equivalent to that of an original analog image is about 12-13 MHz at most. However, in recent years, the resolution is higher and the dot clock frequency is about 100 MHz (the dot clock cycle is 10
Monitors that need to be about ns) are being used, and there is an increasing demand for capturing such high resolution images.

The AD converter capable of sampling at such a high sampling frequency is not only expensive, but also the AD converter having a sufficiently large dynamic range (having a large number of bits per clock) cannot be selected. There has been a problem that a writing circuit for a memory or the like becomes complicated, resulting in an expensive product.
Japanese Patent Laid-Open No. 63-109675 proposes a method of solving such problems and performing AD conversion of a high-resolution still image using a low-speed and inexpensive AD converter. In this method, a still image signal is sampled with sampling pulses whose phases are shifted by 1 / N (N is an integer of 2 or more) for each frame to generate digital image signals of N frames, and these are stored in one frame memory. By writing to each of the N frames of the frame memory (1 frame of digital image signal is written to every N addresses of the frame memory), which is N times the original conversion frequency of the AD converter (hereinafter, referred to as an equivalent sampling frequency). The digital image signal of is obtained. However, the above "conventional technology"
In the case of constructing a medical system as exemplified in the above item, there is often an environment in which a plurality of types of diagnostic devices manufactured by a plurality of manufacturers are mixed. The specifications of the monitor output of the diagnostic device are not unified and there are various resolutions. Therefore, it is desirable to be able to handle these various monitor outputs. Furthermore, since the equivalent sampling frequency required to obtain the desired resolution is often unknown, the user can perform an instruction operation to select the optimum equivalent sampling frequency while monitoring (visually recognizing) the AD-converted digital image. It is desirable to configure it.

The present invention has been made in order to solve such a problem, and has various equivalent sampling frequencies.
The present invention provides a device for AD-converting an analog image signal of (equivalent sampling period) and collecting it as a digital image signal.

[0008]

In order to solve such a problem, the image collecting apparatus of the present invention uses an input analog image signal for each frame with a delay amount Td = Ts / Fn.
(However, Ts is a sampling period for AD conversion, Fn is the number of frames.) AD conversion is performed by using sampling signals whose phases are shifted by each phase to convert into a digital image signal of Fn frame per primary color An image collecting apparatus configured to store an image signal as a digital image signal having an equivalent sampling period Td in a readable format, wherein the means for generating the sampling signal is a horizontal synchronizing signal of the analog video signal. Synchronous clock generating means for generating a clock signal having a synchronized period T ₀ , and using the synchronous clock signal,
A period T that is _{equal to} or longer than the minimum conversion period Ts _min that can be AD-converted
s, and a sampling original signal generator that generates a sampling original signal whose phase changes by a cycle T ₀ , and a minimum delay time Td for the input sampling original signal.
_A delay circuit unit that gives a delay i times (i is an integer of 0 to M−1) _min (= T ₀ / M), and a phase of each clock cycle T ₀ in order to create a sampling signal whose phase is shifted.
A control unit for performing control to instruct the sampling original signal generation unit to change the amount of phase change , and to perform control to instruct the delay circuit unit to provide a delay amount i times the minimum delay time Td _min given to the sampling original signal; Composed by.

According to the above configuration, the minimum conversion period Ts
It is possible to perform AD conversion of analog image signals of various equivalent sampling periods smaller than the minimum conversion period Ts _min by using an AD converter having a large _min (that is, a maximum conversion frequency is small) and collect them as digital image signals. Becomes In particular, the sampling original signal generator generates a sampling original signal whose phase is shifted by the period T ₀ , and the sampling original signal is multiplied by i (i) of the minimum delay time Td _min (= T ₀ / M) in the delay circuit unit. Is characterized by being configured to give a delay of 0 to M-1).
This is not only complicated in the delay circuit, but also disadvantageous in accuracy, when it is attempted to realize all the required delay amounts by a delay circuit such as a delay line. For this reason, the delay circuit divides the period T _{0 of the} synchronous clock into 1 / M to give the minimum delay time Td _min, and the sampling original signal generator generates a delay amount which is an integral multiple of the synchronous clock T _0. Configured to do so.

This delay circuit section has a minimum delay time T, for example.
a delay line having at least M tap outputs for giving a delay amount i times d _min (i is an integer of 0 to M−1); and a selection circuit for selecting and outputting tap outputs of the delay lines. It may be configured by. Also, regarding the phase shift given to the sampling original signal and the delay amount given by the delay circuit section, the j-th (j is an integer of 0 to Fn−1)
When the digital image signal of the frame is generated, the quotient value S and the remainder J obtained by the division formula (Td / Td _min × i) / M are obtained, and the horizontal synchronizing signal is supplied to the sampling original signal generator. The instruction to generate the sampling original signal with the phase shift of S × T ₀ and the instruction to select the delay amount J × Td _{min to} the delay circuit section may be performed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to the drawings. First, a configuration example and an operation example of an image collecting apparatus to which the present invention is applied will be described with reference to FIGS. 1 to 3. This image collecting device takes in R, G, and B component signals, converts them into digital image signals, and stores them in a memory 8. The digital image signal stored in the memory 8 is output to an external device (for example, a personal computer having a monitor and an input device) via the interface unit 9. Further, a control signal designating the equivalent sampling frequency Td is supplied from the external device to the interface unit 9.
Be captured via. This control signal is sent to the sampling signal generating section 1, the select signal generating section 3, and the memory control signal generating section 7 to perform an operation (described later) corresponding to the equivalent sampling Td designated by the control signal. (Sampling signal generator 1, select signal generator 3, and memory control signal generator are provided with independent control means such as MPU, and control corresponding to the equivalent sampling signal Td designated in advance is performed by this control means. It suffices to incorporate a micro program, etc.) When the sampling frequency Td is instructed by an external device, the sampling signal generator 1 creates a sampling signal corresponding to each frame based on the sampling frequency Td and supplies it to the AD converter 2. It is a thing. Further, 3 is a select signal generator, which is an output prohibiting signal / DISR, / DISG, / D.
The output of the component signal is selected by sending the ISB to the preamplifiers 41 to 43 provided for each color of the RGB component signal, and only the selected component signal is supplied to the clamp / gain circuit 5 of the next stage. .

The AD converter 2 is for AD-converting the input analog image signal, and the minimum sampling period that can be converted is Ts _min . Clamp /
The gain circuit 5 is a circuit for adjusting the DC level and gain of the signal. The AD converter 2 converts the output signal of the clamp / gain circuit into a digital value with the sampling clock generated by the sampling signal generator 1.

The sync signal extraction unit 6 enables any input of a horizontal / vertical composite sync, a composite sync csync, and a vertical sync vsync on the video signal, and extracts a horizontal sync signal / HD and a vertical sync signal / VD from them. It is a thing. The memory control signal generator 7 is for writing the digital signal output from the AD converter 2 into the memory 8, and selects a write plane and generates a write address (this control will be described later).

FIG. 2 is a diagram for explaining the outline of the operation of the image collecting apparatus shown in FIG. In FIG. 2, (a) shows the dot clock signal of the analog image signal, and (b)
Represents the luminance signal of the analog image signal. When the frequency of the dot clock signal in (a) is high, AD conversion cannot be performed by the AD converter 2 in FIG. 1. Therefore, as shown in (c), the phases are shifted by Td in order to perform AD conversion in a plurality of frames. Create multiple sampling clocks.

In FIG. 2, the period Tdotclk of the dot clock signal (a) of the analog image signal and the phase shift Td of the sampling clock are different. In the present invention, this is the period Tdot of the original dot clock signal of the analog image signal.
This is because clk is assumed to be unknown, and the user performs an instruction operation to change the equivalent sampling frequency while monitoring the display output of the external device. Since the image acquisition device of the present invention can accurately obtain digital images of various equivalent sampling frequencies (cycles),
The dot clock signal is suitable for AD converting an unknown analog signal.

Next, a method of collecting RGB image signals will be described with reference to FIG. FIG. 2 shows an example in which three frames are needed for each color, that is, a total of nine frames are required to collect one still image. FIG. 3A shows the vertical synchronizing signal / VD supplied to the select signal generator 3 and the start signal for instructing the start. One frame of a still image is input at the cycle of the vertical synchronizing signal / VD.

In FIG. 3B, the R image signal is collected in the first 3 frames, and the G image signal and the B image signal are collected every 3 frames thereafter. CLK1, CLK2
CLK3 indicates three types of sampling clocks having the same frequency but different phases. CLK in the first frame and C in the first frame for collecting the R image signal
In the LK2 and 3rd frames, AD conversion is performed using a sampling clock having a different phase for each frame, such as CLK3. Similarly, image signals of other colors are A-converted with high resolution by performing AD conversion using sampling clocks having different phases for each frame.
It becomes possible to perform D conversion.

As shown in FIG. 3 (c), the sampling clock may be switched every three frames, and the color image signal may be switched every one frame. In any case, Fn per primary color can be obtained by performing AD conversion with sampling clocks that are shifted by phase Td for each frame.
By generating a digital image of the frame, there is no change in obtaining a digital image signal of the equivalent sampling frequency Td.

As described above, the method of collecting RGB image signals (which color of the image signal is AD-converted and collected, and which sampling clock is used) is predetermined, so that the select signal generator 3 and the memory are used. Control signal generator 7
Recognizes a frame delimiter based on the vertical synchronization signal and performs a process corresponding to the current frame. Specifically, the select signal generator outputs the preamplifiers 41 to 43 so that only the image signals of the colors to be collected are output to the clamp / gain circuit 5.
Control the output inhibit signal sent to.

Further, the memory control signal generating section 7 selects a plane of a corresponding color, and when the same color is divided into Fn frames for AD conversion, the write address is stored for each Fn address. For example, when performing AD conversion using three frames for each primary color as described above, the addresses are 1, 4, 7 ... In the first frame, 2, 5, 8 in the second frame.
... address, in the third frame, digital values may be written at addresses 3, 6, 9 ... The digital image signal thus written can be reproduced as a digital image having an equivalent sampling period Td by reading out the addresses one by one.

Regarding the configuration in which the AD-converted digital image signal of the Fn frame is stored in a format that can be read as a digital image signal of the equivalent sampling period Td, the example of FIG. Alternatively, a plurality of memory planes for each primary color may be provided and one plane may be allocated for each frame. In this case, the digital image having the equivalent sampling period Td can be reproduced by sequentially switching the reading planes at the time of reading. However, the feature of the present invention is that it is possible to collect digital images of various equivalent sampling frequencies (cycles), and the number of frames per primary color also changes depending on the equivalent sampling cycle. Unnecessary planes may appear. Therefore, from the viewpoint of efficient use of memory, the configuration example of FIG. 1 is considered to be preferable.

In order to speed up AD conversion, R
You may employ | adopt the structure which provides three AD converters corresponding to each of GB3 primary color. In this case, the select signal generator 3 becomes unnecessary. With such a configuration, A
Although the cost increases due to the increase in the number of D converters, since the image signal can be AD converted for each primary color, the collection time can be shortened.

Next, an example of a concrete structure and operation of the sampling signal generator 1 will be described with reference to FIGS. 4 to 6. FIG. 4 is a block diagram showing a configuration example of the sampling signal generator 1. The synchronous clock generation unit 11 in the figure is a clock signal (cycle T) output by the free-running oscillator 10.
₀ ) is synchronized with the horizontal synchronizing signal / HD to generate a synchronizing clock of period T ₀ . Further, the sampling original signal generator 12 has a cycle of Ts based on this synchronous clock.
Then, the sampling original signal whose phase is shifted by To is generated. The operations of the synchronous clock generator 11 and the sampling original signal generator 12 will be described with reference to FIG.

FIG. 5A shows a clock signal of the cycle T ₀ generated by the oscillator 10. Synchronous clock generator 11
When the horizontal synchronizing signal / HD as shown in (b) is input, the synchronizing clock (FIG. 5 (c)) is generated by synchronizing the clock signal generated by the oscillator with the horizontal synchronizing signal / HD. Based on the instruction from the control unit 14, the sampling original signal generation unit 12 has a cycle of Ts based on this synchronous clock.
, The sampling original signal ORGC whose phase is shifted by T ₀
Create K0 to ORGCK5 (any of them). It is an example of this original signal. The phase of the sampling original signal to be generated is determined based on an instruction from the control unit 14 described later.

The delay circuit section 13 comprises a delay line 131 and a selection circuit 132. Delay line 1
Reference numeral 31 denotes a delay of i times (i is an integer of 0 to M−1) of the minimum delay time Td _min (= T ₀ / M) to the sampling original signal generated by the sampling original signal generating unit 12, and M It has tap outputs. The selection circuit 132 selects tap output of the delay line according to an instruction from the control unit 14.

FIG. 6 illustrates the operation of the delay circuit section 13. Original sampling signal ORGC shown in (a)
K is 0, Tdmin, 2Tdmin, 3Tdmin, ... as shown in (b).
Such a delay of i times Td _min (i is an integer of 0 to M−1) is given. The ACTIVE signal in (c) defines the valid data for memory writing, and is determined by the number of frames Fn for collection, the frame count value at writing, and CLKi.

The control unit 14 controls the period T of the original sampling signal.
s and the phase shift amount corresponding to the frame currently being processed are instructed to the sampling original signal generation unit 12, and the delay amount selected by the delay circuit unit 13 is instructed respectively. To obtain these values, it is first necessary to calculate the number of frames required for each equivalent sampling period. An example of this calculation will be described.

For example, the clock frequency generated by the oscillator 10 is 50 MHz (To = 20 ns), and the delay line 131
Is assumed to be composed of 8 steps (M = 8) with tap interval Tdmin = 2.5ns. That is, the delay amount is 0, 2.5,
Selectable from 5, 7.5, 10, 12.5, 15, 17.5ns. The highest conversion frequency that can be converted by the AD converter 2 is 10 MHz (that is, the minimum conversion period Ts _min = 100 ns). [Example 1] When the equivalent sampling frequency is 25 MHz, the equivalent sampling period Td is 40 ns, so it is necessary to sample at a point of 0 40 80 (120) ns. But using A
The sampling period of the D converter needs to be 100 ns or more. In this case, the sampling clock cycle is 120n
Set to s (= 8.33MHz) and shift the phase by 40ns each time 3 times (3
Frame) Collect the data. [Example 2] When the equivalent sampling frequency is set to 200 MHz, it is sufficient to sample at the point of 0 5 10 15 20 25 30 .... (100) ns. In this case, the sampling clock cycle is 100 ns (= 10 MHz), the phase is shifted by 5 ns, and the data may be collected 20 times (20 frames).

More generally expressed. Now, one tap length is Td _min = 2.5 ns. Also, the period T of the synchronization clock
_It can be expressed by ₀ = 20 ns = 8 Td _min . On the other hand, the amount of phase shift to be given for each frame is 40 ns in Example 1.
= 16 Td _min , and in Example 2, 5 ns = 2 Td _min
Becomes Therefore, a value obtained by converting the amount of phase shift into the minimum delay time Td _min of the delay line (in the example below, TA
P)) for each frame, and the remainder of 8 (lower 3 bits) of that value is the delay line tap selection value.
(See DELSEL below), the value obtained by dividing the cumulative value by 8 is the selection signal for each To in the sampling original signal generator (OR below
It is understood that it is good to use (see GSEL).

That is, with respect to the above Examples 1 and 2, the tap selection value DE of the delay circuit unit 13 when a digital image signal of j frames (j is an integer of 0 to Fn−1) is generated.
Phase shift OR between sampling source signal generator 12 and LSEL
GSEL looks like this: (In the example below, the numbers with h indicate hexadecimal numbers.) Example 1) Phase shift amount TAP = 10h ・ Td _min Frame number j = 0h 1 2 TAP * j = 0h 10h 20h ORGSEL = 0h 2h 4h DELSEL = 0h 0h 0h Example 2) Phase shift amount TAP = 2h ・ Td _min Frame number j = 0 1 2 3 4 5 6 7 8 9 TAP * j = 0h 2h 4h 6h 8h ah ch eh 10h 12h ... ORGSEL = 0h 0h 0h 0h 1h 1h 1h 1h 2h 2h ... DELSEL = 0h 2h 4h 6h 0h 2h 4h 6h 0h 2h ... As described above, the j-th (j is an integer from 0 to Fn-1) frame When a digital image signal is generated, a quotient value S and a remainder J obtained by a division formula (Td / Td _min × j) / M are obtained, and the sampling original signal generating unit shifts the phase from the horizontal synchronizing signal. Is S
Instructing to generate a sampling original signal of × T ₀ ,
The delay circuit unit may be controlled to instruct the delay circuit unit to select the delay amount J × Td _min .

[0031]

According to the present invention, analog image signals can be converted into various equivalent sampling frequencies (equivalent sampling periods).
It is possible to obtain a digital image that has been AD-converted in step (3) and to obtain a digital image with high conversion accuracy.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of the overall configuration of an image collecting apparatus of the present invention.

FIG. 2 is a diagram illustrating a relationship between an analog image signal and a sampling clock in the image acquisition device in FIG.

FIG. 3 is a diagram illustrating a method of collecting RGB image signals in the image collecting apparatus of FIG.

FIG. 4 is a block diagram showing a configuration example of a sampling signal generator.

FIG. 5 is a diagram illustrating operations of a synchronous clock generation unit and a sampling original signal generation unit.

FIG. 6 is a diagram illustrating an operation of a delay circuit section.

[Explanation of symbols]

1 Sampling signal generator 10 oscillators 11 Synchronous clock generator 12 Sampling original signal generator 13 Delay circuit section 131 delay line 132 selection circuit 14 Control unit 2 AD converter 3 Select signal generator 41-43 preamplifier 5 Clamp / gain circuit 6 Sync signal extractor 7 Memory control signal generator 8 memory 9 Interface section

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-63-109675 (JP, A) JP-A-2-67883 (JP, A) JP-A-2-309773 (JP, A) JP-A-7- 143424 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 5/44 H04N 7/00 H03H 17/02 H03M 1/12

Claims (4)

(57) [Claims] 1. A sampling signal in which a phase of an input analog image signal is shifted by a delay amount Td = Ts / Fn (where Ts is a sampling period for AD conversion, Fn is the number of frames) for each frame is used. Image collection configured to convert into a digital image signal of Fn frame per primary color by performing AD conversion and to store the digital image signal of the Fn frame as a digital image signal having an equivalent sampling period Td in a readable format In the apparatus, the means for generating the sampling signal has a period T ₀ synchronized with a horizontal synchronizing signal of the analog video signal.
And a period Ts that is equal to or longer than a conversion minimum period Ts _min that can be AD-converted by using the synchronous clock signal.
A sampling original signal generator that generates a sampling original signal whose phase changes by _0, and a minimum delay time Td for the input sampling original signal.
a delay circuit unit that gives a delay i times (i is an integer of 0 to M−1) _min (= T ₀ / M), and in order to create the phase-shifted sampling signal,
Along with performing control to instruct the sampling original signal generation unit to change the amount of phase change for each clock cycle T ₀ , the minimum delay time Td _min given to the sampling original signal
And a control unit that controls the delay circuit unit to instruct the delay circuit unit to delay i times as much as . 2. The delay circuit section comprises a minimum delay time Td _min.
A delay line having at least M tap outputs for giving a delay amount i times (i is an integer of 0 to M−1) and a selection circuit for selecting and outputting tap outputs of the delay lines. The image acquisition device according to claim 1, wherein 3. The control unit is the j-th (where j is 0 to Fn-1).
In the case of generating a digital image signal of a frame of an integer), a quotient value S and a remainder J obtained by the division formula (Td / Td _min × j) / M are obtained and horizontally synchronized with the sampling original signal generator. The phase shift from the signal is S
Instructing to generate a sampling original signal of × T ₀ ,
The control for instructing the delay circuit unit to select a delay amount J × Td _min is performed.
The image acquisition device described in. 4. An image collecting apparatus for collecting an input analog image signal as a digital image signal having an equivalent sampling period Td, wherein the digital image signal having the equivalent sampling period Td has a delay amount Td = Ts for each frame. / Fn (however, Ts
Is a sampling period for performing AD conversion, and Fn is the number of frames). By performing AD conversion using a sampling signal whose phase is shifted by, a primary color is converted into a digital image signal of Fn frame, and from the digital image signal of the Fn frame, A synchronous clock generation unit that generates a clock signal having a clock cycle T ₀ synchronized with the horizontal synchronous signal of the analog video signal, and an AD having a conversion minimum cycle Ts _min or more that can be AD-converted using the synchronous clock signal. Sampling cycle T for conversion
generates s sampling the original signal, and the said sampling original signal clock period T ₀ by a phase changeable sampling the original signal generating section, the clock period T minimum delay time Td 1 for M minutes _0
min delay is possible, and the minimum delay time Td
_A delay circuit unit that gives a delay i times (i is an integer from 0 to M-1) _min (= T0 / M), and a clock cycle T in order to create a sampling signal whose phase is shifted by the delay amount Td. _By instructing the sampling original signal generating section to change the phase by _0, and instructing the delay circuit section to delay i times the minimum delay time Td _min , the phase shifted by the delay amount Td can be set. An image acquisition device configured to generate the sampling signal by a control unit that generates.