JP3479559B2 - Frequency phase comparator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency phase comparator suitable for use in a phase locked loop circuit or a motor phase control circuit.

[0002]

2. Description of the Related Art In recent years, with the advent of digital audio such as satellite broadcasting, a digital-analog converter for processing audio signals sampled at different sampling frequencies has been popular in the market. Here, for example, the transfer rate of digital audio of satellite broadcasting is about 0.8 Mbit / sec in A mode stereo and about 1.5 Mbit / sec in B mode stereo. In order to cope with such different transfer rates, it is necessary to provide a phase locked loop circuit (hereinafter abbreviated as "PLL") that follows the transfer rate of the digital audio signal sent to the above apparatus. If a phase comparator having only a phase comparison function is used for such a PLL, it cannot be used because the pull-in range becomes narrow, and a frequency phase comparator having a frequency comparison function is necessary.

Conventionally, as such a frequency phase comparator, a circuit as shown in FIG. 3 has been generally used. In FIG. 3, reference numerals 20 and 21 denote periodic pulse signals.
Flip-flop received by the lock terminal , 22 is an inverter, 23 is an AND circuit, 26 is a P-type metal oxide semiconductor field effect transistor (hereinafter referred to as “M
OSFET ") and 27 are N-type MOSFETs. 28 is a power supply terminal, which is connected to the power supply V _DD . The transistors 26 and 27 are push-pull connected.
Output circuit.

The operation of the conventional frequency / phase comparator configured as described above will be described below. The D flip-flop 20 has one input D terminal suspended at the power supply voltage V _DD , and the clock terminal C receives the signal F _REF . The Q output terminal of the D flip-flop 20 is input to the inverter 22 through the node A, and the AND circuit 23
Connected to one of the input terminals. The output of the inverter 22 is input to the gate of the P-type MOSFET.

On the other hand, the D flip-flop 21 also has one input D terminal suspended from the power supply voltage V _DD , and the clock terminal C receives the signal F _VCO . The Q output terminal of the D flip-flop 21 is connected to the other input terminal of the AND circuit 23 through the node B, and the N-type MOSFE
Input to the gate of T27. The output of the AND circuit 23 is connected to the reset input terminals of the D flip-flops 20 and 21. When both nodes A and B are high, the output of AND circuit 23 goes high and D flip-flops 20 and 21 are reset.

Now, FIG. 4 shows a signal waveform diagram of each portion of the circuit of FIG. Waveform F _REF is D flip-flop 2
0 is input and the waveform F _VCO is the D flip-flop 21.
Is input. The lower three waveforms A to C are nodes A to C.
Respectively correspond to. Waveform F _VCO respect to the waveform F _REF in the figure, if the interval t ₁ the phase is delayed, the interval t ₂ shows a case where the case, and progressed interval t ₃ the phase both phases match .

The Q terminal outputs of D flip-flops 20 and 21 are used to control MOSFETs 26 and 27. The output of this frequency phase comparator appearing at node C is when only MOSFET 26 is on, ie in the interval t ₁
When the output of the power supply voltage V _DD appears, and only the MOSFET 27 is on, that is, when the output of the ground appears during the period t ₃ , both MOSFETs 26 and 27 are off,
That is, when there is no input to the section t ₂ or any of the D flip-flops 20 and 21, it is always in a high impedance state.

[0008]

However, in the above-mentioned conventional configuration, when the phase difference between F _REF and F _VCO is small, the output pulse widths of the nodes A and B are narrow, so that M
Depending on the frequency characteristics of the OSFETs 26 and 27, the output pulse may disappear, which results in the input / output characteristics shown in FIG.
There is a problem that a dead zone such as that shown in FIG.

Such a frequency / phase comparator can be implemented by, for example, P
When it is used for LL, it may not be able to accurately follow the input frequency, and it may cause a symptom that the PLL apparently oscillates in the dead zone, that is, "bang-bang mode" may occur. There is a problem.

The present invention solves the above problems.
It is an object of the present invention to provide a frequency phase comparator which is essentially free of dead zones in input / output characteristics.

[0011]

In order to achieve this object, a frequency phase comparator of the present invention comprises a first flip-flop with a reset terminal for receiving a first periodic pulse signal at a clock terminal, and a first flip-flop having the reset terminal. A first delay means for delaying the output of the first flip-flop by a predetermined time τ _{1, a} second flip-flop with a reset terminal for receiving a second periodic pulse signal at its clock terminal, and this second flip-flop Is delayed by a predetermined time τ ₂ and the output of the second delay means and the output of the first delay means is subjected to a logical product operation, and the logical product outputs are A logic circuit that is applied to each reset terminal of the second flip-flop to reset the first and second flip-flops, and one of the first and second transistors that are push-pull connected. The output from the first flip-flop is input, in which an output from said second flip-flop to the other, characterized in that it consists of an output circuit that is input.

[0012]

According to this structure, the propagation of the pulse applied to the reset terminals of the first flip-flop and the second flip-flop is delayed and the width of the pulse output from the first flip-flop and the second flip-flop is reduced. The width becomes wider, and the first and second transistors forming the output circuit are surely made to respond.

[0013]

[Action] According to the configuration of claim 1, said by pulse addition means and by Tsu <br/> the pulse generating means generates a pulse to each output of said first flip-flop and the second flip-flop By adding a pulse, the push
The first and second transistors connected in a pull-up connection surely respond .

With respect to the present embodiment configured as described above,
The operation will be described with reference to the signal waveform diagram of FIG.
The first delay circuit 10 delays the Q output of the D flip-flop 20 by time τ ₁ , and the second delay circuit 11 delays the Q output of the D flip-flop 21 by time τ ₂ .
The reason why the delay times are made different from each other is that the output of the D flip-flops 20 and 21 is changed to the MOSFET 2
This is because the time until transmission to 6 and 27 differs depending on the arrangement on the mask, and this is to be corrected. Therefore, it may be considered that the delay times τ ₃ (= τ ₁ = τ ₂ ) are substantially the same.

As a result, the result of taking the logical product by the AND circuit 23 is delayed by the time τ _3, so that the reset timing of the D flip-flops 20 and 21 is delayed by τ ₃ . As a result, the width of the pulse output from each of the D flip-flops 20 and 21 is extended by the time τ ₃ . As a result, the MOSFETs 26 and 27 are surely made to respond. In addition, the first delay circuit 1
Despite the fact that 0 and the second delay circuit 11 are provided, there is no time delay in the phase comparison result, so the stability of the PLL is not impaired.

In the above embodiment, the logic circuit is composed of the AND circuit 23, and the output circuit is the inverter 22 and the plug circuit.
First and second transistors 26 and 2 connected in a shuffle
It is composed of 7 .

Although the reset terminals of the D flip-flops 20 and 21 are made high active in the above embodiments, the AND circuit may be replaced with a NAND circuit by making them low active. Further, the first delay circuit 12 and the second delay circuit 13 may be realized by a gate delay, or may be realized by providing a first-order delay element by a resistor and a capacitor. Besides, the present invention can be variously modified.

[0018]

As described above, in the frequency phase comparator of the present invention, the output of the first flip-flop is provided with the first delay means, and the output of the second flip-flop is provided with the second delay means. it allows the pulse propagation delay applied to the reset terminal of the first flip-flop and the second flip-flop the first flip-flop and the second flip
Since the width of the pulse output from the flip-flop is widened and a pulse for surely responding to the first and second transistors forming the output circuit can be supplied, a dead zone does not occur in the input / output characteristics.

Furthermore, since the delay time shift due to the difference in the layout on the mask can be corrected when integrated into a circuit, the dead zone removal performance is further improved. Also,
Even if the first delay means and the second delay means are provided, there is no time delay in the phase comparison result, and therefore the stability of the PLL is not impaired.

Therefore, when the frequency phase comparator of the present invention is used, for example, in a PLL, it can follow the input frequency accurately and there is no dead zone of the input / output characteristics.
A more stable PLL can be configured without generating a mode.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a frequency phase comparator according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram of a main part of the frequency phase comparator in the example.

FIG. 3 is a circuit diagram of a frequency phase comparator in a conventional example of the present invention.

FIG. 4 is a signal waveform diagram of a main part of the frequency phase comparator in the conventional example.

FIG. 5 is an input / output characteristic diagram of the frequency phase comparator in the conventional example.

[Explanation of symbols]

10 First delay circuit 11 Second delay circuit 20,21 D flip-flop 22 Inverter 23 AND Circuit 26, 27 MOSFET

Claims (2)

(57) [Claims] 1. A first flip-flop with a reset terminal for receiving a first periodic pulse signal at a clock terminal, and a first delay means for delaying the output of the first flip-flop by a predetermined time τ _1. , A second flip-flop with a reset terminal for receiving the second periodic pulse signal at its clock terminal, a second delay means for delaying the output of the second flip-flop by a predetermined time τ _2, and AND the output of the first delay means, and apply the AND output to the reset terminals of the first and second flip-flops to obtain the first and second flip-flops. Output from the first flip-flop is input to one of the first and second transistors connected in push-pull and the second flip-flop is connected to the other. An output circuit output from the flop is input, frequency phase comparator consisting of. 2. The predetermined time τ ₁ and the predetermined time τ ₂ are
The frequency phase comparator according to claim 1, which is different from each other.