JP3479467B2 - Crystal oscillator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field of application of a crystal oscillator in which a crystal element and a circuit element are mounted on a ceramic base, and in particular, a bypass capacitor (as a bypass capacitor) between a power source and ground is formed on the ceramic base itself to form a circuit. The present invention relates to a surface-mount crystal oscillator in which an element is an IC (integrated element) chip only.

[0002]

BACKGROUND OF THE INVENTION Crystal oscillators are widely used in telecommunications and digital equipment as frequency and time reference sources. 2. Description of the Related Art In recent years, a surface-mounted crystal oscillator in which a crystal piece and a circuit element are housed in a ceramic container and which is miniaturized has become widespread.

(Example of Prior Art) FIGS. 6 and 7 are diagrams of a crystal oscillator for explaining a conventional example of this type. FIG. 6 is a sectional view, and FIG. 7 is an exploded view excluding the cover. The crystal oscillator includes a crystal container 13 and a circuit element 2 that form an oscillation circuit in a ceramic container 1.

The ceramic container 1 comprises a ceramic base 3 and a ceramic cover 9 sealed with glass, for example.
The ceramic base 3 includes a bottom wall layer 4, an intermediate frame layer 5 and an upper frame layer 6.
And are laminated and integrally formed by firing. The bottom wall layer 4 and the intermediate frame layer 5 form a hole portion 7 in the central portion, and the intermediate frame layer 5 and the upper frame layer 6 form step portions 8 at both ends.

A circuit pattern is formed on the bottom wall layer 4, and mounting terminals 10 are formed on the side surfaces and the back surface of the four corners formed by through holes.
Extend as (abcd). Mounting terminal 10 (abc
d) consists of power supply, ground, output and standby terminals. In the step portion 8 of the intermediate frame layer 5, the terminal electrode 11 and the bottom wall layer 4 are provided.
The electrode through hole 12 connected to the circuit pattern is formed.

The oscillation circuit (see FIG. 8) is composed of a crystal piece 13
And the IC chip 14 and the bypass capacitor 15 as the circuit element 2.
Consists of. The crystal piece 13 has excitation electrodes 19 on both main surfaces,
The extraction electrodes 20 are extended to both ends. Then, both ends are fixed to the step portion 8 of the ceramic base 3 and the terminal electrode 11
IC chip 1 through the electrode through hole 12
4 is connected to the vibrator electrode pattern 24 connected to the input / output terminal 4.

The IC chip 14 includes an inverter amplifier 16 and a feedback resistor 1 which form an oscillation circuit together with the crystal piece 13.
7 and the oscillation capacitor 18 (ab) are integrated. Then, the IC chip 14 and the decap 15 are fixed to the hole 7 of the ceramic base 3 and connected to the circuit pattern. In the figure, a buffer amplifier, a standby function element, etc. integrated in the IC chip 14 are omitted.

[0008]

Problems to be Solved by the Invention (Problems of Prior Art)
However, in the crystal oscillator having the above configuration, the bypass capacitor 15 between the power supply and the ground has a very large capacitance of, for example, 1000 to 10000 pF and cannot be integrated, and thus it must be accommodated in the ceramic container as an independent chip element. Therefore,
There was a problem that it could not be simplified by increasing the number of parts.

Further, the area of the hole 7 of the ceramic base 3 is inevitably large, and the crystal blank 13 cannot be made small. The chip element as the bypass capacitor 15 is
It is taller than the IC chip 14. from these things,
The chip element as the bypass capacitor 15 has also been a factor that hinders the miniaturization of the crystal oscillator.

From this, for example, Japanese Patent Laid-Open No. 5-3024
According to Japanese Patent Laid-Open No. 3 (1993), the unit bottom wall layer 21 (ab
The interfacial electrode 25 (abcd) is provided between cd) to form a multilayer capacitor to be the ceramic base 3 (see FIG. 1 described later). Then, a package in which the multilayer capacitor is applied to the bypass capacitor 15 between the power supply and the ground is disclosed.

However, when such a ceramic base 3 is simply applied to a crystal oscillator, a capacitance is formed between the electrode pattern formed on the surface of the uppermost unit bottom wall layer 21a and the interface electrode 25a on the back surface side. To form. In particular, the electrode pattern 24 connected to the excitation electrode 19 of the crystal blank 13
Capacitances C1 and C2 between (ab) are the oscillation capacitor 1
Since 8 (ab) is connected in parallel (Fig. 9), there is a problem that the capacitance value of the oscillation capacitor is increased.

In this case, the crystal oscillator is designed by exceeding the upper limit of the capacitance value of the oscillation capacitor 18 formed in the IC chip or increasing the variation in the load capacitance seen from the crystal unit. Will be adversely affected.

(Object of the Invention) The present invention provides a crystal oscillator in which a multilayer capacitor is formed on a ceramic base, the number of parts is reduced, simplification and miniaturization are promoted, and the influence on the oscillation capacitor is small. The purpose is to

[0014]

According to the present invention, a ceramic base having a laminated structure is provided with an interface electrode on each laminated surface to form a laminated capacitor, which is applied to a decap and the surface of the uppermost unit ceramic base is formed. The basic solution is to make the capacitance value generated between the formed vibrator electrode pattern and the back surface side interface electrode smaller than that in the case of forming the unit ceramic base forming the multilayer capacitor. Specifically, for example, the thickness of the uppermost unit ceramic base is increased, the dielectric constant is decreased, or the vibrator electrode and the interface electrode are not opposed to each other.

[0015]

In the present invention, since the multilayer capacitor is formed on the ceramic base to form the bypass capacitor between the power source and the ground, the chip element as the bypass capacitor becomes unnecessary. Since the capacitance value between the vibrator electrode pattern and the back surface side interface electrode is made smaller than that in the case where it is formed in the unit ceramic base forming the multilayer capacitor, the influence on the oscillation capacitor is reduced. An embodiment of the present invention will be described below.

[0016]

1 and 2 are views of a crystal oscillator for explaining one embodiment of the present invention, FIG. 1 is a sectional view, and FIG. 2 is an exploded view of a bottom wall layer. It should be noted that the same parts as those of the prior art example are given the same reference numerals, and the description thereof will be simplified or omitted. The crystal oscillator includes a ceramic base 3, a crystal piece 13 and an IC chip 14.
Only wear it. The ceramic base 3 is composed of the bottom wall layer 4 forming the hole portion 7 and the step portion 8, the intermediate frame layer 5 and the upper frame layer 6 as described above. And the bottom wall layer 4 in this embodiment
Is a plurality of unit bottom wall layers 21 (abc) having the same dielectric constant.
The laminated structure of de) is used. The top unit bottom wall layer 21a
Is set to be larger than the thickness of the second layer and below, and a circuit pattern including the above-mentioned vibrator electrode pattern 24 is formed on the surface.

On the surface of the second unit bottom wall layer to the lowest unit bottom wall layer 21 (bcde), the interfaces facing each other between the unit bottom wall layers 21 (bcde) except the uppermost layer. Electrodes 25 (abcd) are formed to form a multilayer capacitor. Of the interface electrodes 25 (abcd), the odd-numbered 25 (ac) is connected to the mounting terminal 10a for the power source on the side wall of the corner, and the even-numbered 25 (bd) is the mounting terminal 10 for grounding.
Connect to b.

For example, a copper paste is screen-printed on each unit bottom wall layer 21 (bcde) excluding the uppermost layer 21a of the green sheet, and after the uppermost layer 21a is laminated, the intermediate frame layer 5 and The upper frame layer 6 is further laminated and integrally fired.

In such a structure, since the bottom wall layer 4 forms the multilayer capacitor between the mounting terminals 10a and 10b for the power source and the ground, the chip element as the bypass capacitor 15 becomes unnecessary. Therefore, since only the IC chip 14 needs to be housed in the hole 7, the size can be reduced. Therefore, the crystal oscillator can be simplified and downsized by reducing the number of parts.

Further, in this embodiment, the unit bottom wall layer 21 (bcd) having the thickness of the uppermost unit bottom wall layer 21a equal to or less than the second layer is used.
The capacitance between the vibrator electrode pattern 24 and the first-layer interface electrode 25a is reduced. Therefore, the capacitance added to the oscillation capacitor 18 (ab) built in the IC chip 14 can be reduced to be within the allowable value. Also, a crystal unit (crystal piece 13)
The variation in the load capacity seen from the point of view can be reduced to facilitate the design.

[0021]

[Other Matters] In the above embodiment, the uppermost unit bottom wall layer 21a
Although the capacitance with the vibrator electrode pattern 24 has been reduced to a smaller value, the dielectric constant of the uppermost unit bottom wall layer 21a is made smaller than that of the unit bottom wall layer 21 (bcd) of the second or lower layer. May be. In this case, the thickness can be reduced, which is advantageous. Further, the non-opposing region may be formed by removing the portion of the uppermost layer interface electrode 25a that faces the vibrator electrode pattern 21a (not shown).

In short, the capacitance value generated between the vibrator electrode pattern 24 of the uppermost unit bottom wall layer 21a and the interface electrode 25a on the back side is set to the unit bottom wall layer 21 (bc) of the second or lower layer.
It is a requirement of the present invention to make the size smaller than the case formed in d). Normally, the oscillation capacitor 18 (ab) formed in the IC chip is 10 to 25 pF,
On the other hand, if the increase in the capacitance due to the vibrator electrode pattern 24 is about ⅕ or less, the influence on the design and the variation can be prevented.

Further, in the above embodiment, only the bypass capacitor 15 between the power source and the ground is formed as a laminated capacitor, but it can be applied to the case where the coupling capacitor 22 is provided side by side with the output as shown in FIG. 3, for example. Then, the hole 7 is provided only on one main surface of the ceramic base 3 to accommodate the crystal piece 13 and the IC chip 14, but the hole is provided on both main surfaces of the ceramic base to connect the crystal piece 13 and the IC chip 14. It may be housed separately. 4 and 5 are diagrams showing an example of this,
FIG. 4 is a sectional view, and FIG. 5 is a view of the bottom wall layer (excluding the uppermost layer) of the ceramic base 3.

That is, holes are provided in both main surfaces of the ceramic base 3, the crystal piece 13 is housed on one main surface side to cover the cover 9, and the IC chip 14 is housed on the other main surface. A circuit pattern (not shown) is formed on the other main surface. The unit bottom wall layer 21 is formed on the surface of each unit bottom wall layer 21 (bcde) excluding the uppermost layer 21a that forms the bottom wall layer 4.
Two first and second interface electrodes 2 facing each other (bcd)
5A (ad) and 25B (ad) are formed on the left and right. In this case, since the circuit pattern is formed on the other main surface side, the lowest unit bottom wall layer is the highest unit bottom wall layer 2 in the figure.
1a.

Then, the left first interface electrode 25A (a ...
d) is a mounting terminal 10a for power supply and ground for every other sheet,
Connect to 10b. Also, the second interface electrode 25B on the right side
(A to d) are alternately connected between the mounting terminals 10c for output and the output electrode end of the IC chip 14 which is commonly connected by the side surface electrode 26 and is formed on the surface of the uppermost layer (not shown). . By doing so, the chip element as the bypass capacitor 15 of the power source and the coupling capacitor 22 of the output can be eliminated, the number of parts can be further simplified, and the miniaturization can be further promoted.

In the above embodiment, the ceramic base 3 is used.
Although the IC chip 14 is housed in the hole 7 of the, the crystal base 13 and the IC chip 1 are formed by using the ceramic base 3 as a flat plate, for example.
4 may be provided side by side or provided on the front and back (not shown). Also in this case, a ceramic base corresponding to the bottom wall layer 4 is formed from a plurality of unit ceramic bases to form the interface electrode 2
5 may be formed. In addition, the unit bottom wall layer 21 (bcd
Although the interface electrode 25 (abcd) is formed on the surface of e), for example, the electrodes may be formed on both main surfaces of the even-numbered unit bottom wall layer, in short, the electrode is formed on the interface of the unit bottom wall layer. It should be done.

Although the ceramic base 3 is covered with the ceramic cover 9 sealed by glass to form the ceramic container 1, the cover may be resin-sealed or may be seam welded as a metal. Further, in the embodiment, the ceramic base 3 is expediently described as the five unit bottom wall layers 21 (abcde), but it goes without saying that the number may be more than this.

In short, according to the present invention, the bypass capacitor 15 having a large capacitance, especially between the power source and the ground, is formed of a ceramic-based laminated capacitor, and the oscillation capacitor 18 is used.
The purpose is to eliminate the influence on (ab) and to simplify and miniaturize the crystal oscillator by minimizing the number of parts. Techniques based on such a purpose, including various modifications, are included in the technology of the present invention. Belong to the target range.

[0029]

INDUSTRIAL APPLICABILITY According to the present invention, a ceramic base has a laminated structure and an interface electrode is provided on each laminated surface to form a laminated capacitor, which is applied to a decap and a vibrator formed on the surface of the uppermost unit ceramic base. The capacitance value generated between the electrode pattern for the back surface and the interface electrode on the back side is smaller than that of the case where it is formed on the unit ceramic base forming the multilayer capacitor, so the number of parts is reduced and simplification and miniaturization are promoted. In addition, it is possible to provide a crystal oscillator that has a small influence on the oscillation capacitor.

[Brief description of drawings]

FIG. 1 is a sectional view of a crystal oscillator for explaining an embodiment of the present invention.

FIG. 2 is an exploded view of a ceramic-based bottom wall layer illustrating an embodiment of the present invention.

FIG. 3 is an oscillator circuit diagram for explaining another embodiment of the present invention.

FIG. 4 is a sectional view of a crystal oscillator for explaining another embodiment of the present invention.

FIG. 5 is an exploded view of a bottom wall layer excluding a top layer of a ceramic base, which illustrates another embodiment of the present invention.

FIG. 6 is a sectional view of a crystal oscillator for explaining a conventional example.

FIG. 7 is an exploded view of a crystal oscillator for explaining a conventional example.

FIG. 8 is a circuit diagram of a crystal oscillator for explaining a conventional example.

FIG. 9 is a partial circuit diagram of a crystal oscillator illustrating a problem of a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ceramic container, 2 circuit elements, 3 ceramic base, 4 bottom wall layer, 5 middle frame layer, 6 upper wall layer, 7 hole part, 8 step part, 9 ceramic cover, 10 mounting terminals,
11 terminal electrodes, 12 electrode through holes, 13 crystal pieces, 1
4 IC chips, 15 decaps, 16 inverter amplification elements, 17 feedback resistors, 18 oscillation capacitors, 1
9 excitation electrode, 20 extraction electrode, 21 unit bottom wall layer, 2
2 coupling capacitor, 23 conductive adhesive, 24 vibrator electrode pattern.

Claims (4)

(57) [Claims] 1. A ceramic base, wherein a multilayer capacitor is formed by interposing an interfacial electrode between a plurality of unit ceramic bases, and the multilayer capacitor is used as a bypass capacitor between a power supply and ground, and a top unit ceramic base of the ceramic base. An electrode pattern for a vibrator formed on the surface of the substrate and electrically connected to the excitation electrode of the crystal piece, and the vibrator.
Inverter whose input and output ends are electrically connected to the electrode pattern for
A crystal oscillator comprising an oscillation IC chip having a built-in amplifier element , comprising: an oscillator electrode pattern of the uppermost unit ceramic base and an interface electrode on a back surface side of the uppermost unit ceramic base. The capacitance value generated between is compared with the case of forming the unit ceramic base forming the multilayer capacitor,
A crystal oscillator characterized by being made smaller. 2. The crystal oscillator according to claim 1, wherein the uppermost unit ceramic base is thicker than the thickness of another unit ceramic base forming the multilayer ceramic base. 3. The non-opposing region according to claim 1, wherein an interface electrode is not formed on a part of a back surface of the uppermost unit ceramic base facing the electrode pattern for the vibrator, and a non-opposing region is provided. Crystal oscillator. 4. The crystal oscillator according to claim 1, wherein the uppermost unit ceramic base is smaller than the dielectric constant of another unit ceramic base forming the multilayer ceramic base.