JP3479457B2 - Plasma display panel - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly to a strong discharge generated by involving a large number of discharge cells at a peripheral boundary portion of an image display area which is a portion where an image of the plasma display panel is actually displayed. The present invention relates to a plasma display panel that stably displays a clear image by suppressing the occurrence of abnormal discharge.

[0002]

2. Description of the Related Art In a plasma display panel, electric charges are abnormally accumulated at a peripheral boundary portion of an image display area, which is a portion displaying an image on the plasma display panel, and the electric potential rises. The problem is the occurrence of abnormal discharge, which is a strong discharge caused by the inclusion of the. Once the abnormal discharge occurs, the abnormal discharge generation part may not be able to display an image for several seconds, and the discharge cell may be destroyed. This phenomenon is an essential problem of the plasma display panel, and has become apparent as the definition and the brightness of the plasma display panel become higher.

Conventionally, as measures against the above-mentioned abnormal discharge, (1) as shown in Japanese Patent Laid-Open No. 10-64432, the dielectric of the back plate located at the top and bottom of the display screen of the plasma display panel is removed. A method of exposing the address electrodes and discharging the accumulated charges by using electric conduction of the address electrodes, (2)
As disclosed in JP-A-69858, a method is provided in which a constantly lit region is provided in the outermost peripheral portion of the plasma display panel, and electric charges in the constantly lit region are used to discharge and remove accumulated charges. As disclosed in Japanese Patent Laid-Open No. 64-43434, a method of mixing conductive particles in a dielectric material forming a back plate for holding address electrodes and discharging electric charges accumulated by utilizing electric conduction of the dielectric material is adopted. It had been.

[0004]

[Problems to be Solved by the Invention] Conventional (1), (2)
The above method is effective only when the entire surface of the panel is used as the display area, and the abnormal discharge cannot be prevented when only a part of the panel is used as the display area. The method (3) is also effective when any area of the panel is used as the display area. However, the dielectric constituting the back plate is formed by firing, and it is difficult to fire the dielectric containing the conductive particles without losing the conductivity of the conductive particles.

The present invention has been made in view of the above-mentioned various problems, and effectively moves the wall charges formed on the back plate instead of using the electric conduction as shown in the conventional example. It is an object of the present invention to provide a high-definition and high-brightness plasma display panel capable of preventing electric charge from being accumulated and suppressing abnormal discharge to stably display a clear image by preventing the electric charge.

[0006]

The present invention adopts the following means in order to solve the above problems.

A first substrate, a plurality of address electrodes arranged in parallel on the first substrate, and a first dielectric layer that covers the address electrodes and forms a partition between the address electrodes. A first panel, a second substrate, a pair of sustain electrodes composed of a plurality of sets of X sustain electrodes and a Y sustain electrode arranged side by side on the second substrate, and a second cover for covering the plurality of electrode pairs. And a second panel including a dielectric layer, the address panel and the sustain electrode pair are substantially orthogonal to each other, and
In a plasma display panel arranged so as to face each other so that a discharge space is formed between a first panel and a second panel, an electrostatic charge formed by a portion of the first dielectric layer facing the discharge space. The capacitance is 0. of the capacitance formed by the second dielectric layer facing the discharge space.
It is characterized by being 85 times or more.

Further, a first substrate, a plurality of address electrodes arranged in parallel on the first substrate, and a first dielectric layer covering the address electrodes and forming a partition between the address electrodes. And a second substrate, and a plurality of sets of X sustain electrodes and a pair of sustain electrodes formed of Y sustain electrodes arranged in parallel on the second substrate, and the plurality of sets of electrode pairs. Second comprising a second dielectric layer
The first panel and the second panel, the address electrode and the sustain electrode pair are substantially orthogonal to each other,
Further, in a plasma display panel arranged so as to face each other so that a discharge space is formed between the first panel and the second panel, a portion of the discharge space facing the X sustain electrode and the Y sustain electrode pair has the first electrode. The capacitance formed by the first dielectric layer is 0.8 of the capacitance formed by the second dielectric layer facing the discharge space.
Plasma display panel characterized by being 5 times or more.

Also, a first substrate, a plurality of address electrodes arranged in parallel on the first substrate, and a first dielectric layer that covers the address electrodes and forms a partition between the address electrodes. And a second panel, and a sustain electrode pair composed of a plurality of sets of X sustain electrodes and Y sustain electrodes arranged in parallel on the second substrate, and covering the plurality of electrode pairs. A second panel including a second dielectric layer, wherein the address panel and the sustain electrode pair are substantially orthogonal to each other in the first panel and the second panel,
In the plasma display panel, which is arranged so as to face each other so that a discharge space is formed between the first panel and the second panel, the first dielectric layer in a portion of the discharge space facing the Y sustain electrode. The plasma display panel is characterized in that the capacitance formed by the above is 0.85 times or more of the capacitance formed by the second dielectric layer facing the discharge space.

Also, a first substrate, a plurality of address electrodes arranged in parallel on the first substrate, and a first dielectric layer that covers the address electrodes and forms a partition between the address electrodes. And a second panel, and a sustain electrode pair composed of a plurality of sets of X sustain electrodes and Y sustain electrodes arranged in parallel on the second substrate, and covering the plurality of electrode pairs. A second panel including a second dielectric layer, wherein the address panel and the sustain electrode pair are substantially orthogonal to each other in the first panel and the second panel,
Further, in the plasma display panel, which is arranged so as to face each other so that a discharge space is formed between the first panel and the second panel, the first dielectric layer in a portion of the discharge space which does not face the Y sustain electrode. The plasma display panel is characterized in that the capacitance formed by is less than 0.85 times the capacitance formed by the second dielectric layer facing the discharge space.

Further, a first substrate, a plurality of address electrodes arranged in parallel on the first substrate, and a first dielectric layer that covers the address electrodes and forms a partition between the address electrodes. And a second panel, and a sustain electrode pair composed of a plurality of sets of X sustain electrodes and Y sustain electrodes arranged in parallel on the second substrate, and covering the plurality of electrode pairs. A second panel including a second dielectric layer, the address panel and the sustain electrode pair being substantially orthogonal to each other, and the first panel and the second panel. In a plasma display panel arranged so as to face each other so that a discharge space is formed between two panels, the discharge space is formed by the first dielectric layer in a portion not facing the X sustain electrode and Y sustain electrode pair. A plasma display panel, wherein the electrostatic capacitance is less than 0.85 times the capacitance formed by the second dielectric layer facing the discharge space.

Further, in the plasma display panel, the first dielectric layer is provided with a blast protective layer having a film thickness of 1 μm or more.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is an external perspective view of the plasma display panel according to the present embodiment, FIG. 2 is a right sectional view of FIG. 1, and FIG. 3 is a perspective view of an electrode arrangement viewed from the upper surface of FIG.

The structure of the plasma display panel will be described below with reference to these drawings.

In these figures, 1 is a front glass substrate, which is arranged on the side of the plasma display panel on which the display light is emitted. Reference numeral 2 is a back glass substrate, 3 is an X sustain electrode formed of a transparent conductive film, 3a is a bus electrode attached to one side end of the X sustain electrode, and the resistance of the transparent conductive film is reduced to drive the voltage of the sustain electrode. make it easier.
4 is a Y sustain electrode formed of a transparent conductive film, and 4a is Y
It is a bus electrode attached to one end of the sustain electrode,
The resistance of the transparent conductive film is reduced to facilitate voltage driving of the sustain electrodes. Reference numeral 5 is a dielectric layer that covers the X sustain electrode, the Y sustain electrode, and the bus electrodes 3a and 4a.
The dielectric layer 5 is composed of a plurality of dielectric layers. 6 is an address electrode formed on the rear glass substrate 2, 7 is a rear plate dielectric formed on the address electrode 6, and is composed of a phosphor layer. Reference numeral 8 is a partition wall formed so as to partition the address electrodes 6, and 9 is a discharge space.

Although not shown, a sandblast protective layer made of an insulating material is formed on the address electrode 6 with a film thickness of 1 μm or more. The partition wall 8 is formed by grinding and removing the discharge space 9 by sandblasting an insulating plate which is formed in a flat plate shape in advance. The sandblast protection layer is formed in order to prevent the address electrodes 6 from being scraped during the sandblast process.

The front glass substrate and the rear glass substrate thus formed are combined so that the sustain electrodes 3 and 4 and the address electrode 6 are substantially orthogonal to each other and the discharge space 9 is formed. The discharge space 9 is about 100 μm, and the discharge space 9 is filled with a mixed gas containing a rare gas such as Ne and Xe as a main component. In this way, the X sustain electrodes 3, Y
The sustain electrode 4 and the address electrode 6 facing these electrodes form a discharge cell. The X sustain electrode 3 and the Y sustain electrode 4 are directed from one end side (hereinafter, referred to as an upper part) of the front glass substrate 1 constituting the plasma display panel to the other end (hereinafter, referred to as a lower part) as shown in FIG. The Y sustain electrode 4, the X sustain electrode 3, the Y sustain electrode 4, the X sustain electrode 3, ... Are arranged in this order to form a so-called three-electrode surface discharge type plasma display panel.

FIG. 4 is a diagram showing an example of a driving state of the three-electrode surface discharge type plasma display panel. In the figure, 10 represents one frame. One frame 10
Has a duration of 16.7 ms. 11 to 16 are subfields, and one frame 10 is divided into, for example, 6 subfields 11 to 16. Reference numerals 17, 18, and 19 denote a reset discharge period, an address discharge period, and a sustain discharge period, which will be described later, respectively.
Each subfield 11 to 16 has a reset discharge period 1
7, an address discharge period 18 and a sustain discharge period 19. The sustain discharge period in each subfield 11 to 16 is a weighted period,
For example, assuming that the sustain discharge period of the subfield 11 is 1, the sustain discharge period of the subfield 12 is 2,
Subfield 13 has a sustain discharge period of 4, subfield 14 has a sustain discharge period of 8, subfield 15 has a sustain discharge period of 16, subfield 1
The 6 sustain discharge periods are set to have 32 weights. By repeating the display of the subfields 11 to 16 set in this way, a multi-gradation display is possible.

FIG. 5 is a diagram showing an electrode applied voltage waveform in one subfield period.

In the figure, in the reset discharge period 17, 340V, 0V and 7 are applied to the X sustain electrode, the Y sustain electrode and the address electrode between time points a and b, respectively.
Apply 0V. As a result, a discharge is generated between the X sustain electrode and the Y sustain electrode on the front surface of the panel, and among the space charges generated in the discharge space 9, the positive charge is on the Y electrode side where the voltage is low, and the negative charge is the X sustain electrode where the voltage is high. Attracted to the side to form wall charges on the dielectric layer 5.

Next, at the time point b when the applied voltage disappears, a high electric field is generated between the X sustain electrode 3 and the Y sustain electrode 4 due to the wall charges on the dielectric, and this electric field causes the X sustain electrode 3 and the Y sustain electrode 3 to operate. Electric discharge is again generated between the electrodes 4. As a result, between the time points b and c, the X sustain electrode 3 and the Y sustain electrode 4 are
All the upper wall charges are neutralized to complete the reset discharge of the entire panel.

In the next address discharge period 18, for example, 70 V and -70 V are applied to the X sustain electrode 3 and the Y sustain electrode 4 at time point c-e, respectively. Then, according to the display information, for example, at the time point d, the scan pulse −140 V and the address voltage 7 are applied to the Y sustain electrode 4 and the address electrode 6, respectively.
Apply 0V. As a result, a voltage of 210 V is applied between the address electrode 6 and the Y sustain electrode 4 to cause discharge. However, since the applied voltage and the pulse width at this time are not as large as the discharge voltage and the pulse width in the reset discharge period, the opposite discharge for neutralizing the wall charges does not occur at the end of the application of the pulse voltage. Of the space charges generated by the address discharge, positive charges are attracted to the Y sustain electrodes 4 to which a negative voltage is applied, and negative charges are attracted to the X sustain electrodes 3 and address electrodes 6 to which a positive voltage is applied. Wall charges are formed on the dielectric on each electrode.

In the next sustain discharge period 19, time point c-
In f, the wall charges formed in the address discharge period 18 are used to perform discharge according to the brightness of the display. That is, a sustain voltage having a magnitude that causes discharge in a cell having wall charge between the X sustain electrode 3 and the Y sustain electrode 4 but does not discharge in a cell having no wall charge is used.
And to the Y sustain electrode 4. As a result, in the cell in which the wall charges are formed during the address discharge period, the discharge is alternately repeated between the X electrode and the Y sustain electrode. The magnitude of brightness can be changed according to the number of pulses of this discharge. Therefore, multi-gradation display is possible by repeating the weighted sub-fields in the sustain discharge period. Further, the emission color of the phosphor is set to, for example, red, green, and blue for each discharge space partitioned by the barrier ribs 8, and the discharge of these cells is combined to enable full-color display.

Next, the mechanism of abnormal discharge generation will be described.

When an image is displayed in a certain area of the plasma display panel, abnormal discharge occurs especially at the top and bottom of the image display area. Then, at each occurrence location, abnormal discharge occurs at a frequency of about once every 30 seconds.

Examining the relationship between the electric potential on the surface of the front plate and the abnormal discharge at the top and bottom of the panel, the electric potential on the surface of the front plate at the abnormal discharge occurrence point at the top of the image display unit is positive, In addition, the potential of the front plate surface at the generation point at the bottom of the image display section is negatively charged, and once abnormal discharge occurs, the positively and negatively charged potential is restored to the value at the start of image display. I found out that

Next, as to which discharge period in the sub-field consisting of the reset discharge period 17, the address discharge period 18 and the sustain discharge period 19 in which the electric charges are accumulated, the charge is accumulated. It was found that when the panel was driven with 19 removed, charge was accumulated and abnormal discharge occurred at exactly the same frequency as in the case of the sustain discharge period. In the reset discharge period 17, all the discharge cells are discharged, so that the electric charge is not accumulated. Therefore, the charge is accumulated and the potential rises during the address discharge period 1
8

Next, it was considered that the generation of the potential was due to the movement of charges, and the movement of charges in the direction along the address electrodes during the address discharge period 18 was examined. As a result, the electrons move toward the lower part of the panel during the address discharge, and the X sustain electrode 3 and the Y sustain electrode 4 in the adjacent space, that is, the discharge space, do not stay within the cell where the address discharge is performed.
It was found that the cell reached the part not facing the cell and the adjacent cell. At this time, the ions generated along with the address discharge hardly moved to the outside of the cell subjected to the address discharge.

Due to the movement of electrons as described above, the electrons move to the lower adjacent cell and form negative wall charges on the surface of the back plate dielectric 7. On the other hand, positive wall charges are formed on the surface of the upper back plate dielectric 7 where electrons are insufficient. The number of electrons that move in one address discharge is very small, but when the address discharge is repeated many times, charges are accumulated in the cells above and below the panel, and eventually the upper limit of the potential that the discharge cell can hold is reached. When reaching, the discharge cells in the vicinity are involved and a strong discharge is generated. That is, the abnormal discharge occurs.

Next, the structure of the plasma display panel and the mechanism of abnormal discharge generation were quantitatively investigated. As a result, the relationship between the capacitance ratio between the dielectric layer and the back plate dielectric layer and the occurrence of abnormal discharge was clarified.

FIG. 6 is a diagram showing the above relationship. In the figure, "capacitance of the front plate" is the capacitance of the dielectric layer 5,
The "capacitance of the back plate" means the capacitance of the back plate dielectric, and does not consider the influence of the dielectric forming the partition wall 8 on the above-mentioned capacitance. As described above, the “BP layer” is a blast protective layer provided on the surface of the address electrode in order to prevent the address electrode 6 from being scraped during the sandblasting in which the partition wall 8 is used in the forming process.

As can be seen from FIG. 6, the ratio of the capacitance of the back plate dielectric to the capacitance of the dielectric layer is about 0.85.
If it is larger, abnormal discharge does not occur. That is, when the ratio of the capacitances satisfies the above relationship, the wall charges generated on the back plate dielectric 7 generated by the address discharge remain only in the cell in which the address discharge is performed and in the adjacent space or the adjacent cell. Do not move. When the above relationship is applied to the plasma display panel of this embodiment shown in FIG. 2, the capacitance of the back plate relative to the capacitance of the dielectric layer 5 formed on the X sustain electrode 3 and the Y sustain electrode 4, that is, the address electrode. The capacitance ratio of the phosphor layer, which is the back plate dielectric, formed on 6 may be set to be larger than 0.85. According to a further investigation, the capacitance of the back plate does not have to be uniform over the front surface, and the portion facing the Y electrode, which is the scan electrode where address discharge is performed, may be set so as to satisfy the above condition. Do you get it.

The method of increasing the capacitance of a specific area of the back plate dielectric is to increase the area of the address electrode in that area, and the dielectric forming the area is a dielectric having a large relative dielectric constant. There are a method of forming the material, a method of reducing the thickness of the dielectric material forming the region, and a method of combining these. In order to reduce the capacitance of the back plate dielectric that faces a specific area, for example, the adjacent space area where the electrode pair is adjacent, a method of reducing the area of the address electrode in that area, and forming the area There are a method of forming a dielectric with a dielectric material having a small relative permittivity, a method of increasing the thickness of the dielectric forming the region, and a method of combining these. An example in which these methods are specifically applied will be described below.

FIG. 7 is a diagram showing a second embodiment of the present invention. In the figure, C1 is the X sustain electrode 3 in the discharge space.
And C2 is the capacitance of the back plate dielectric facing the Y sustain electrode 4, and C2 is the capacitance per unit length of the back plate dielectric in the portion of the discharge space not facing the X sustain electrode 3 and the Y sustain electrode 4. . In addition, in FIG.
The same parts as those shown in are attached with the same notations and an explanation thereof will be omitted.

In the present embodiment, the capacitance C1 per unit length in the address direction of the back plate dielectric opposed to the X sustain electrode and the Y sustain electrode is different from the X sustain electrode and the Y sustain electrode.
The electrostatic capacitance C2 per unit length in the address direction of the back plate dielectric which does not face the sustain electrodes is set small.

As described above, the address electrode 6 is driven in each of the reset discharge period, the address discharge period and the sustain discharge period. Therefore, it is desirable for the address electrode driving circuit that the back plate dielectric, which becomes a load when driving the address electrodes, has a small capacitance. In this embodiment, the capacitance C2, which is the capacitance not directly involved in the movement of the electrons, is set smaller than the capacitance C1 which is the capacitance directly involved in the movement of the electrons.

FIG. 8 is a diagram showing a third embodiment of the present invention. In the figure, C1 is the capacitance of the back plate dielectric facing the X sustain electrode and the Y sustain electrode in the discharge space,
C2 is the capacitance of the back plate dielectric that does not face the X sustain electrode and the Y sustain electrode in the discharge space. In the figure, the same parts as those shown in FIGS. 1 to 6 are designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, the back plate dielectric not facing the X sustain electrode and the Y sustain electrode with respect to the capacitance C1 per unit length in the address direction of the back plate dielectric facing the X sustain electrode and the Y sustain electrode. The electrostatic capacitance C2 per unit length in the address direction is set small. In this embodiment, in order to set the capacitance C2 smaller than the capacitance C1, the thickness of the back plate dielectric not facing the X sustain electrode and the Y sustain electrode in the discharge space is set large. The actions and effects of this embodiment are the same as those of the second embodiment, and therefore their explanations are omitted.

FIG. 9 is a diagram showing a fourth embodiment of the present invention. In the figure, C1 is the capacitance of the back plate dielectric facing the Y sustain electrode of the discharge space, and C2 is the Y of the discharge space.
This is the capacitance of the back plate dielectric that does not face the sustain electrodes. In the figure, the same parts as those shown in FIGS. 1 to 6 are designated by the same reference numerals and the description thereof will be omitted.

As described above, if the portion facing the Y electrode, which is the scan electrode for address discharge, is set so as to satisfy the above condition, the wall charges generated on the back plate dielectric generated by the address discharge are generated. Since only the cells that have undergone the address discharge do not move to the adjacent space or the adjacent cells, only the capacitance of the back plate dielectric facing the Y sustain electrode may be set so as to satisfy the above condition. With this setting, the address electrodes can be driven more easily.

FIG. 10 shows the fifth embodiment of the present invention, that is, the electrostatic capacitance C per unit length in the address direction of the back plate dielectric which does not face the X sustain electrode and the Y sustain electrode.
2 is a diagram showing another embodiment in which 2 is set small, and FIG.
FIG. 0 is a view showing a state where the plasma display panel is viewed from the back plate side. In the figure, 6A and 6B are address electrodes, and the address electrode 6A is an address electrode disposed between the partition walls 8 and has a relatively large area.
Is an address electrode disposed under the partition 8 and having a relatively small area. The address electrodes 6A and 6B are sequentially connected to each other, so that the electrostatic capacitance C2 per unit length in the address direction of the back plate dielectric which does not face the X sustain electrode and the Y sustain electrode can be set small. The actions and effects of this embodiment are the same as those of the second embodiment, and therefore their explanations are omitted.

[0043]

As described above, according to the present invention, the wall charges formed on the rear plate due to the address discharge are prevented from moving to the adjacent space portion or the adjacent cell, and the abnormal discharge is suppressed to obtain a clear image. It is possible to provide a plasma display panel capable of stable display with high definition and high brightness.

[Brief description of drawings]

FIG. 1 is an external perspective view of a plasma display panel according to a first embodiment of the present invention.

FIG. 2 is a right side sectional view of FIG.

FIG. 3 is a perspective view of an electrode arrangement viewed from the upper surface of FIG.

FIG. 4 is a diagram showing an example of a driving state of a three-electrode surface discharge type plasma display panel.

FIG. 5 is a diagram showing an electrode applied voltage waveform in one subfield period.

FIG. 6 is a diagram showing a relationship between a capacitance ratio of a front plate dielectric layer and a rear plate dielectric layer and abnormal discharge.

FIG. 7 is a diagram showing a second embodiment of the present invention.

FIG. 8 is a diagram showing a third embodiment of the present invention.

FIG. 9 is a diagram showing a fourth embodiment of the present invention.

FIG. 10 is a diagram showing a fifth embodiment of the present invention.

[Explanation of symbols]

1 Front glass substrate 2 Rear glass substrate 3 X sustain electrodes 4 Y sustain electrodes 5 Dielectric layer 6,6A, 6B address electrodes 7 Back plate dielectric 8 partitions 9 discharge space 10 frames 11,12,13,14,15,16 Subfield 17 Reset discharge period 18 address discharge period 19 Sustain discharge period

─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Keizo Suzuki 1-280, Higashi Koikekubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Shoji Ishigaki 4-6, Kanda Surugadai, Chiyoda-ku, Tokyo Hitachi, Ltd. Mfg. Co., Ltd. Information Media Division (72) Inventor Yoshimi Kawanami 1-280, Higashi-Kengokubo, Kokubunji, Tokyo Hitachi Co., Ltd. Central Research Laboratory (72) Inventor Hei Rin, 1-280, Higashi-Kengokubo, Kokubunji, Tokyo Hitachi, Ltd. Chuo Inside the research institute (72) Kenichi Yamamoto 1-280 Higashi Koigokubo, Kokubunji, Tokyo Hitachi Central Research Laboratory (72) Inventor Norihiro Uemura 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Central Research Laboratory (72) ) Inventor Kawafumi Tomonari Kana 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kawachi, Ltd., Production Engineering Laboratory, Hitachi, Ltd. (72) Ryohei Sato, 4-6, Kanda Surugadai, Chiyoda-ku, Tokyo Hitachi, Ltd., Information Media Division (56) References JP 2000-90835 (JP, A) JP 10-64434 (JP, A) JP 8-171857 (JP, A) JP 7-161298 (JP, A) JP 5-250993 ( JP, A) JP 5-47305 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01J 11/02 H01J 11/00

Claims (6)

(57) [Claims] 1. A first substrate, a plurality of address electrodes juxtaposed on the first substrate, and a first dielectric layer that covers the address electrodes and forms a partition between the address electrodes. And a second substrate, and a sustain electrode pair composed of a plurality of sets of X sustain electrodes and a Y sustain electrode arranged in parallel on the second substrate, and covering the plurality of sets of electrode pairs. A second panel including a second dielectric layer, the first panel and the second panel having the address electrode and the sustain electrode pair substantially orthogonal to each other, and the first panel and the second panel. In a plasma display panel arranged so as to face each other so that a discharge space is formed between the panels, a capacitance formed by the first dielectric layer in a portion facing the discharge space faces the discharge space. The second invitation to A plasma display panel having a capacitance of 0.85 or more formed by an electric layer. 2. A first substrate, a plurality of address electrodes arranged in parallel on the first substrate, and a first dielectric layer that covers the address electrodes and forms a partition between the address electrodes. And a second substrate, and a sustain electrode pair composed of a plurality of sets of X sustain electrodes and a Y sustain electrode arranged in parallel on the second substrate, and covering the plurality of sets of electrode pairs. A second panel including a second dielectric layer, the first panel and the second panel having the address electrode and the sustain electrode pair substantially orthogonal to each other, and the first panel and the second panel. In a plasma display panel arranged so as to face each other so that a discharge space is formed between the panels, a portion of the discharge space facing the X sustain electrode and Y sustain electrode pair is formed by the first dielectric layer. Stillness The plasma display panel is characterized in that a capacitance is 0.85 times or more of a capacitance formed by the second dielectric layer facing the discharge space. 3. A first substrate, a plurality of address electrodes juxtaposed on the first substrate, and a first dielectric layer that covers the address electrodes and forms a partition between the address electrodes. And a second substrate, and a sustain electrode pair composed of a plurality of sets of X sustain electrodes and Y sustain electrodes arranged side by side on the second substrate, and covering the plurality of electrode pairs. A second panel including a second dielectric layer, the address panel and the sustain electrode pair being substantially orthogonal to each other, and the first panel and the second panel. In a plasma display panel arranged so as to face each other so that a discharge space is formed between the panels, the capacitance formed by the first dielectric layer in a portion of the discharge space facing the Y sustain electrode is For discharge space The plasma display panel is 0.85 times or more of the electrostatic capacity formed by the facing second dielectric layer. 4. A first substrate, a plurality of address electrodes juxtaposed on the first substrate, and a first dielectric layer that covers the address electrodes and forms a partition between the address electrodes. And a second substrate, and a sustain electrode pair composed of a plurality of sets of X sustain electrodes and Y sustain electrodes arranged side by side on the second substrate, and covering the plurality of electrode pairs. A second panel including a second dielectric layer, the address panel and the sustain electrode pair being substantially orthogonal to each other, and the first panel and the second panel. In the plasma display panel arranged so as to face each other so that a discharge space is formed between the panels, the capacitance formed by the first dielectric layer in a portion of the discharge space not facing the Y sustain electrode is In the discharge space A plasma display panel, wherein the capacitance is less than 0.85 times the capacitance formed by the second dielectric layer facing each other. 5. A first substrate, a plurality of address electrodes arranged in parallel on the first substrate, and a first dielectric layer that covers the address electrodes and forms a partition between the address electrodes. And a second substrate, and a sustain electrode pair composed of a plurality of sets of X sustain electrodes and Y sustain electrodes arranged side by side on the second substrate, and covering the plurality of electrode pairs. And a second panel including a second dielectric layer, wherein the address panel and the sustain electrode pair are substantially orthogonal to each other, and the first panel and the second panel are the first panel and the second panel. In a plasma display panel arranged so as to face each other so that a discharge space is formed between two panels, the discharge space is formed by a portion of the first dielectric layer not facing the X sustain electrode and Y sustain electrode pair. The plasma display panel is characterized in that the capacitance is less than 0.85 times the capacitance formed by the second dielectric layer facing the discharge space. 6. The plasma display panel according to claim 1, wherein the first dielectric layer includes a blast protective layer having a film thickness of 1 μm or more.