JP2000100334A - Plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably display a clear images by restraining abnormal discharges. SOLUTION: This plasma display panel consists of a first panel comprising a first board 2, a plurality of address electrodes 6 arranged in parallel on the first board, and a first dielectric layer 5 that covers the address electrodes and defines a bulkhead between the address electrodes, and a second panel comprising a second board 1, a pair of sustain electrodes comprising plural sets of X-sustaining electrodes 3 and Y-sustaining electrodes 4 arranged in parallel on the second board, and a second dielectric layer 5 for covering the plural sets of electrode pairs, and the first and second panels are arranged facing each other, so that the address electrodes are substantially orthogonal with the sustain electrode pairs and a discharge space is formed between the first and second panels. Electrostatic capacity formed by the first dielectric layer of a part facing the discharge space is set 0.85 times larger than that formed by the second dielectric layer which faces the discharge space.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a strong discharge generated by involving a large number of discharge cells at a peripheral boundary of an image display area where an image of the plasma display panel is actually displayed. The present invention relates to a plasma display panel that stably displays a clear image by suppressing the occurrence of abnormal discharge.

[0002]

2. Description of the Related Art In a plasma display panel, charges are abnormally accumulated at a peripheral boundary of an image display area where an image of the plasma display panel is displayed, and the potential rises. The problem is the occurrence of abnormal discharge, which is a strong discharge caused by entanglement. Once the abnormal discharge has occurred, the abnormal discharge generating section may not only be unable to display an image for several seconds, but may also destroy the discharge cells. This phenomenon is an essential problem of the plasma display panel, and has become apparent as the definition and brightness of the plasma display panel have been increased.

Conventionally, as a countermeasure against the abnormal discharge, (1) As shown in Japanese Patent Application Laid-Open No. 10-64432, a dielectric material on a rear plate located at the top and bottom of a display screen of a plasma display panel is removed. A method of exposing an address electrode to discharge and remove accumulated charges by utilizing electric conduction of the address electrode;
Japanese Patent Application Laid-Open No. Hei 10-69858 discloses a method in which a constant lighting region is provided at the outermost peripheral portion of a plasma display panel, and accumulated electric charges are discharged and removed by using electric conduction in the constant lighting region. JP-A-64434 discloses a method in which conductive particles are mixed into a dielectric constituting a back plate for holding an address electrode, and accumulated electric charges are discharged and removed using electric conduction of the dielectric. It had been.

[0004]

SUMMARY OF THE INVENTION Conventional (1) and (2)
The method described above is effective only when the entire panel is used as a display area. When only a part of the panel is used as a display area, the occurrence of abnormal discharge cannot be prevented. The method (3) is an effective method when any area of the panel is used as a display area. However, the dielectric forming the back plate is formed by firing, and it is difficult to fire the dielectric containing conductive particles without losing the conductivity of the conductive particles.

The present invention has been made in view of the above-mentioned various problems, and does not utilize the electric conduction as shown in the above-mentioned conventional example, but effectively utilizes the movement of wall charges formed on the back plate. An object of the present invention is to provide a high-definition and high-brightness plasma display panel capable of preventing charge accumulation, suppressing abnormal discharge, and stably displaying a clear image.

[0006]

The present invention employs the following means in order to solve the above-mentioned problems.

A first substrate, a plurality of address electrodes juxtaposed on the first substrate, and a first dielectric layer covering the address electrodes and forming a partition wall between the address electrodes. A first panel, a second substrate, a pair of sustain electrodes including a plurality of sets of X sustain electrodes and Y sustain electrodes arranged in parallel on the second substrate, and a second pair of electrodes covering the plurality of pairs of electrodes. A second panel made of a dielectric layer of the above, wherein the first panel and the second panel are formed such that the address electrodes and the sustain electrode pairs are substantially orthogonal to each other, and
In a plasma display panel which is disposed so as to form a discharge space between a first panel and a second panel, a static electricity formed by a portion of the first dielectric layer which faces the discharge space. The capacitance is 0.1% of the capacitance formed by the second dielectric layer facing the discharge space.
It is 85 times or more.

A first substrate, a plurality of address electrodes juxtaposed on the first substrate, and a first dielectric layer covering the address electrodes and forming a partition wall between the address electrodes; , A second substrate, a plurality of pairs of X-sustain electrodes and a plurality of Y-sustain electrodes arranged side by side on the second substrate, and the plurality of pairs of electrodes are covered. A second dielectric layer
The first panel and the second panel, the address electrode and the sustain electrode pair are substantially orthogonal,
Further, in the plasma display panel which is disposed so as to form a discharge space between the first panel and the second panel, a portion of the discharge space which faces a pair of an X sustain electrode and a Y sustain electrode is formed by the first and second panels. The capacitance formed by the first dielectric layer is 0.8% of the capacitance formed by the second dielectric layer facing the discharge space.
A plasma display panel characterized by being at least 5 times.

A first substrate, a plurality of address electrodes arranged in parallel on the first substrate, and a first dielectric layer covering the address electrodes and forming a partition wall between the address electrodes; And a second substrate, a plurality of sets of X sustain electrodes and a plurality of Y sustain electrodes arranged side by side on the second substrate, and the plurality of pairs of electrodes are covered. A second panel made of a second dielectric layer, wherein the address electrode and the sustain electrode pair are substantially orthogonal to each other,
In the plasma display panel, which is disposed so as to form a discharge space between the first panel and the second panel, a portion of the discharge space facing the Y-sustain electrode in the first dielectric layer Wherein the capacitance formed by the second dielectric layer is 0.85 times or more the capacitance formed by the second dielectric layer facing the discharge space.

A first substrate, a plurality of address electrodes juxtaposed on the first substrate, and a first dielectric layer covering the address electrodes and forming a partition wall between the address electrodes; And a second substrate, a plurality of sets of X sustain electrodes and a plurality of Y sustain electrodes arranged side by side on the second substrate, and the plurality of pairs of electrodes are covered. A second panel made of a second dielectric layer, wherein the address electrode and the sustain electrode pair are substantially orthogonal to each other,
Further, in the plasma display panel which is disposed so as to form a discharge space between the first panel and the second panel, a portion of the discharge space which is not opposed to the Y sustain electrode is provided with the first dielectric layer. A capacitance formed by the second dielectric layer facing the discharge space is less than 0.85 times the capacitance formed by the second dielectric layer.

A first substrate, a plurality of address electrodes juxtaposed on the first substrate, and a first dielectric layer covering the address electrodes and forming a partition wall between the address electrodes; And a second substrate, a plurality of sets of X sustain electrodes and a plurality of Y sustain electrodes arranged side by side on the second substrate, and the plurality of pairs of electrodes are covered. And a second panel made of a second dielectric layer. The first panel and the second panel are formed such that the address electrode and the sustain electrode pair are substantially orthogonal to each other, and the first panel and the second panel are connected to each other. In a plasma display panel arranged so as to form a discharge space between two panels, a portion of the discharge space that does not face the X sustain electrode and Y sustain electrode pair is formed by the first dielectric layer. A plasma display panel, wherein the electrostatic capacitance is less than 0.85 times the capacitance formed by the second dielectric layer facing the discharge space.

Further, in the plasma display panel, the first dielectric layer includes a blast protection layer having a thickness of 1 μm or more.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is an external perspective view of the plasma display panel according to the present embodiment, FIG. 2 is a right sectional view of FIG. 1, and FIG. 3 is a perspective view of the electrode arrangement as viewed from the top of FIG.

The structure of the plasma display panel will be described below with reference to these drawings.

In these figures, reference numeral 1 denotes a front glass substrate, which is disposed on the side of the plasma display panel from which display light is emitted. Reference numeral 2 denotes a rear glass substrate, 3 denotes an X sustain electrode formed of a transparent conductive film, and 3a denotes a bus electrode attached to one end of the X sustain electrode. The bus electrode is driven by reducing the resistance of the transparent conductive film. make it easier.
4 is a Y sustain electrode formed of a transparent conductive film, and 4a is a Y sustain electrode.
A bus electrode attached to one end of the sustain electrode,
The resistance of the transparent conductive film is reduced to facilitate voltage driving of the sustain electrode. 5 is a dielectric layer covering the X sustain electrode, the Y sustain electrode and the bus electrodes 3a, 4a,
The dielectric layer 5 is composed of a plurality of dielectric layers. Reference numeral 6 denotes an address electrode formed on the rear glass substrate 2, and reference numeral 7 denotes a rear plate dielectric formed on the address electrode 6, which is composed of a phosphor layer. Reference numeral 8 denotes a partition formed to partition between the address electrodes 6, and 9 denotes a discharge space.

Although not shown, a sandblast protective layer made of an insulator is formed on the address electrode 6 to a thickness of 1 μm or more. The partition walls 8 are formed by grinding and removing the discharge space 9 by sandblasting an insulating plate formed in a flat plate shape in advance. The sandblast protection layer is formed to prevent the address electrodes 6 from being scraped during the sandblasting.

The front glass substrate and the rear glass substrate thus formed are combined so that the sustain electrodes 3, 4 and the address electrode 6 are substantially orthogonal to each other and a discharge space 9 is formed. The discharge space 9 is about 100 μm, and the discharge space 9 is filled with a mixed gas mainly composed of a rare gas such as Ne and Xe. Thus, the X sustain electrode 3, Y
A discharge cell is constituted by the sustain electrode 4 and the address electrode 6 facing these electrodes. As shown in FIG. 3, the X sustain electrode 3 and the Y sustain electrode 4 extend from one end (hereinafter, referred to as an upper portion) to the other end (hereinafter, referred to as a lower portion) of the front glass substrate 1 constituting the plasma display panel. The Y-sustain electrodes 4, the X-sustain electrodes 3, the Y-sustain electrodes 4, the X-sustain electrodes 3,... Are arranged in this order to form a so-called three-electrode surface discharge type plasma display panel.

FIG. 4 is a diagram showing an example of a driving state of the three-electrode surface discharge type plasma display panel. In the figure, 10 represents one frame. One frame 10
Has a duration of 16.7 ms. 11 to 16 are subfields, and one frame 10 is divided into, for example, six subfields 11 to 16. Reference numerals 17, 18, and 19 denote a reset discharge period, an address discharge period, and a sustain discharge period, respectively, which will be described later.
Each of the subfields 11 to 16 has a reset discharge period 1
7, an address discharge period 18, and a sustain discharge period 19. The sustain discharge period in each of the subfields 11 to 16 is a weighted period,
For example, if the sustain discharge period of the subfield 11 is 1, the sustain discharge period of the subfield 12 is 2,
The sustain discharge period of the subfield 13 is 4; the sustain discharge period of the subfield 14 is 8; the sustain discharge period of the subfield 15 is 16;
The sustain discharge period of 6 is set to have a weight of 32. By repeatedly displaying the subfields 11 to 16 set as described above, multi-gradation display can be performed.

FIG. 5 is a diagram showing a voltage waveform applied to the electrodes during one subfield period.

In the figure, during the reset discharge period 17, the X sustain electrode, the Y sustain electrode, and the address electrode are respectively set to 340 V, 0 V, and 7 between the points a and b.
0 V is applied. As a result, a discharge is generated between the X sustain electrode and the Y sustain electrode on the front surface of the panel, and among the space charges generated in the discharge space 9, the positive charge is on the Y electrode side where the voltage is low, and the negative charge is the X sustain electrode where the voltage is high. Side to form a wall charge on the dielectric layer 5.

Next, at a time point b when the applied voltage stops, a high electric field is generated between the X sustain electrode 3 and the Y sustain electrode 4 due to the wall charges on the dielectric, and the electric field causes the X sustain electrode 3 and the Y sustain electrode 3 to generate a high electric field. Discharge occurs again between the electrodes 4. As a result, the X sustain electrode 3 and the Y sustain electrode 4
All of the upper wall charges are neutralized, and the reset discharge of the entire panel is completed.

In the next address discharge period 18, for example, 70V and -70V are applied to the X sustain electrode 3 and the Y sustain electrode 4 at time c-e. Then, according to the display information, for example, at time point d, scan pulse -140 V and address voltage 7 are applied to Y sustain electrode 4 and address electrode 6, respectively.
0 V is applied. As a result, a voltage of 210 V is applied between the address electrode 6 and the Y sustain electrode 4 to generate a discharge. However, since the applied voltage and the pulse width at this time are not so large as the discharge voltage and the pulse width during the reset discharge period, the opposite discharge for neutralizing the wall charge does not occur at the end of the application of the pulse voltage. Of the space charges generated by the address discharge, a positive charge is attracted to the Y sustain electrode 4 to which a negative voltage is applied, and a negative charge is attracted to the X sustain electrode 3 and the address electrode 6 to which a positive voltage is applied. A wall charge is formed on the dielectric on each electrode.

In the next sustain discharge period 19, the time point c-
At f, discharge is performed in accordance with the display luminance by using the wall charges formed during the address discharge period 18. That is, a sustain voltage having such a magnitude that discharge occurs in a cell having wall charges between the X sustain electrode 3 and the Y sustain electrode 4 but does not discharge in a cell having no wall charge.
And Y sustain electrode 4. As a result, in the cell in which the wall charges are formed during the address discharge period, the discharge is alternately repeated between the X electrode and the Y sustain electrode. The magnitude of the luminance can be changed according to the number of pulses of this discharge. Therefore, by repeating the weighted subfield in the sustain discharge period, multi-gradation display can be performed. Further, a full-color display is possible by setting the emission color of the phosphor to red, green, and blue, for example, for each discharge space defined by the partition walls 8 and combining the discharges of these cells.

Next, the mechanism of occurrence of abnormal discharge will be described.

When an image is displayed in a certain area of the plasma display panel, abnormal discharge is generated particularly at the top and bottom of the image display area. Then, abnormal discharge occurs at a frequency of about 30 seconds at each occurrence location.

Examining the relationship between the potential on the front plate surface and the abnormal discharge at the top and bottom of the panel, the potential of the front plate surface at the abnormal discharge occurrence position at the top of the image display section was positive. In addition, the potential of the front plate surface at the generation point at the bottom of the image display portion is negatively charged, and once an abnormal discharge occurs, the positively and negatively charged potentials are restored to the values at the start of image display. I found out.

Next, it is examined in which discharge period in the subfield of the reset discharge period 17, the address discharge period 18, and the sustain discharge period 19 the charge is accumulated. It was also found that when the panel was driven after removing the pixel 19, as in the case where the sustain discharge period was present, charge accumulation occurred, and abnormal discharge occurred at exactly the same frequency. In the reset discharge period 17, all the discharge cells are discharged, so that the charge is not accumulated. Therefore, the charge is accumulated and the potential rises during the address discharge period 1.
8

Next, the generation of the potential was considered to be caused by the movement of charges, and the movement of charges in the direction along the address electrodes during the address discharge period 18 was examined. As a result, at the time of the address discharge, electrons move toward the lower part of the panel and do not remain only in the cell where the address discharge was performed.
It has been found that it reaches the part that does not face and the adjacent cell. At this time, ions generated by the address discharge hardly moved out of the cell where the address discharge was performed.

Due to the movement of the electrons as described above, the electrons move to the lower adjacent cell, and a negative wall charge is formed on the surface of the back plate dielectric 7. On the other hand, positive wall charges are formed on the surface of the upper back plate dielectric 7 where electrons are insufficient. The number of electrons that move in one address discharge is very small, but when address discharge is repeated many times, electric charges are accumulated in the cells above and below the panel, and eventually the upper limit of the potential that the discharge cells can hold , A strong discharge is generated by involving nearby discharge cells. That is, the abnormal discharge occurs.

Next, the structure of the plasma display panel and the mechanism of occurrence of abnormal discharge were quantitatively examined. As a result, the relationship between the ratio between the capacitance of the dielectric layer and the capacitance of the back plate dielectric layer and the occurrence of abnormal discharge became clear.

FIG. 6 is a diagram showing the relationship. In the figure, the “capacitance of the front plate” is the capacitance of the dielectric layer 5,
The “capacitance of the back plate” means the capacitance of the back plate dielectric, and does not consider the influence of the dielectric forming the partition 8 on the capacitance. Further, as described above, the “BP layer” is a blast protection layer provided on the surface of the address electrode in order to prevent the address electrode 6 from being scraped during sandblasting used in the formation process of the barrier ribs 8.

As can be seen from FIG. 6, the ratio of the capacitance of the back plate dielectric to the capacitance of the dielectric layer is approximately 0.85.
If it is larger, no abnormal discharge occurs. That is, when the above-mentioned capacitance ratio satisfies the above-described relationship, the wall charges generated on the back plate dielectric 7 generated by the address discharge remain only in the cell where the address discharge has been performed, and remain in the adjacent space or adjacent cell. Do not move. When the above-described relationship is applied to the plasma display panel of this embodiment shown in FIG. 2, the capacitance of the back plate with respect to the capacitance of the dielectric layer 5 formed on the X sustain electrode 3 and the Y sustain electrode 4, that is, the address electrode. The ratio of the capacitance of the phosphor layer serving as the back plate dielectric formed on the substrate 6 may be set to be larger than 0.85. According to a further investigation, the capacitance of the back plate does not need to be uniform over the front surface, and a portion facing the Y electrode, which is a scan electrode where an address discharge is performed, may be set so as to satisfy the above condition. Do you get it.

The method for increasing the capacitance of a specific region of the back plate dielectric includes a method of increasing the area of the address electrode in that region and a method of forming a dielectric forming the region with a dielectric having a large relative dielectric constant. There are a method of forming with a material, a method of reducing the thickness of a dielectric forming the region, and a method of combining these. A method for reducing the capacitance of the back plate dielectric facing a specific region, for example, the adjacent space region where the electrode pair is adjacent, includes a method of reducing the area of the address electrode in that region, and forming the region. There are a method of forming the dielectric with a dielectric material having a small relative permittivity, a method of increasing the thickness of the dielectric forming the region, and a method of combining these. Hereinafter, examples in which these methods are specifically applied will be described.

FIG. 7 is a diagram showing a second embodiment of the present invention. In the figure, C1 is the X sustain electrode 3 in the discharge space.
And the capacitance of the back plate dielectric facing the Y sustain electrode 4, and C2 is the capacitance per unit length of the back plate dielectric in the portion of the discharge space not facing the X sustain electrode 3 and the Y sustain electrode 4. . 1 to 6 in the drawings.
The same reference numerals are given to the same parts as those shown in FIG.

In this embodiment, the X-sustain electrode and the Y-sustain electrode have a capacitance C1 per unit length in the address direction of the back plate dielectric facing the X-sustain electrode and the Y-sustain electrode.
The capacitance C2 per unit length in the address direction of the back plate dielectric that is not opposed to the sustain electrode is set small.

As described above, the address electrodes 6 are driven during the reset discharge period, the address discharge period, and the sustain discharge period, respectively. Therefore, it is desirable for the drive circuit of the address electrode that the back plate dielectric, which is a load when driving the address electrode, has a small capacitance. In the present embodiment, the capacitance C2 which is not directly involved in the movement of electrons is set smaller than the capacitance C1 which is directly concerned with the movement of electrons.

FIG. 8 is a diagram showing a third embodiment of the present invention. In the figure, C1 is the capacitance of the back plate dielectric facing the X sustain electrode and the Y sustain electrode in the discharge space,
C2 is the capacitance of the back plate dielectric that does not face the X sustain electrode and the Y sustain electrode in the discharge space. In the drawings, the same portions as those shown in FIGS. 1 to 6 are denoted by the same reference numerals, and description thereof will be omitted.

In this embodiment, the capacitance C1 per unit length in the address direction of the back plate dielectric facing the X sustain electrode and the Y sustain electrode is different from that of the back plate dielectric not facing the X sustain electrode and the Y sustain electrode. The capacitance C2 per unit length in the address direction is set small. In the present embodiment, in order to set the capacitance C2 smaller than the capacitance C1, the thickness of the back plate dielectric that is not opposed to the X sustain electrode and the Y sustain electrode in the discharge space is set to be large. The operation and effect of the present embodiment are the same as those of the second embodiment, and thus description thereof is omitted.

FIG. 9 is a view showing a fourth embodiment of the present invention. In the figure, C1 is the capacitance of the back plate dielectric facing the Y sustain electrode in the discharge space, and C2 is the Y capacitance in the discharge space.
This is the capacitance of the back plate dielectric that does not face the sustain electrode. In the drawings, the same portions as those shown in FIGS. 1 to 6 are denoted by the same reference numerals, and description thereof will be omitted.

As described above, if the portion facing the Y electrode, which is the scan electrode on which the address discharge is performed, is set so as to satisfy the above conditions, the wall charge generated on the back plate dielectric caused by the address discharge is reduced. Since only the cell that has performed the address discharge does not move to the adjacent space or the adjacent cell, only the capacitance of the back plate dielectric facing the Y sustain electrode may be set so as to satisfy the above-described condition. With this setting, the address electrodes can be driven more easily.

FIG. 10 shows a fifth embodiment of the present invention, that is, the capacitance C per unit length in the address direction of the back plate dielectric that is not opposed to the X sustain electrode and the Y sustain electrode.
FIG. 1 is a diagram showing another embodiment in which 2 is set to be small, and FIG.
FIG. 0 is a diagram showing the appearance of the plasma display panel viewed from the back plate side. In the drawing, reference numerals 6A and 6B denote address electrodes, and the address electrodes 6A are disposed between the partition walls 8 and have a relatively large area.
Is an address electrode having a relatively small area disposed below the partition 8. The address electrodes 6A and 6B are sequentially connected so that the capacitance C2 per unit length in the address direction of the back plate dielectric that does not face the X sustain electrode and the Y sustain electrode can be set small. The operation and effect of the present embodiment are the same as those of the second embodiment, and thus description thereof is omitted.

[0043]

As described above, according to the present invention, the abnormal discharge is suppressed by preventing the wall charges formed on the back plate from being moved to the adjacent space portion or the adjacent cell by the address discharge, so that the clear image can be obtained. Can be provided stably and a plasma display panel capable of displaying high definition and high brightness can be provided.

[Brief description of the drawings]

FIG. 1 is an external perspective view of a plasma display panel according to a first embodiment of the present invention.

FIG. 2 is a right side sectional view of FIG.

FIG. 3 is a perspective view of an electrode arrangement as viewed from above in FIG. 1;

FIG. 4 is a diagram showing an example of a driving state of a three-electrode surface discharge type plasma display panel.

FIG. 5 is a diagram showing an electrode applied voltage waveform during one subfield period.

FIG. 6 is a diagram showing the relationship between the ratio of capacitance between the front plate dielectric layer and the back plate dielectric layer and abnormal discharge.

FIG. 7 is a diagram showing a second embodiment of the present invention.

FIG. 8 is a diagram showing a third embodiment of the present invention.

FIG. 9 is a diagram showing a fourth embodiment of the present invention.

FIG. 10 is a diagram showing a fifth embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Front glass substrate 2 Back glass substrate 3 X sustain electrode 4 Y sustain electrode 5 Dielectric layer 6, 6A, 6B Address electrode 7 Back plate dielectric 8 Partition wall 9 Discharge space 10 Frame 11, 12, 13, 14, 15, 16 Subfield 17 Reset discharge period 18 Address discharge period 19 Sustain discharge period

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Eiji Fukumoto 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Keizo Suzuki 1-280, Higashi Koigakubo, Kokubunji-shi, Tokyo (72) Inventor Shoji Ishigaki 4-6-6 Kanda Surugadai, Chiyoda-ku, Tokyo Inventor Information Media Division, Hitachi, Ltd. (72) Yoshimi Kawanami 1-280, Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (72) Inventor Kunin, 1-280 Higashi Koigakubo, Kokubunji, Tokyo, Japan Inside the Hitachi, Ltd. Central Research Laboratory (72) Kenichi Yamamoto 1-280, Higashi Koikebo, Kokubunji, Tokyo, Hitachi, Ltd. Inside the research institute (72) Inventor Norihiro Uemura Tokyo 1-280 Higashi-Koigakubo, Hitachi, Ltd.In the Central Research Laboratory, Hitachi, Ltd. (72) Inventor: Tomonori Kawai 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture In-house Research Laboratory, Hitachi, Ltd. (72) Ryohei Sato, Inventor 4-6, Kanda Surugadai, Chiyoda-ku, Tokyo F-term in the Information Media Division of Hitachi, Ltd. (Reference) 5C040 FA01 FA04 GB03 GB14 GD01 GD03 GD07 GD09 GD10 GE01 GF02 GF08 JA17 KB19 KB29 LA11 MA03 MA17 MA20

Claims (6)

[Claims] A first substrate, a plurality of address electrodes juxtaposed on the first substrate, and a first dielectric layer covering the address electrodes and forming a partition wall between the address electrodes. And a second substrate, a plurality of pairs of X sustain electrodes and a plurality of Y sustain electrodes arranged side by side on the second substrate, and the plurality of electrode pairs. A second panel made of a second dielectric layer, wherein the first panel and the second panel are formed such that the address electrode and the sustain electrode pair are substantially orthogonal to each other, and the first panel and the second panel are connected to each other. Wherein the capacitance formed by the first dielectric layer in a portion facing the discharge space is opposed to the discharge space. The second invitation to A plasma display panel characterized in that the capacitance is 0.85 times or more of the capacitance formed by the conductor layer. 2. A first substrate, a plurality of address electrodes juxtaposed on the first substrate, and a first dielectric layer covering the address electrodes and forming a partition wall between the address electrodes. And a second substrate, a plurality of pairs of X sustain electrodes and a plurality of Y sustain electrodes arranged side by side on the second substrate, and the plurality of electrode pairs. A second panel made of a second dielectric layer, wherein the first panel and the second panel are formed such that the address electrode and the sustain electrode pair are substantially orthogonal to each other, and the first panel and the second panel are connected to each other. In a plasma display panel which is disposed so as to form a discharge space between the panels, a portion of the discharge space which is opposed to the X sustain electrode and the Y sustain electrode pair is formed by the first dielectric layer. Stillness A plasma display panel, wherein a capacitance is 0.85 times or more a capacitance formed by the second dielectric layer facing the discharge space. 3. A first substrate, a plurality of address electrodes juxtaposed on the first substrate, and a first dielectric layer covering the address electrodes and forming a partition wall between the address electrodes. A plurality of pairs of X sustain electrodes and Y sustain electrodes arranged side by side on the second substrate, and a plurality of pairs of electrode pairs covering the plurality of pairs of electrode pairs. A second dielectric layer comprising: a first dielectric layer and a second dielectric layer, wherein the first panel and the second panel are arranged such that the address electrodes and the sustain electrode pairs are substantially orthogonal to each other; In the plasma display panel, which is disposed so as to form a discharge space between the panels, a capacitance formed by the first dielectric layer in a portion of the discharge space facing the Y sustain electrode is For discharge space A capacitance of 0.85 times or more the capacitance formed by the second dielectric layer facing the plasma display panel. 4. A first substrate, a plurality of address electrodes juxtaposed on the first substrate, and a first dielectric layer covering the address electrodes and forming a partition wall between the address electrodes. A plurality of pairs of X sustain electrodes and Y sustain electrodes arranged side by side on the second substrate, and a plurality of pairs of electrode pairs. A second dielectric layer comprising: a first dielectric layer and a second dielectric layer, wherein the first panel and the second panel are arranged such that the address electrodes and the sustain electrode pairs are substantially orthogonal to each other; In a plasma display panel, which is disposed so as to form a discharge space between the panels, a capacitance formed by the first dielectric layer in a portion of the discharge space that does not face the Y sustain electrode is In the discharge space A plasma display panel, wherein the capacitance is less than 0.85 times the capacitance formed by the opposing second dielectric layer. 5. A first substrate, a plurality of address electrodes juxtaposed on the first substrate, and a first dielectric layer covering the address electrodes and forming a partition wall between the address electrodes. A plurality of pairs of X sustain electrodes and Y sustain electrodes arranged side by side on the second substrate, and a plurality of pairs of electrode pairs covering the plurality of pairs of electrode pairs. A second panel made up of a second dielectric layer, and the first panel and the second panel are formed such that the address electrodes and the sustain electrode pairs are substantially orthogonal to each other, and the first panel and the second panel are connected to each other. A plasma display panel arranged so as to form a discharge space between two panels, wherein a portion of the discharge space that does not face a pair of an X sustain electrode and a Y sustain electrode is formed by the first dielectric layer. A plasma display panel having a capacitance less than 0.85 times a capacitance formed by the second dielectric layer facing the discharge space. 6. The plasma display panel according to claim 1, wherein the first dielectric layer includes a blast protection layer having a thickness of 1 μm or more.