JP2000030615A - Plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a plasma display panel with high precision and high luminance capable of stably displaying a clear picture. SOLUTION: This plasma display panel has a first substrate on the surface of which an address electrode 6, a first dielectric layer 7 to cover the address electrode 6 and a phosphor layer 21 to cover the first dielectric layer 7, and a second substrate on the surface of which plural pairs of electrodes having an X sustain electrode 3 crossing the address electrode 3 and a Y sustain electrode 4 (scan electrode) as one pair, and a second dielectric layer 5 to cover the sustain electrodes are formed and the first substrate and the second substrate are placed face to face through a discharge space 9 in it. The thickness of the first dielectric layer 7 covering the surface of the address electrode 6 is not more than 5 μm (micron).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a strong discharge that occurs accidentally by involving a large number of discharge cells at a peripheral boundary of a display area, which is a part of the panel where an image is displayed. That is, the present invention relates to a plasma display panel that stably displays a clear image by suppressing occurrence of abnormal discharge.

[0002]

2. Description of the Related Art As a conventional measure against abnormal discharge, Japanese Patent Application No.
No. 219521 (removing the dielectric material on the top and bottom back panels of the panel and exposing the address electrodes to remove accumulated charges), and Japanese Patent Application No. 8-226274 (providing a constant lighting area at the outermost periphery of the panel) There are techniques such as removing charges accumulated by electric conduction in that region) and Japanese Patent Application No. 10-64434 (removing charges accumulated by mixing conductive particles into the dielectric of the back plate). The first two prior arts are effective only when the display area covers the entire panel, and abnormal discharge occurs when the display area is a part of the panel. The third prior art is effective for any display area. However, know-how is required so that the particles do not lose conductivity in the firing process. In addition, the above three prior arts have a common feature in that abnormal discharge is suppressed by utilizing electric conduction of a specific portion constituting a panel.

[0003]

In a plasma display panel, there is a problem that a strong discharge that occurs accidentally by involving a large number of discharge cells in a peripheral portion of a display area, that is, an abnormal discharge. When the main discharge is generated, not only is it impossible to display an image for several seconds at the generation unit, but also the discharge cell may be broken. This phenomenon is an essential problem of the plasma display panel, and has become apparent as the definition and brightness have been increased.

An object of the present invention is to provide a high-definition and high-brightness PDP for stably displaying a clear image.

[0005]

In order to achieve the above object, the thickness of the dielectric layer and the electrical characteristics are set to appropriate ranges. The appropriate difficulty is a range in which the potential difference due to the charge separation in the address electrode direction in the display area does not exceed the upper limit that the discharge cell can hold. Thereby, it is possible to prevent the polarization of the wall charges in the direction along the address electrode, thereby preventing abnormal discharge.

As means for this purpose, a first substrate on which a plurality of address electrodes and a first dielectric layer covering the address electrodes are formed, and an X-sustainer which intersects the address electrodes on the surface. , Y sustain electrodes, and a second substrate on which a second dielectric layer covering the scan electrodes is formed, wherein the first and second substrates are discharged. In the PDPs opposed to each other via a space, the thickness and electric characteristics of the dielectric layer are set to appropriate ranges, and the potential difference due to the charge separation in the address electrode direction in the display area exceeds the upper limit value that the discharge cells can hold. It is not to be.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Description of PDP) An embodiment of the present invention will be described with reference to the drawings. FIG. 2 shows the structure of the AC PDP according to the embodiment of the present invention. FIG. 3 is a sectional view of the PDP as viewed from the right side in FIG. FIG. 4 is a perspective view of the electrode arrangement as viewed from the side where the display light of the PDP emerges. The structure will be described with reference to these drawings. Reference numeral 1 denotes a front glass substrate on the side from which display light is emitted. 2 is a back glass substrate. A plurality of X sustain electrodes 3 and Y sustain electrodes 4 each composed of a transparent electrode and a bus electrode are formed on the front glass substrate. In this figure, the bus electrode is arranged at a position close to the adjacent space on the transparent electrode, but the bus electrode may be located anywhere on the transparent electrode. Hereinafter, these are simply referred to as X electrodes, Y electrodes, or collectively as sustain electrodes.
The sustain electrode is covered with a dielectric layer 5 made of several materials. A plurality of bases and address electrodes 6 are provided on the back glass substrate 2, and are covered with a dielectric 7 and a phosphor layer 21. Each address electrode 6 is partitioned by a partition wall 8. As shown in FIG. 3, the front glass substrate and the rear glass substrate are combined so as to maintain a gap of about 100 μm, and a discharge gas 9 therebetween is filled with a mixed gas mainly composed of a rare gas such as Ne or Xe. Is done. As shown in the electrode arrangement perspective view of FIG. 4, the electrodes are arranged in the order of the Y electrode and the X electrode from the upper panel to the lower panel.
In describing the embodiments of the present invention, the upper and lower portions of the panel are defined as described above for convenience. A PDP having a structure equivalent to the above structure is referred to as a three-electrode surface discharge type PDP.

In driving a three-electrode surface discharge type PDP, as shown in FIG. 5, one frame 10 of 16.7 ms is divided into a plurality of subfields. FIG. 5 shows an example of division into six subfields 11, 12, 13, 14, 15, and 16. Each subfield includes a reset discharge period 17, an address discharge period 18, and a sustain discharge period 19. FIG. 6 is an example of an electrode applied voltage waveform in one subfield. The value of the applied voltage shown in this figure is a rough guide, and the optimum value of the applied voltage differs depending on conditions such as the panel structure, gas composition and pressure.

In the reset discharge period, for example, at time ab in FIG.
V, 0 V and 70 V are applied. As a result, a discharge is generated between the X and Y electrodes on the front surface of the panel, and of the space charges generated in the discharge space 9, positive charges are drawn to the Y electrode side with a low voltage and negative charges are drawn to the X electrode side with a high voltage. A wall charge is formed on the dielectric 5. Next, at time b when the applied voltage stops,
Discharge occurs again due to the electric field between X and Y due to the wall charges on the dielectric. As a result, at time bc, all X,
The wall charges on the Y electrodes are neutralized, and the reset discharge of the entire panel is completed. In the address discharge period, the time c-
At e, for example, 70 V, -7
0 V is applied. According to the display information in order from the upper part of the panel to the lower part, at time d in FIG.
An address voltage of 70 V is applied. As a result, a voltage of 210 V is applied between the address electrode and the Y electrode, and a discharge occurs. However, since the magnitude of the applied voltage and the pulse width at this time are not so large as in the case of the reset discharge, the opposite discharge for eliminating the wall charge at the end of the pulse does not occur. Of the space charges generated by this discharge, negative charges are drawn to the X electrode and address electrode to which a positive voltage is applied, and positive charges are drawn to the Y electrode to which a negative voltage is applied, to form wall charges on the dielectric.

Finally, in the sustain discharge period, at time cf in FIG. 6, a discharge is performed in accordance with the display luminance by using the wall charges formed in the address discharge period. That is,
Appropriate sustain voltage is applied so that cells having wall charges between the X and Y electrodes will discharge, but cells without wall charges will not discharge. As a result, in the cell in which the wall charges are formed during the address discharge period, the discharge is alternately repeated between the X and Y electrodes. Display gradation can be realized according to the number of pulses of this discharge. Therefore, multi-gradation display is enabled by repeating the weighted sub-field a plurality of times in the sustain discharge period. A full-color display can be realized by combining discharges of cells coated with red, green, and blue phosphors.

(Generation Mechanism of Abnormal Discharge) It is known that in the PDP having the above-mentioned conventional structure, a strong discharge that occurs accidentally by involving a large number of discharge cells in the periphery of the display area, that is, an abnormal discharge is generated. As the definition and brightness of PDPs increase, the problem of image quality deterioration due to abnormal discharge has become apparent. When an abnormal discharge occurs, not only the image cannot be displayed for several seconds in the generating section, but also the discharge cells may be destroyed. First, the mechanism of occurrence of abnormal discharge in a conventional PDP will be described.

When an image is displayed in a certain area in the PDP having the conventional structure, an abnormal discharge is generated particularly at the uppermost portion and the lowermost portion of the image display portion. Causes abnormal discharge. Generally, it was considered that the occurrence of electric discharge was accompanied by some change in electric potential, and the relationship between the electric potential on the front plate surface at the uppermost part and the lowermost part of the panel and the occurrence of abnormal electric discharge was examined. As a result, the potential at the top of the image display unit where the abnormal discharge occurs is positive, and the potential at the bottom of the image display unit is negative.The potential starts to be displayed once the abnormal discharge occurs. It turned out to return to the hour value. Further, it was examined in which discharge period in the subfield consisting of the reset, address, and sustain discharge periods the potential difference occurred. As a result, it was found that, even when the sustain discharge period was removed from the subfield and the panel was driven, the above-mentioned potential difference was generated and abnormal discharge occurred at exactly the same frequency as in the case where the sustain discharge period was present. On the other hand, in the reset discharge period, all the discharge cells discharge similarly, so that the above potential difference cannot occur. Therefore, the potential difference occurs during the address discharge period.

Next, on the assumption that the generation of the potential difference is related to the movement of charges, the movement of charges in the direction along the address electrodes during the address discharge period was examined. As a result, it was found that electrons move downward in the panel at the time of the address discharge, and reach not only the cell where the address discharge was performed but also the adjacent space or the adjacent cell. At this time, the ions hardly went out of the cell where the address discharge was performed.
The electrons reach the adjacent cells by the above-described charge transfer, and form negative wall charges on the dielectric and phosphor surfaces of the back plate. Although the number of electrons that move in one address discharge is extremely small, the number of address discharges is repeated many times, and eventually reaches the upper limit of the potential that the discharge cell can hold. And
Eventually, a strong discharge involving the discharge cells in the vicinity is a mechanism of the abnormal discharge.

(PDP that can suppress abnormal discharge) As a result of quantitatively examining the relationship between the PDP structure and the above-mentioned potential change causing abnormal discharge, the conditions of the PDP structure for preventing the above-mentioned potential change from being clarified. Was. A PDP capable of suppressing the occurrence of abnormal discharge has been devised based on the conditions of the PDP structure for preventing the above potential change and the mechanism of generating abnormal discharge.

First, a PDP capable of suppressing the occurrence of abnormal discharge
The first structure will be described. FIG. 1 shows a cross-sectional view of the PDP along the address electrode direction. The present invention is characterized in that the thickness of the first dielectric layer covering the surface of the address electrode is 5 μm (micron) or less. FIG.
FIG. 4 shows the relationship between the thickness of the first dielectric layer covering the surface of the address electrode and the occurrence of abnormal discharge. In the figure, condition 1 is a display area having a diagonal length of 25 ″, XGA resolution, and a thickness of a second dielectric layer covering the sustain electrode of 20 μm.
(Micron), and condition 2 is the diagonal length 2 of the display area.
5 ", XGA resolution, 2nd covering the sustain electrode
The thickness of the dielectric layer was 30 μm (micron), and the condition 3
Is the diagonal length of the display area 42 ″, the XGA resolution, and the thickness of the second dielectric layer covering the sustain electrode 30 μm (micron). From this figure, even if the cell structure and size of the PDP are changed, The thickness of the first dielectric layer is 5 μm (micron)
It can be seen that abnormal discharge does not occur if it is below. Similarly, even if the composition and pressure of the filling gas are changed, abnormal discharge does not occur if the thickness of the first dielectric layer is 5 μm (micron) or less.

The reason will be described below. The smaller the film thickness of the first dielectric layer, the larger the capacitance C due to the first dielectric layer on the address electrode. As a result, more electrons per unit area can be retained as wall charges on the surface of the dielectric and phosphor on the address electrode. In this case, the electrons generated by the address discharge form a wall charge only in the cell where the address discharge is being performed, and do not form a wall charge on the adjacent space portion or on the dielectric of the adjacent cell. For this reason, the charge transfer in the address direction due to the electrons does not occur, and the charge separation, which causes abnormal discharge, is suppressed. FIG. 7 shows that the thickness of the first dielectric layer is 5 μm.
A value of (micron) or less indicates that, even if other conditions are different, electrons form wall charges only in the cell where the address discharge is being performed and do not cause charge transfer.

The smaller the thickness of the first dielectric layer, the larger the capacitance and the less likely it is for charge transfer to occur. However, if the thickness is extremely small, another effect appears. When the thickness of the first dielectric layer is smaller than about 1 μm (micron),
It becomes difficult to form an ideal dielectric layer over a large area on the address electrode. This is because the first dielectric layer is exposed to sandblast for forming a partition wall, and causes a very large number of atomic-level defects on the film surface. If the thickness of the dielectric layer is less than about 1 μm (micron), the dielectric layer must be considered to have substantially most of its surface. In such a dielectric layer, the electrical properties are different from those of an ideal dielectric due to atomic level defects, so that a sufficient amount of wall charges cannot be held, and the wall charges flow into the address electrode. Therefore, when the thickness of the first dielectric layer is smaller than about 1 μm (micron), the above-described charge separation, which causes abnormal discharge due to electric conduction of the dielectric film, in addition to the effect of the capacitance of the dielectric film. Will not occur. As long as the sand blast method is used to form the partition walls, the first dielectric layer, which is the blast protection film of the address electrode, is not completely eliminated, but its thickness is made smaller than about 1 μm (micron) to achieve blast protection and static electricity. Providing the effect of electric capacity and conductivity is a good measure from the viewpoint of product life and measures against abnormal discharge.

In the PDP of the present invention, it is desirable to satisfy the following additional conditions in order to more effectively suppress the occurrence of abnormal discharge.

The present invention, which satisfies one additional condition, is characterized in that in the above-described PDP, the thickness of the phosphor layer on the first substrate is 20 μm (micron) or less. If the thickness of the phosphor layer is too large, the influence of the capacitance of the phosphor layer on the address electrodes becomes dominant. As a result, even if the thickness of the first dielectric layer covering the surface of the address electrode is reduced, the effect is less likely to be exhibited, and the capacitance on the address electrode cannot be sufficiently increased. When the presence or absence of abnormal discharge was examined by changing the structure of the panel in FIG. 7, the thickness of the phosphor was 20 μm (micron). For a phosphor layer having a constant filling rate p, the emission intensity of visible light depends on the film thickness. When the thickness of the phosphor is increased,
The luminous intensity increases up to a film thickness of about 20 μm (micron), and the luminous intensity does not change significantly even if the film thickness is increased beyond that.

In the current phosphor coating method, the quality of the completed phosphor film is porous. Filling rate p of phosphor film
Is as low as about 0.3, and its effective capacitance is small. However, in the future, the coating method will be improved so that more precise film quality can be used. Since the emission intensity of visible light is determined by the amount of the phosphor itself, the filling rate p
Is doubled, the film thickness d can be halved. The capacitance of the phosphor is expressed by the ratio p / of the filling factor p and the thickness d of the phosphor.
In this case, the capacitance of the phosphor layer is 4
Double. As a result, even if the thickness of the first dielectric layer is the same, the charge separation can be more effectively suppressed.

According to the present invention, which satisfies another additional condition, in the above-described PDP, of the phosphor layers on the first substrate, the red phosphor layer is more compared with the green phosphor layer and the blue phosphor layer. It is characterized in that the film thickness is small. This additional condition corresponds to the fact that the electrical resistivity of the red phosphor is larger than the volume resistivity of the other two color phosphors. However, the magnitudes of the dielectric constants of the three color phosphors are equal to each other.

The wall charge formed on the dielectric layer is expressed as exp (-t
/ Τ) exponentially dissipates with time t. Here, the time constant τ is equal to the product of the resistance R of the dielectric and the capacitance C. That is, it can be seen that the red cell has a larger time constant than the cells of the other two colors, and dissipates the wall charges slowly. Therefore, even if the above-described charge separation in the direction of the address electrode occurs at the same size in the row of green cells, the row of blue cells, and the row of red cells, the total amount of charge separation is large in red cells in which wall charges are slowly dissipated. Abnormal discharge is likely to occur. So 3
In order to obtain the same magnitude of charge separation for the color cells, it is necessary to reduce the thickness of the red phosphor layer and increase the capacitance C. At this time, the time constant τ is constant irrespective of the film thickness, so that the speed of dissipation of the wall charges does not change. However, since the capacitance C on the address electrode increases, the charge transfer to the adjacent space or the adjacent cell occurs. Is suppressed.

According to the present invention, which satisfies still another additional condition, in the above-mentioned PDP, among the phosphor layers on the first substrate, the red phosphor layer is more luminous than the green phosphor layer or the blue phosphor layer. The film thickness is small, and the thickness of the red phosphor layer is 20 μm (micron) or less. This additional condition,
The above invention is numerically limited more clearly.

According to the present invention, which satisfies still another additional condition, in the above PDP, the thickness of the dielectric layer of the second substrate is 2
It is characterized by being at least 0 μm (micron). FIG.
Then, as described above, the thickness of the second dielectric layer is 20
３０30 μm (micron). When the thickness of the dielectric layer of the second substrate is reduced, the capacitance C increases.
The wall voltage V (= Q / C) becomes smaller for the wall charges Q having the same magnitude. In the AC type PDP, the condition for terminating the discharge is determined by the wall voltage V generated as a result of the discharge. Therefore, when the thickness of the dielectric is reduced, the discharge continues for a relatively long time and generates more wall charges Q. As a result, it is understood that the wall charges reaching the first dielectric layer covering the address electrodes increase, and the charge separation increases. Therefore, it is desirable that the thickness of the dielectric layer of the second substrate is 20 μm (micron) or more.

As described above, according to the present method, the thickness of the dielectric layer and the electrical characteristics are set in appropriate ranges, and the upper limit at which the discharge cell can maintain the potential difference due to the charge separation in the address electrode direction in the display area. By not exceeding the value, it is possible to provide a high-definition and high-luminance PDP capable of preventing abnormal discharge and stably displaying a clear image.

[0026]

According to the present invention, a plurality of address electrodes, a first dielectric layer covering the address electrodes, and a phosphor layer covering the first dielectric layer are formed on the surface. A first substrate, a plurality of sets of X sustain and Y sustain electrodes (scan electrodes) intersecting the address electrodes on the surface, and a second set of electrodes covering the sustain electrodes;
In a plasma display panel having a second substrate on which a first dielectric layer and a second dielectric layer are formed, and the first and second substrates are arranged to face each other via a discharge space, the thickness and electric characteristics of the dielectric layer are determined. By setting an appropriate range so that the potential difference due to charge separation in the address electrode direction in the display area does not exceed the upper limit value that the discharge cell can hold, abnormal discharge can be prevented and a clear image can be stably displayed. High definition and high brightness PD
P can be provided.

[Brief description of the drawings]

FIG. 1 shows a structure of a PDP capable of suppressing occurrence of abnormal discharge.

FIG. 2 shows the structure of a PDP.

FIG. 3 is a cross-sectional view of a PDP.

FIG. 4 is a perspective view of a PDP electrode arrangement.

FIG. 5 shows driving of a PDP.

FIG. 6 shows an electrode applied voltage waveform in one subfield.

FIG. 7: Dielectric film thickness and occurrence of abnormal discharge.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Front glass substrate, 2 ... Back glass substrate, 3 ... X sustain electrode, 4 ... Y sustain electrode, 5 ... Front plate dielectric, 6 ... Address electrode, 7 ... Dielectric covering address electrode, 8 ... Partition, 9: discharge space, 10: 1 frame, 1
1 ... first subfield, 12 ... second subfield,
13: third subfield, 14: fourth subfield, 15: fifth subfield, 16: sixth subfield, 17: reset discharge period, 18: address discharge period, 19: sustain discharge period, 20: bus electrode , 21
... Phosphor layer.

Continued on the front page (72) Inventor Eiji Fukumoto 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd.Hitachi Research Laboratories Co., Ltd. (72) Inventor Keizo Suzuki 1-280, Higashi Koikebo, Kokubunji-shi, Tokyo Hitachi, Ltd. Inside the Central Research Laboratory (72) Inventor Shoji Ishigaki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the New Display Business Promotion Center of Hitachi, Ltd. (72) Yoshimi Kawanami 1-280-1, Higashi-Koigakubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (72) Inventor Kunin, 1-280 Higashi Koigakubo, Kokubunji, Tokyo, Japan Inside the Hitachi, Ltd. Central Research Laboratory (72) Kenichi Yamamoto 1-280, Higashi Koikebo, Kokubunji, Tokyo, Hitachi, Ltd. Inside the research institute (72) Norihiro Uemura 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. No. 292, Hitachi, Ltd. Production Technology Laboratory, Hitachi, Ltd. (72) Ryohei Sato 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term (reference) 5C040 FA01 GB03 GB14 in the new display business promotion center of Hitachi, Ltd. GD01 GG01 GG03 MA20

Claims (5)

[Claims] A first substrate having a plurality of address electrodes formed on a surface thereof, a first dielectric layer covering the address electrodes, and a phosphor layer covering the first dielectric layer; A second electrode having a plurality of sets of X sustain and Y sustain electrodes (scan electrodes) intersecting the address electrodes on the surface and a second dielectric layer covering the sustain electrodes; In a plasma display panel having a substrate, wherein the first and second substrates are arranged to face each other via a discharge space, the thickness of the first dielectric layer covering the surface of the address electrode is 5 μm (micron) or less. A plasma display panel, characterized in that: 2. The phosphor layer on the first substrate has a thickness of 2
2. The plasma display panel according to claim 1, wherein the thickness is 0 μm (micron) or less. 3. The phosphor layer on the first substrate according to claim 1, wherein the thickness of the red phosphor layer is smaller than that of the green phosphor layer or the blue phosphor layer. Plasma display panel. 4. The plasma display panel according to claim 3, wherein the thickness of the red phosphor layer on the first substrate is 20 μm (micron) or less. 5. A method according to claim 1, wherein said second substrate has a dielectric layer having a thickness of 20 μm.
2. The plasma display panel according to claim 1, wherein the diameter is not less than m (microns).