JP3475173B2 - Charge pump circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit used in a power supply circuit or the like, and more particularly to a charge pump circuit in which the step of boosting voltage can be freely adjusted in steps smaller than the power supply voltage and the circuit efficiency is greatly improved. Regarding the circuit.

[0002]

2. Description of the Related Art A charge-pump circuit developed by Dickson is a pumping circuit.
A plurality of stages of packets (pumping packets) are connected in series, and a voltage higher than the power supply voltage Vdd of the LSI chip is generated by boosting the voltage of each pumping packet. For example, flash memory (Flas
It is used to generate voltage for program / erase of h memories.

These usage examples are intended for an output load current of about several tens of μA. Such a low load current charge pump circuit has a coupling capacitor (coupli).
MO acting as a diode
This is advantageous in that all SFETs and the like can be built into the LSI. 2. Description of the Related Art In recent years, a charge pump circuit that improves a boosting efficiency and generates a high voltage has been proposed with a decrease in a voltage of a flash memory.

On the other hand, in recent years, mobile devices such as video cameras, digital cameras, and mobile phones have become widespread, but these mobile devices require high voltage and large current (several mA) for displaying liquid crystal. A switching regulator is used as the high voltage generating circuit.

The principle of the switching regulator is that a large current is passed through the coil to boost the voltage at once with a back electromotive force, and a characteristic is that a high voltage and a large current can be obtained efficiently. Especially for mobile devices, power efficiency (output power / input power)
In this respect, switching regulators are suitable. However, when a large current is passed through the coil, harmonic noise is generated, and it is necessary to shield the power supply circuit to prevent the influence of this harmonic noise. Generation of high voltage with low noise in mobile devices has been required due to miniaturization and high sensitivity.

Each pumping packet of the charge pump circuit theoretically boosts the power supply voltage Vdd per stage, ignoring the voltage loss such as the threshold value of the diode. If the input voltage Vin of the charge pump circuit is Vdd and the pumping packets of n stages are connected in series from the power supply, (n + 1) × (Vd
d-Vt) can be boosted. Here, Vdd is the power supply voltage, and Vt is the forward threshold voltage of the diode.
In the following description, Vt = 0V is set for simplicity.

FIG. 9 shows a conventional charge pump circuit (n
= 4) is a schematic circuit diagram. In FIG. 9, D1 to D5
Is a diode connected in series, C1 to C4 are capacitors whose one ends are connected to the connection points of the diodes D1 to D5, and 1 is a clock Φ to the other ends of the capacitors D1 to D5.
It is a clock driver that supplies 1 and Φ2. Here, the clocks Φ1 and Φ2 are clock pulses having mutually opposite phases. Reference numeral 2 is a current load driven by the boosted voltage VH output from the diode D5 and the output current I _out . Here, this charge pump circuit has four pumping packets and corresponds to a four-stage (n = 4) charge pump circuit.

Next, the operation of this charge pump circuit will be described. When the clock output from the clock driver 1 is Φ1 = L level and Φ2 = H level, a current of 2 × I _out flows in the direction of the solid arrow in the figure. Where I _out is
It is the output current flowing from the diode D5 at the final stage.

Next, the clock Φ1 = H level, Φ2 = L
At the level, a current of 2 × I _out flows in the direction of the dotted arrow in the figure. By alternately flowing these currents, each stage is boosted, and 5Vdd is output as the boosted voltage VH from the diode D5 in the final stage.

When the output current flowing from the diode D5 in the final stage is I _out , the current input to the diode D1 in the first stage is equal to I _out on average. Further, the currents indicated by solid arrows and dotted arrows in the figure are also equal to I _out on average. Therefore, if the efficiency η of the charge pump circuit is defined as η = output power / input power (%), the efficiency of this circuit is expressed by the following equation.

Η = 5 Vdd × I _out / Vdd × 5 I _out = 100% That is, under the above operating conditions, the efficiency of this charge pump circuit is 100%.

As mentioned above, the charge pump circuit is
(n + 1) × Vdd is boosted and output. However, n is the number of pumping stages of the charge pump circuit, and Vdd is the power supply voltage. Therefore, for example, if Vdd = 5V, n
The theoretical value VHn of the output voltage of the stage charge pump is n = 1
In the case of VH ₁ = 2 × Vdd = 10V, and in the case of n = 2, VH
When H ₂ = 3 × Vdd = 15V and n = 3, VH ₃ = 4 ×
The step voltage has Vdd steps, such as Vdd = 20V.

[0013]

Now, for example, when the charge pump circuit is used as a high voltage generating circuit, it is possible to adjust the voltage by a regulator in order to set a desired high voltage. FIG. 10 is a schematic circuit diagram of an n-stage charge pump circuit provided with a regulator. In FIG. 10, the same components as those in FIG. 9 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 10, D1 to Dn are diodes connected in series. The boosted voltage VHn output from the final stage diode Dn is stepped down by the regulator 3 and supplied to the current load 2. The final output voltage obtained through the regulator 3 is Vout, and the output current is I
If out, the efficiency η of the charge pump circuit is η =
Output power / Input power = Vout × Iout / (n + 1) ×
It is defined as Vdd × Iout = Vout / (n + 1) · Vdd.

The number n of charge pump stages is large, that is, the boost ratio =
When VHn / Vdd is large, the charge pump circuit can obtain almost high efficiency. However, if the power supply voltage fluctuation range is wide and Vout / Vdd is small, the efficiency deteriorates. For example, the number of charge pump stages n is Vdd = 4V to 5.5V, Vou as a variable control system.
Assume a specification of t = 6.5V. Then, under this assumption, the number of stages n = 1 is optimal, and Vdd = 4V,
The efficiency η of the charge pump circuit at each power supply voltage of 5 V and 5.5 V is as follows. Vdd = 4V n = 1 VH = 8V η = 81% Vdd = 5V n = 1 VH = 10V η = 65% Vdd = 5.5V n = 1 VH = 11V η = 59% Thus, the power supply voltage Vdd rises And the efficiency η will deteriorate. Here, if n = 0.5 exists, the following high efficiency is obtained. Vdd = 4V n = 1 VH = 8V η = 81% Vdd = 5V n = 0.5 VH = 7.5V η = 86% Vdd = 5.5V n = 0.5 VH = 8.25V η = 79% Is 0.5 in the charge pump circuit.
It means that it is performed in the step of Vdd. However, the conventional charge pump circuit performs boosting in Vdd steps, and no charge pump circuit capable of boosting in voltage steps smaller than Vdd has been proposed.

Therefore, an object of the present invention is to provide a charge pump circuit capable of boosting voltage steps smaller than Vdd and improving the efficiency η of the circuit. That is, the charge pump circuit proposed by the present inventor has theoretical output voltages of 1.5 Vdd, 2 Vdd,
It is possible to obtain 2.5 Vdd, 3 Vdd, .... Another object of the present invention is to extend this basic charge pump circuit to provide 1.5Vd
d, 1.75 Vdd, 2 Vdd, 2.25 Vdd, 2.
5Vdd, 2.75Vdd, 3Vdd, ... Furthermore, for example, 1.33Vdd, 1.66Vdd, 2Vd
d, 2.33 Vdd, 2.66 Vdd, 3 Vdd, and so on, to obtain a boosted voltage in an arbitrary voltage step. It is also possible to obtain the same negative voltage. The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

[0017]

The typical ones of the inventions of the present application will be outlined below.

The first charge pump circuit includes a plurality of diodes connected in series, two or more capacitors connected to the connection points of the diodes, a clock supply means for supplying a clock to the capacitors, and a voltage level of the clock. And switch means for connecting two or more capacitors in series or in parallel to the connection point of the diode,
The boosted voltage is output from the diode.

Such a structure constitutes the basic structure of the present invention, and is capable of boosting a voltage step smaller than the power supply voltage and improving the efficiency η of the circuit.

The second charge pump circuit is connected to a plurality of diodes connected in series, a voltage source for supplying a power supply voltage to the first stage diode, and a connection point between the first stage diode and the next stage diode. 2 or more capacitors,
Clock supply means for supplying a clock to the capacitor,
Switch means for connecting the two or more capacitors in series to the connection point of the diode when the clock is at the L level and for connecting the two or more capacitors in parallel to the connection point of the diode when the clock is at the H level; And a positive boosted voltage with a voltage step smaller than the power supply voltage is output from the diode at the final stage.

According to this structure, it is possible to boost the voltage in a positive voltage step smaller than the power supply voltage and improve the efficiency η of the circuit.

The third charge pump circuit includes a plurality of diodes connected in series, a plurality of diodes connected in series, a voltage source for supplying a power supply voltage to the first stage diode, a first stage diode and a second stage diode. Two or more first capacitors connected to the connection point with the diode of, and one or more second capacitors connected to the connection point of other diodes except the connection point
And a clock supply means for alternately supplying clocks of opposite phases to the first capacitor and the second capacitor, and the second or more of the first capacitors depending on the voltage level of the clock supplied to the first capacitor. Switch means for switching the connection state of the capacitor, the switch means,
When the clock supplied to the first capacitor is at the L level, two or more capacitors are connected in series at the connection point between the first stage diode and the next stage diode, and when the clock is at the H level, the two or more capacitors are connected. Switching is performed so that the points are connected in parallel, and a positive boosted voltage obtained by adding a voltage step smaller than the power supply voltage to the voltage step of the power supply voltage is output from the final stage diode.

According to this structure, a positive boosted voltage obtained by adding a voltage step smaller than the power supply voltage to the voltage step of the power supply voltage can be output, and the efficiency η of the circuit can be improved.

The fourth charge pump circuit includes second and third charge pump circuits.
Of the charge pump circuit, the switch control means for controlling the switch means is provided, and the two or more capacitors are connected to the first stage diode and the second stage diode in accordance with a switch control signal output from the switch control means. The connection point is switched between always connected in series or connected in series or in parallel according to the level of the clock.

According to this structure, the voltage step-up of the power supply voltage and the step-up of the voltage step smaller than the power supply voltage can be realized by one charge pump circuit.
The boosted voltage can be set with higher accuracy and the efficiency η of the circuit can be improved.

The fifth charge pump circuit includes the second and third charge pump circuits.
In the above charge pump circuit, a regulator for adjusting the boosted voltage output from the diode at the final stage is provided.

The sixth charge pump circuit, in the third, fourth and fifth charge pump circuits, is a voltage detecting means for detecting the boosted voltage output from the diode at the final stage and a charge detecting circuit according to the detection result. And a charge pump circuit stage number control means for controlling the stage number of the pump circuit.

According to this structure, according to the boosted voltage,
By switching the number of stages of the charge pump circuit and adjusting the boosted voltage, the efficiency η of the circuit can be further improved.

The seventh charge pump circuit includes first, second,
In the charge pump circuits 3, 4, 5 and 6, the diode is composed of a MOS transistor whose gate and source are commonly connected. According to such a configuration, it is not necessary to separately form the diode in the MOS process, and it is easy to manufacture.

The eighth charge pump circuit includes first, second,
In the charge pump circuits 3, 4, 5 and 6, the switching means is composed of MOS transistors. According to this structure, the number of circuit elements is small and the structure is simple.

The ninth charge pump circuit has a plurality of diodes connected to each other in series, the ground voltage being supplied to the first-stage diode, and two or more connected to the connection point between the first-stage diode and the next-stage diode. Capacitor of
A clock driver means for supplying a clock to a capacitor, and two or more capacitors are connected in series to a diode connection point when the clock is at H level, and two or more capacitors are connected in parallel to the diode connection point when the clock is at L level. Switch means for switching to connect,
The negative boosted voltage is output in a voltage step smaller than the power supply voltage supplied from the final stage diode to the clock driver means.

According to this structure, it is possible to boost the voltage by a negative voltage step smaller than the power supply voltage and improve the efficiency η of the circuit.

In the tenth charge pump circuit, a ground voltage is supplied to the first-stage diode and a plurality of diodes connected in series and two or more connected to the connection point of the first-stage diode and the next-stage diode. A first capacitor, one or more second capacitors connected to the connection points of other diodes except the connection point, and a clock for alternately supplying a clock of opposite phase to the first capacitor and the second capacitor The power supply device includes a supply means and a switch means for switching the connection state of two or more first capacitors according to the voltage level of the clock supplied to the first capacitor, and the switch means is supplied to the first capacitor. When the clock is at the H level, connect two or more capacitors in series at the connection point between the first stage diode and the next stage diode, and when the clock is at the L level. Switching two or more capacitors to be connected in parallel to the connection point, and outputting a negative boosted voltage from the final stage diode in a voltage step smaller than the power supply voltage supplied to the clock driver means. Is.

According to this structure, the negative boosted voltage can be output in a voltage step smaller than the power supply voltage supplied to the clock driver means, and the efficiency η of the circuit can be improved.

The eleventh charge pump circuit is the ninth and tenth charge pump circuits, and the switch means is
It is controlled according to the switch control signal so that two or more capacitors are always connected in series at the connection point between the first-stage diode and the second-stage diode, regardless of the voltage level of the clock supplied to the first capacitor. It is that.

According to this structure, the voltage step of the power supply voltage and the step of the voltage step smaller than the power supply voltage can be realized by one charge pump circuit, and the boosted voltage can be set with higher accuracy, and the circuit can be set with higher accuracy. Efficiency of
Can be improved.

The twelfth charge pump circuit is the ninth and tenth charge pump circuits provided with a regulator for adjusting the boosted voltage output from the diode at the final stage.

The thirteenth charge pump circuit is the same as the ninth, tenth, eleventh and twelfth charge pump circuits.
A voltage detecting means for detecting the boosted voltage output from the diode at the final stage and a charge pump circuit stage number controlling means for controlling the number of stages of the charge pump circuit according to the detection result are provided.

According to this structure, according to the boosted voltage,
By switching the number of stages of the charge pump circuit and adjusting the boosted voltage, the efficiency η of the circuit can be further improved.

The fourteenth charge pump circuit is the same as the ninth to thirteenth charge pump circuits, in which the diode is composed of a MOS transistor whose gate and source are commonly connected. According to such a configuration, it is not necessary to separately form the diode in the MOS process, and it is easy to manufacture.

The fifteenth charge pump circuit is the ninth to thirteenth charge pump circuits, and the switch means is
It is composed of MOS transistors. According to this structure, the number of circuit elements is small and the structure is simple.

[0042]

BEST MODE FOR CARRYING OUT THE INVENTION First to sixth embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a schematic circuit diagram showing a charge pump circuit according to the first embodiment.

In FIGS. 1A and 1B, the diode D
1, D2 are connected in series, and the power supply voltage Vdd is supplied to the anode of the diode D1. Diode D
1 and D2 can be configured by, for example, MOS transistors whose gates and drains are commonly connected. S
1, S2, S3 are at the connection points of the diodes D1, D2,
It is a switch for switching and connecting the capacitors C1A and C1B in parallel or in series.

These switches S1, S2, S3 can be constituted by MOS transistors, for example. Reference numeral 11 is a clock driver that supplies a clock to the capacitor C1B. Clock driver 11
Is composed of, for example, a two-stage CMOS inverter. Reference numeral 12 is a load to which the boosted voltage VH output from the diode D2 is supplied. CL is the capacitance of the output node of the diode D2.

The operation of this charge pump circuit will be described below. When the input clock of the clock driver 11 is at L level (CLK = Low),
As shown in (a), S1 = off, S2 = on, S3 =
When turned off, the two capacitors C1A and CIB are connected in series to the connection point of the diodes D1 and D2. Then, the capacitors C1A and C1B are charged to Vdd / 2. At this time, from the power supply voltage Vdd to the capacitor C1
When the current flowing into A and C1B is Iin, the same current Idv = Iin flows into the clock driver 11.

Next, when the input clock of the clock driver 11 is at H level (CLK = High), as shown in FIG.
As shown in (b), S1 = on, S2 = off, S3 =
When turned on, the two capacitors C1A and C1B are connected in parallel to the connection point of the diodes D1 and D2. Then,
Since the voltage of each of the capacitors C1A and C1B is Vdd / 2, if the output of the clock driver 11 is Vdd, the voltage VH1 at the connection point of the diodes D1 and D2 is 1.
Boosted to 5Vdd. At this time, the current flowing from the two capacitors C1A and C1B to the diode D2 at the next stage is 2 × Iin. The same current Idv = 2 × lin flows out from the clock driver 11.

Output current I output from the diode D2
When out is constant and all currents are time average currents, the following is obtained in a steady state. Iin = Iout / 2 Vout = 1.5 Vdd (provided that the power supply voltage of the driver is Vdd) Idv = Iout / 2 (current flowing into the clock driver) Idv = Iout (current flowing out of the power supply Vdd of the clock driver) where Vout Is the output voltage output from the diode D2, and for simplification, the threshold voltage of the diodes D1 and D2 is set to 0V.

The point of the charge pump circuit of this embodiment is that the capacitor C1 is changed in accordance with the level of the clock CLK.
By repeatedly connecting A and C1B in series and charging and connecting in parallel and discharging, voltage boosting is performed in steps of Vdd / 2. Also, the important point here is CL
The point is that when K = L, the input current Iin from the power supply voltage Vdd is 1/2 of the output current Iout. As a result, the theoretical efficiency η of the circuit when the output voltage is not regulated can be set to 100%, and there is no power loss due to the boosted voltage being 1.5 Vdd.

That is, since the input current is the sum of Iout when CLK = H and Iout / 2 when CLK = L, η = output power / input power = (1 + 0.5) × Vdd × Iout / Vdd × 1.5Iout = 100% This can be said to be substantially a 0.5-stage charge pump circuit. Moreover, the theoretical efficiency η of the circuit can be 100%. Other methods of producing a voltage of 0.5 Vdd can be considered. For example, a method using resistance division. However, the efficiency η of the circuit cannot be set to 100%, which causes power loss. On the other hand, according to the present invention, the connection of the capacitors is alternately switched in parallel and in series according to the level of the clock CLK, so that the power loss can theoretically be 0%.

If the two capacitors C1A and C1B are operated in series regardless of the state of the clock CLK (S1 = OFF, S2 = ON, S3 = OFF), the same function as the conventional charge pump is obtained. And Vout = 2Vd
It becomes d. In this case, a switch control circuit (negative is shown) is provided, and switches S1, S2, S are connected from this switch control circuit.
By supplying the switch control signal to 3, the two capacitors C1A and C1B can be switched to be always connected in series or connected in series or in parallel according to the voltage level of the clock CLK.

That is, the charge pump circuit of this embodiment can obtain 1.5 Vdd or 2 Vdd as the output voltage Vout. In other words, it is possible to switch between 0.5 stage and 1 stage.

Further, if the 0.5-stage charge pump circuit is generalized, it is possible to obtain an output voltage Vout of Vdd + Vdd / m by switching m capacitors in series and in parallel.

In FIG. 2, the changeover switches S1 to S3 are MOS.
It is a 0.5-stage charge pump circuit replaced with an FET (MOS transistor). The switches S1, S2, S3 correspond to the MOS transistors M1, M2, M3, respectively. The part surrounded by the dotted line is the series-parallel capacitor 13
Therefore, the series-parallel capacitor 13 will be represented by a symbol as shown below.

FIG. 3 is a schematic circuit diagram showing a charge pump circuit according to the second embodiment. This charge pump circuit is a (n + 0.5) Vdd boost charge pump circuit, and outputs a boosted voltage of (n + 0.5) Vdd or (n + 1) Vdd according to the number of stages n.

In FIG. 3, diodes D1 to Dn + 1 are connected in series, and the power supply voltage Vdd is supplied to the anode of the diode D1. The diodes D1 to Dn + 1 can be composed of, for example, MOS transistors whose gates and drains are commonly connected. The serial-parallel capacitor 13 is connected to the connection point of the diodes D1 and D2, and the clock CLK is supplied from the clock driver 11a.

Capacitors C2 to Cn are connected to the connection points of the diodes D2 and Dn + 1, and clocks CLK2 to CLKn are supplied from the clock driver 11b. Here, the clocks CLK and CLK2 to CLKn are
Assume that the clocks have opposite phases alternately. Reference numeral 14 is a regulator for adjusting the boosted voltage VHn + 1 output from the diode Dn + 1. Then, the output V of the regulator 14
out is applied to the load 12.

A detection circuit 15 detects the boosted voltage VHn + 1, and outputs the detection result to the charge pump circuit stage number control circuit 16. The detection circuit 15 is, for example, a differential amplifier that compares the boosted voltage VHn + 1 with the reference voltage Vref, and outputs “H” when VHn + 1> Vref, and outputs “L” when VHn + 1 <Vref. Is output.

The charge pump circuit stage number control circuit 16 includes
A clock control signal is output to the clock driver 11b according to the output of the detection circuit 15. The clock driver 11b is composed of, for example, a NAND circuit. Also,
Reference numeral 17 indicates whether to boost 0.5 Vdd by the series-parallel capacitor 13 or Vdd depending on the detection result of the detection circuit 15.
It is a series-parallel capacitor control circuit that switches whether to boost the voltage.

The charge pump circuit stage number control circuit 16 includes
The number of stages of the charge pump circuit is controlled according to the output of the detection circuit 15. Power is supplied from the battery, and the power supply voltage Vdd decreases as the battery is consumed. And the power supply voltage Vd
The change in d appears as the value of VHn + 1. If the power supply voltage Vdd rises, VHn + 1 rises, and if the power supply voltage Vdd falls, VHn
It also drops by +1. A desired Vout is obtained by Vout = VHn + 1−Δv by the regulator. At this time, Δv is a voltage to be discarded, and minimizing Δv leads to improvement in efficiency of the charge pump circuit.

When the power supply voltage Vdd is high, the number of stages of the charge pump circuit is reduced, and when the power supply voltage Vdd is low, the number of stages of the charge pump circuit is increased to minimize Δv. After the switch of the portable device is turned on and the operation of the charge pump circuit is stabilized, the charge pump circuit stage number control circuit 16 operates to optimize the stage number of the charge pump circuit. The number of controlled stages does not change until the mobile device is switched off. That is, the charge pump circuit stage number control circuit 16 operates every time the switch of the portable device is turned on.

For example, the clock CKL in FIG.
MOSF acting as a diode with n'fixed at H level
ET is always on. This has one charge pump stage
It is equivalent to the reduction. When reducing the number of stages by 0.5, as described above, the capacitors of the pumping packet at the first stage are operated in series and in parallel. With this combination, the number of charge pumps is substantially n stages, n-0.5 stages, n-1
Adjustable in steps, n-1.5 steps, n-2 steps, .... It suffices to set the number of steps that minimizes Δv.

The (n + 0.5) Vdd boost charge pump circuit is a combination of the 0.5-stage or 1-stage charge pump circuit and the n-stage charge pump circuit of the first embodiment, and the boost voltage VHn thereof. +1 is (n + 0.
5) Vdd or (n + 1) Vdd. Further, by making the detection circuit 15 and the charge pump circuit stage number control circuit 16 function, the stage number of the n-stage charge pump circuit can be made variable. Accordingly, the boosted voltage VH
n + 1 can be variable. For example, if the clock CLKn 'is fixed to H level (clock stopped) by the clock control signal generated by the charge pump circuit stage number control circuit 16 and the MOS transistor corresponding to Dn + 1 is always turned on, the charge pump stage number is n. It becomes -1.

Thus, the (n + 0.5) Vdd step-up charge pump circuit has 1.5Vdd, 2Vdd, and 2.5V.
A boosted voltage in 0.5 Vdd steps is output, such as dd, 3 Vdd .... And the regulator 14
The boosted voltage is adjusted to a desired voltage and applied to the load 12.

FIG. 4 is a schematic circuit diagram showing a charge pump circuit according to the third embodiment. This charge pump circuit is a -0.5 Vdd boosting charge pump circuit, which creates a boosting voltage of -0.5 Vdd with respect to the ground voltage.

In FIGS. 4A and 4B, the diodes D'1 and D'2 are connected in series, and the cathode of the diode D'1 is supplied with the ground voltage (0V). The diodes D′ 1 and D′ 2 can be configured by, for example, MOS transistors whose gates and drains are commonly connected.

S1, S2 and S3 are diodes D'1,
A switch for switching and connecting the capacitors C1A and C1B in parallel or in series to the connection point of D′ 2. These switches S1, S2, S3 can be constituted by MOS transistors as shown in FIG. Reference numeral 21 is a clock driver that supplies a clock to the capacitor C1B. The clock driver 21
For example, it is configured by a two-stage CMOS inverter. The output voltage output from the diode D′ 2 is applied to the load (not shown).

The operating principle of this charge pump circuit is the first
The embodiment is similar to that of the above embodiment, but its outline is as follows.

When the input clock of the clock driver 21 is H level (CK1 = High), if S1 = OFF, S2 = ON, S3 = OFF, the two capacitors C1A and C1B are connected in series, and The terminal voltage is 0 V, Vdd / 2, V as shown in FIG.
It becomes dd. That is, each capacitor has Vdd / 2
Is charged to the voltage of.

When the input clock of the clock driver 21 is at L level (CK2 = Low), if S1 = on, S2 = off and S3 = on, the two capacitors C1A and C1B are connected in parallel. Since the output voltage of the clock driver 21 drops from Vdd to 0V, the voltage VL1 at the pump node is VL1 = Vdd / 2−Vd.
d = -Vdd / 2.

Assuming that the current flowing through the load is constant and the currents are all time-averaged currents, the following is obtained in a steady state. Current of diode D'1 ID1 = Iout / 2 Current of diode D'2 ID2 = Iout Clock driver current dv1 = Iout / 2 (CK1 = High) Clock driver current Idv2 = Iout (CK2 = Low) Vout = -0 ． 5Vdd (provided that the power supply voltage of the driver is Vdd) -0.5Vdd The input power of the boost charge pump circuit is
It is the power consumption of the driver. Further, when CK1 = H, the current ID1 of the diode D1 ′ is the output current ID2 =
It is 1/2 of Iout. Therefore, if there is no output regulation, the theoretical efficiency will be 100%, and Vout
= There is no loss due to setting to -0.5 Vdd. That is,
Similar to that of the first embodiment, the efficiency η of the circuit is 100% as in the following equation.

Η = 1.5 Vout × Iout / Vout
× 1.5Iout = 100% Further, the two capacitors C1A and C1B are clocked by CK.
If operated in series (S1 = OFF, S2 = ON, S3 = OFF) irrespective of the states of 1 and CK2, the same function as that of the conventional charge pump is achieved and Vout = −Vdd.

In this case, a switch control circuit (negative is shown) is provided, and switches S1, S2,
By supplying a switch control signal to S3, it is possible to switch between connecting the two capacitors C1A and C1B in series at all times or in series or in parallel according to the voltage levels of the clocks CK1 and CK2. To be done.

That is, the charge pump circuit of this embodiment can obtain -0.5 Vdd or -Vdd as the output voltage Vout. In other words, 0.5
It is possible to switch between steps and one step.

When the -0.5Vdd charge pump circuit is generalized, the output voltage Vout of -Vdd / m can be obtained by switching m capacitors in series or in parallel.

FIG. 6 is a schematic circuit diagram showing a charge pump circuit according to the fourth embodiment. This charge pump circuit is a -0.5Vdd step boost charge pump circuit, and outputs a boosted voltage of-(n-0.5) Vdd or -nVdd under the control of the switches S1, S2 and S3.

In FIG. 6, diodes D'1 to D'n + 1 are provided.
Are connected in series, and the ground voltage (0 V) is supplied to the node of the diode D'1. Diode D'1 ~
D'n + 1 can be constituted by, for example, a MOS transistor in which the gate and the drain are commonly connected.

The serial-parallel capacitors of the third embodiment are connected to the connection points of the diodes D'1 and D'2, and the clocks CK1 and CK2 are supplied from the clock driver 21. In FIG. 6, the input clock of the clock driver 21 is CK1 = High, but naturally CK2 =
Including the case of Low. In addition, each diode D'2-D '
The capacitors C2 to Cn are connected to the respective connection points of n + 1, and the clock driver 21 outputs the clocks CK2 to CK.
n is supplied.

In FIG. 6, C3 to Cn and other clock drivers are omitted. Here, the clocks CK1 and CK2 to CKn are alternating clocks having opposite phases. A load 22 is a load to which the boosted voltage VHn + 1 output from the diode D′ n + 1 is applied.

This -0.5 Vdd step boost charge pump circuit is a combination of the 0.5 stage or 1 stage charge pump circuit and the n stage charge pump circuit of the third embodiment, and the boost voltage VHn + 1 is -(N-
0.5) Vdd or -nVdd. Also, the second
Similar to the embodiment described above, by providing the detection circuit and the charge pump circuit stage number control circuit, the stage number of the n-stage charge pump circuit can be made variable. Accordingly, the boosted voltage VHn + 1 can be made variable. For example, the clock CLKn is stopped, and M corresponding to D'n + 1
If the OS transistor is always turned on, the number of charge pump stages becomes n-1.

Thus, the -0.5 Vdd step boost charge pump circuit is -0.5 Vdd, -Vdd,-.
It outputs a boosted voltage in steps of -0.5 Vdd, such as 1.5 Vdd, -2 Vdd, -2.5 Vdd ....
Further, by providing a regulator (not shown) at the output stage of the diode D′ n + 1, the boosted voltage VHn + 1 can be adjusted to the desired voltage Vout and applied to the load 22.

FIG. 7 is a schematic circuit diagram showing a charge pump circuit according to the fifth embodiment. This charge pump circuit is a 1.25 Vdd boost charge pump circuit. In FIGS. 10A and 10B, the diodes D1 and D
2 are connected in series, and the power supply voltage Vdd is supplied to the anode of the diode D1. Diodes D1 and D2
Can be composed of, for example, a MOS transistor in which the gate and the drain are commonly connected. S1 to S9
Is a capacitor C1 at the connection point of the diodes D1 and D2.
A switch for switching and connecting A, C1B, C1C, and C1D in parallel or series.

These switches S1 to S9 can be composed of, for example, MOS transistors. Reference numeral 31 is a clock driver that supplies a clock to the capacitor C1D. The clock driver 31
For example, it is configured by a two-stage CMOS inverter. The output voltage output from the diode D2 is applied to the load (not shown).

The operation of this charge pump circuit will be described below. When the input clock of the clock driver 31 is at L level (CLK = Low), FIG.
As shown in (a), S1 to S3 = on, S4 to S9 =
When turned off, the four capacitors C1A to CID are connected in series to the connection points of the diodes D1 and D2. Then, the capacitors C1A to C1D are charged to Vdd / 4.

Next, when the input clock of the clock driver 31 is at H level (CLK = High), as shown in FIG. 7B, S1 to S3 = OFF, S4 to S9.
When turned on, the four capacitors C1A to C1D are connected in parallel to the connection points of the diodes D1 and D2. Then, since the voltage of each of the capacitors C1A to C1D is Vdd / 4, assuming that the output of the clock driver 11 is Vdd, the voltage at the connection point of the diodes D1 and D2 is 1.25.
Boosted to Vdd.

FIG. 8 is a schematic circuit diagram showing a charge pump circuit according to the sixth embodiment. This charge pump circuit is a 0.25 Vdd step ± step-up charge pump circuit. In FIG. 8, 30 is a + 0.25Vdd step boost charge pump circuit, and 50 is -0.25V.
dd step boost charge pump circuit, 40 is +1.
A 25Vdd boosting charge pump circuit, whose output voltage 1.25Vdd is supplied as the power supply voltage of the clock drivers 31b and 51b in accordance with the switching of the switches S10 and S11. The + 1.25Vdd boosting charge pump circuit 40 has the same configuration as that of the fifth embodiment, and therefore detailed description thereof will be omitted.
It includes two series-parallel capacitors 42 and outputs a voltage of 1.25 Vdd.

The +0.25 Vdd step boost charge pump circuit 30 increases the boost voltage Vout in 0.25 steps.
= 1.5Vdd, 1.75Vdd, 2Vdd, 2.25
Vdd, 2.5Vdd, 2.75Vdd, ... Are output. On the other hand, the -0.25Vdd step-up charge pump circuit 50 has -0.5Vdd, -Vdd, -1.5V.
dd, -1.75Vdd, -2Vdd, -2.25Vd
It outputs d, -2.5Vdd, -2.75dd, ....
The two charge pump circuits 30 and 50 operate separately as will be described later, but by combining these, a positive voltage power supply and a negative voltage power supply can be configured.

The configuration of the +0.25 Vdd step boost charge pump circuit 30 is as follows. Diode D
1 to Dn + 1 are connected in series, and the power supply voltage Vdd is supplied to the anode of the first-stage diode D1. 33 (C1) is two series-parallel capacitors connected to the connection point of the diodes D1 and D2, and C2, C3 ...
A capacitor connected to each connection point of the diodes D2 to Dn + 1, and 32 is a load connected to the output of the diode Dn + 1.

Further, 31a is a clock driver for supplying the clock CLK to the series-parallel capacitor 33, and 31b is a clock driver for supplying the clock CLK to the capacitors C2, C3 .... Here, it is assumed that the clocks CLK of the clock drivers 31a and 31b are clocks of opposite phases alternately. Further, S10 is 1.25 Vdd or Vd as the power supply voltage of the clock driver 31a.
It is a switch for switching and supplying d.

If necessary, like the second embodiment, a detection circuit, a charge pump circuit stage number control circuit, and a regulator can be provided.

Next, the configuration of the -0.25 Vdd step boost charge pump circuit 50 is as follows. The diodes D′ 1 to D′ n + 1 are connected in series, and the anode of the first-stage diode D′ 1 has a ground voltage (0 V).
Is being supplied. 53 (C'1) is a diode D '
Two serial-parallel capacitors C'2, C'3 ... Connected to the connection point of 1, D'2 are diodes D'2-D'n +
1 is a capacitor connected to each connection point, and 52 is a load connected to the output of the diode D'n + 1.

Further, 51a is a clock driver for supplying the clock CK to the serial-parallel capacitor 53, 51b is a clock driver for supplying the clock CK to the capacitor C'2, 51c is a clock driver for the capacitor C'3 ...
Is a clock driver that supplies. Here, the clock CK of each clock driver 51a, 51b, 51c
Are clocks of alternating phases. In addition, S11
Is 1.2 as the power supply voltage of the clock driver 51b.
It is a switch for switching and supplying 5 Vdd or Vdd. Further, if necessary, as in the second embodiment, a detection circuit, a charge pump circuit stage number control circuit, and a regulator can be provided.

The operation of the +0.25 Vdd step boost charge pump circuit 30 will be described below. Now, focusing on the pump node voltage VH1 of the first stage, it is assumed that the switch 10 is switched to the Vdd side and Vdd is supplied to the power supply voltage of the clock driver 31a. Then, the pump node voltage VH1 is, as described in the first embodiment, the series-parallel capacitor 33.
, Vdd + 1 / 2Vdd
= 1.5Vdd, Vdd + Vdd = 2Vdd when the series-parallel capacitors always operate in series connection.

On the other hand, it is assumed that the switch 10 is switched to the 1.25 Vdd side and 1.25 Vdd is supplied to the power supply voltage of the clock driver 31a. Then, 1.25Vdd + 1 / 2Vdd = 1.75Vdd when the series-parallel capacitor 33 performs the series-parallel switching operation, and 1.2 when the series-parallel capacitor always operates in series connection.
5Vdd + Vdd = 2.25Vdd.

That is, the pump node voltage VH1 is 1.5 Vdd, 1.75 Vdd, 2 Vdd, 2. Vd depending on the switching of the switch 10 and the series-parallel capacitor 33.
It can be seen that 25 Vdd can be obtained. Therefore, Vdd is added to the pump node voltage of the second stage, so 2.5 Vdd, 2.75 Vdd, 3 Vdd, 3.2.
It can be seen that 5 Vdd is obtained. In this way, by controlling the number n of charge pump stages after the second stage, an arbitrary 0.
A boosted voltage in 25 Vdd steps can be obtained.

The same applies to the operation of the -0.25 Vdd step-up charge pump circuit 50.
The difference is that the power supply voltage of the clock driver 51b connected to the capacitor C2 of the stage is switched by the switch 11. This is because if the power supply voltage of the clock driver 51a of the first stage is to be switched, the power supply voltage will be halved, and a voltage step of 0.25 Vdd cannot be obtained.

As a result, the first-stage pump node voltage V
As H′1, according to the switching of the series-parallel capacitor 53,
0.5 Vdd or Vdd is obtained, and as the second stage pump node voltage VH′2, depending on the switching of the switch 11, −1.5 Vdd, −1.75 Vdd, −2 Vdd,
-2.25 Vdd is obtained. In this way, by controlling the number of charge pump stages after the third stage,
A boosted voltage in 0.25 Vdd steps can be obtained.

In the charge pump circuit of this embodiment, it is also within the scope of the patent that the boosted voltage at any step can be obtained by changing the number of capacitors in the series-parallel capacitors 33, 42 and 53. For example,
By configuring the serial-parallel capacitors 33, 42, and 53 by the changeover switch corresponding to the three capacitors,
A charge pump circuit of 0.33 Vdd steps can be configured. That is, the boosted voltage in this case is
1.33 Vdd, 1.66 Vdd, 2 Vdd, 1. ．
33Vdd, 2.66Vdd, 3Vdd, ..., -1.6
6, -2Vdd, -2.33Vdd, -2.66Vd
d, −3 Vdd, ...

[0098]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

First, by switching the capacitors in series or in parallel according to the clock level, the power supply voltage Vd
This makes it possible to obtain a positive or negative boosted voltage with a voltage step smaller than d, and improve the efficiency η of the circuit.

Second, by combining with the n-stage charge pump circuit, a positive or negative boosted voltage obtained by adding a voltage step smaller than the power supply voltage to the voltage step of the power supply voltage Vdd can be output. And the efficiency of the circuit η
Can be improved.

Thirdly, by further comprising a regulator, a voltage detection means, and a clock control means, the number of stages of the charge pump circuit is switched according to the boosted voltage and the boosted voltage is adjusted to further increase the efficiency η of the circuit. Can be improved.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram showing a charge pump circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing changeover switches S1 to S3 that are MOSFET
FIG. 6 is a schematic circuit diagram showing a 0.5-stage charge pump circuit replaced with an S transistor).

FIG. 3 is a schematic circuit diagram showing a charge pump circuit according to a second embodiment.

FIG. 4 is a schematic circuit diagram showing a charge pump circuit according to a third embodiment.

FIG. 5 is a circuit diagram showing changeover switches S1 to S3 that are MOSFET (MO
FIG. 6 is a schematic circuit diagram showing a 0.5-stage charge pump circuit replaced with an S transistor).

FIG. 6 is a schematic circuit diagram showing a charge pump circuit according to a fourth embodiment.

FIG. 7 is a schematic circuit diagram showing a charge pump circuit according to a fifth embodiment.

FIG. 8 is a schematic circuit diagram showing a charge pump circuit according to a sixth embodiment.

FIG. 9 is a schematic circuit diagram showing a conventional charge pump circuit (n = 4).

FIG. 10 is a schematic circuit diagram of an n-stage charge pump circuit provided with a regulator.

[Explanation of symbols]

D1, D2 diode C1A, C1B capacitors S1, S2, S3 switches 11 clock driver 12 load 13 series-parallel capacitor 14 Regulator 15 Detection circuit 16 Charge pump circuit Number of stages control circuit

Claims (15)

(57) [Claims] 1. A plurality of diodes connected in series, two or more capacitors connected to a connection point of the diodes, a clock supply means for supplying a clock to the capacitors, and a voltage supply circuit according to a voltage level of the clock. A switch means for connecting the two or more capacitors in series or in parallel to the connection point of the diode, and outputting a boosted voltage from the diode. 2. A plurality of diodes connected in series, a voltage source for supplying a power supply voltage to the first stage diode, and two or more capacitors connected to a connection point between the first stage diode and the next stage diode. A clock supply means for supplying a clock to the capacitor, the two or more capacitors connected in series to a connection point of the diode when the clock is at L level, and the two or more capacitors when the clock is at H level. Switch means for switching so as to be connected in parallel to the connection point of the diode, and outputting a positive boosted voltage of a voltage step smaller than the power supply voltage from the diode of the final stage. Charge pump circuit. 3. A plurality of diodes connected in series, a voltage source for supplying a power supply voltage to the first stage diode,
Two or more first capacitors connected to the connection point between the first-stage diode and the next-stage diode, and one or more second capacitors connected to the connection points of other diodes except the connection point, Clock supply means for alternately supplying a clock of opposite phase to the first capacitor and the second capacitor; and a plurality of first and second capacitors according to the voltage level of the clock supplied to the first capacitor. Switch means for switching the connection state, wherein the switch means connects the two or more capacitors to the connection point between the first-stage diode and the next-stage diode when the clock supplied to the first capacitor is at the L level. Connected in series, and when the clock is at H level, the two or more capacitors are switched to be connected in parallel to the connection point, and the final stage dio The charge pump circuit outputs a positive boosted voltage obtained by adding a voltage step smaller than the power supply voltage to the voltage step of the power supply voltage. 4. The charge pump circuit according to claim 2, further comprising switch control means for controlling the switch means, wherein the switch control means outputs the switch control signal in accordance with a switch control signal output from the switch control means. Two or more capacitors are connected to a connection point between the first-stage diode and the second-stage diode so that they are connected in series at all times or in series or in parallel depending on the level of the clock. A charge pump circuit. 5. The charge pump circuit according to claim 2, further comprising a regulator that adjusts a boosted voltage output from the diode at the final stage. 6. The charge pump circuit according to claim 3, 4, or 5, wherein voltage detection means for detecting a boosted voltage output from the diode at the final stage, and a charge pump circuit according to the detection result. And a charge pump circuit stage number control means for controlling the number of stages of the charge pump circuit. 7. The charge pump circuit according to claim 1, wherein the diode comprises a MOS transistor having a gate and a source commonly connected. circuit. 8. The charge pump circuit according to claim 1, wherein said switch means is M.
A charge pump circuit comprising an OS transistor. 9. A plurality of diodes connected to the first stage diode in series while being supplied with a ground voltage; two or more capacitors connected to a connection point between the first stage diode and the next stage diode; Clock driver means for supplying a clock to a capacitor, the two or more capacitors are connected in series to a connection point of the diode when the clock is at H level, and the two or more capacitors are connected to the diode when the clock is at L level. Switch means for switching so as to be connected in parallel to the connection point of, and outputting a negative boosted voltage in a voltage step smaller than the power supply voltage supplied from the final stage diode to the clock driver means. A charge pump circuit characterized in that. 10. A plurality of diodes connected to the first stage diode in a ground voltage and connected in series, and two or more first capacitors connected to a connection point between the first stage diode and the next stage diode. And one or more second capacitors connected to the connection points of the diodes other than the connection point, and clock driver means for alternately supplying a clock of opposite phase to the first capacitor and the second capacitor. Switch means for switching connection states of the two or more first capacitors according to a voltage level of a clock supplied to the first capacitor, the switch means being supplied to the first capacitor. When the clock is at H level, the two or more capacitors are connected in series to the connection point between the first-stage diode and the second-stage diode, Switch means for switching the two or more capacitors so that they are connected in parallel to the connection point when the voltage is at the L level. A charge pump circuit that outputs a negative boosted voltage in small voltage steps. 11. The charge pump circuit according to claim 9 or 10, further comprising switch control means for controlling the switch means, wherein the switch control means outputs the switch control signal in accordance with a switch control signal output from the switch control means. Two or more capacitors are connected to a connection point between the first-stage diode and the second-stage diode so that they are connected in series at all times or in series or in parallel depending on the level of the clock. A charge pump circuit. 12. The charge pump circuit according to claim 9, further comprising a regulator that adjusts a boosted voltage output from the diode at the final stage. 13. The charge pump circuit according to claim 9, wherein voltage detection means for detecting a boosted voltage output from the diode at the final stage, and charge according to the detection result. A charge pump circuit comprising: a charge pump circuit stage number control means for controlling the stage number of the pump circuit. 14. The charge pump circuit according to claim 9, wherein the diode is formed of a MOS transistor whose gate and source are commonly connected. 15. The charge pump circuit according to claim 9, 10, 11, 12, or 13, wherein the switch means comprises a MOS transistor.