JP3471913B2 - Computer system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duplicated computer system that sends and receives data to and from a facing computer via an online line.

[0002]

2. Description of the Related Art Conventionally, in an online data communication system, such as a weather information system, which is required to have a high operating rate and high reliability, it is possible to prevent data loss when a failure occurs and restart the operation after the failure occurs at high speed. In order to do so, the dual method is adopted and is configured as shown in FIG.

That is, the computers 100-1 and 100
Any one of -2 communicates with an opposite computer (not shown) via the communication control device 4 and the line 3. A switching device 5 is provided between the communication control device 4 and the line 3,
A main computer (here, 100-1) is selectively connected to the communication control device 5 and can communicate. The computer 100-1 is provided with a transmission process 101-1 and a reception process 102-1. The transmission process 101-1 transmits necessary data to the corresponding computer, and the reception process 102-1 is transmitted from the opposite computer. Receive the data that is sent. When the transmission process 101-1 finishes the transmission process, it passes control to the post-transmission process 105-1. As a result, the post-transmission processing 105-1 post-processes the files in the transmission file 107 related to the transmission. Also,
Upon completion of the reception process, the reception process 102-1 transfers control to the post-reception process 106-1. As a result, the post-reception processing 106-1 determines that the file related to reception is the reception file 1
Post-processing such as accumulation in 08-1 is performed.

In this system, the processing results of the master computer 100-1 and the slave computer 100-2 are equalized so that switching can be performed in the event of a failure so that the master computer 100-1 can switch. To the slave computer 100-2. That is,
After the data transmission by the transmission process 101-1 is completed,
The transmission synchronization transmission processing 103-1 transfers the transmitted data to the transmission synchronization reception processing 103-2 of the computer 100-2. The transmission synchronization reception process 103-2 which receives this,
When the data received above is sent to the post-transmission processing 105-2, the post-transmission processing 105-2 performs post-processing such as accumulating a file related to transmission in the transmission file 107-2. Further, after the reception process 102-1 completes the reception of the data, the reception synchronization transmission process 104 performs the reception process 102-
The data received by No. 1 is sent to the reception synchronization reception process 104-2 of the computer 100-2. The post-reception processing 106 is the reception synchronization reception processing 104-2 from the computer 100.
-1 receives the received data, and performs post-processing such as storing a file related to the reception in the received file 108-2.

As a result of the above operation, the subordinate computer 10
Since 0-2 has the communication result and post-processes similarly to the main system, it seems that the process is independently performed and the input / output is performed.

[0006]

However, in the above computer system, the main computer 100 is used.
In -1, the transmission synchronous transmission processing 103-1 and the reception synchronization transmission processing 103-2 are required to operate, and it is necessary to perform processing to make the main system and the slave system appear to be performing the same process. The main system needs to be equipped. In other words, when the slave system communicates on behalf of the master system, it is assumed that the master system is down, and processing for synchronization is not required, so the programs of the master system and slave system must be different. .

Further, the slave system cannot process data relating to communication unless the master system sends data, which delays the process of the slave system. Further, the master system performs processing for synchronizing the master system and the slave system after completion of reception or after completion of transmission, and even when the master system fails, even if the master system switches to the slave system. As long as the transmission data is not transferred after the transmission is completed, the subordinate system does not know the transmission data, and if it is in the middle of reception, the reception data is not transferred and the reception data in the middle of reception is grasped. It became impossible to do so, and there was a problem that the main system could not start up quickly.

The present invention has been made to solve the problems of the conventional computer system as described above, and an object thereof is to allow a plurality of subordinate computers to operate under the same program and conditions as the main system. It is to provide a computer system. Another object of the present invention is to provide a computer system in which a new master computer can quickly start up when switching between a master system and a slave system.

[0009]

According to a first aspect of the present invention, there is provided a computer system in which one master computer in a plurality of computers, each of which performs data processing, exchanges data with a computer which is opposed via a line. In a computer system for transmitting / receiving, a shared memory device capable of storing data to be transmitted / received by the one master computer, while being able to read the data from the one master computer and another slave computer; With respect to the shared memory device, a pointer used for writing and reading the data transmitted and received by the one master computer, and at the time of starting and restarting, determine whether the own device is the master computer or the slave computer, Based on the determination result, the shared memory device is referred to by referring to the pointer .
It kicking characterized in that it comprises a data processing unit to continue processing that is the untreated relates transmit and receive data.

A computer system according to a second aspect of the present invention is a computer system in which one main computer in a plurality of computers, each of which performs data processing , transmits and receives data to and from the opposite computer via a line. A shared memory device capable of storing the data transmitted and received by the one master computer and reading the data by the one master computer and another slave computer; and the shared memory device,
A transmission buffer write pointer used to write the data to be transmitted by the one main computer, a transmission buffer read pointer used to read the written data for transmission, and a transmission result regarding the transmission completed data. Is stored in its own transmission buffer, and the post-transmission processing pointer used to indicate the part where the post-processing has finished, and at the time of startup and restart, the device determines whether it is the master computer or the slave computer. The shared memory device by referring to the transmission buffer write pointer and the transmission buffer read pointer based on
Both the proceeding have been outstanding relates transmission of data in the transmission and post-transmission processing pointer buffering
Compared with the pointer, the transmission result is
That there is data that has not been post-processed stored in
If detected, refer to post-send processing pointer and share
It is common to execute post-processing on the corresponding data in memory.
And data processing means for updating the post-transmission processing pointer .

In the computer system according to claim 3 of the present application, the post-transmission processing pointer is provided corresponding to each of the primary computer and the secondary computer,
The main system computer and the slave of each computer, it
It is characterized in that the post-processing of storing the transmission result in its own transmission buffer is executed for each data which has been transmitted in the shared memory device independently .

The computer system according to claim 4 of the present application is a computer system in which one main system computer in a plurality of computers, each of which performs data processing , transmits and receives data to and from an opposite computer via a line. A shared memory device capable of storing the data transmitted and received by the one master computer and reading the data by the one master computer and another slave computer; and the shared memory device, The reception buffer write pointer used for writing the data received by the one main computer and the reception result of the received data for its own reception buffer.
The receive buffer post-processing pointer used to indicate the part where the post-processing to be stored in the file is completed, and at the time of start-up and restart, the own device judges whether it is the master computer or the slave computer, and based on the judgment result, Data processing means for continuing an unprocessed process related to the reception of data in the shared memory device with reference to the reception buffer write pointer and the reception buffer post-processing pointer.

In the computer system according to claim 5 of the present application, the reception buffer post-processing pointer is provided corresponding to each of the master computer and the slave computer, and each of the master computer and the slave computer is provided. Each computer uniquely stores the reception result in its own reception buffer for the received data in the shared memory device.
It is characterized in that post-processing is performed.

In a computer system according to a sixth aspect of the present application, each computer is provided with a register indicating whether it is a master system or a slave system and the same data processing means, and the data processing means refers to this register at the time of startup, It is determined whether or not to execute the process of writing data to and reading the data from the shared memory device at the time of transmitting data, and the process of writing the data to the shared memory device at the time of receiving data, and in the case of the main system, execute the process. In the case of a subordinate system, the processing is not executed.

According to a seventh aspect of the present invention, each pointer is provided in the shared memory device.

In the computer system according to claim 8 of the present application, the data processing means writes the data to be transmitted in the shared memory device in accordance with the transmission buffer write pointer in response to the generation of the transmission request, and updates the transmission buffer write pointer. When the transmission request processing means for comparing the transmission buffer write pointer and the transmission buffer read pointer is compared and it is detected that the untransmitted data is in the shared memory device, the data is referred to by the transmission buffer read pointer. A transmission processing unit that reads out and transmits, and updates the transmission buffer read pointer,
If the post-send processing pointer is compared with the send buffer read pointer and it is detected that there is unprocessed data that stores the transmission result in its own send buffer, the post-send processing pointer is referenced. The post-processing for the corresponding data in the shared memory is executed, and the post-transmission processing means for updating the post-transmission processing pointer and the reception data are written to the shared memory device by referring to the reception buffer write pointer. At the same time, the reception processing means for updating the reception buffer write pointer is compared with the reception buffer post-processing pointer and the reception buffer read pointer to store the reception result in its own reception buffer. When it detects "," it refers to the post-processing pointer of the receive buffer and relates to the corresponding data in the shared memory. And executes post-processing, characterized by comprising a reception post-processing means for updating the receive buffer postprocessing pointer.

[0017]

According to a first aspect of the present invention, at the time of starting and restarting, the computer system judges whether the own device is a master computer or a slave computer, and based on the judgment result, the pointer is referred to and data in the shared memory device is referred to. Work to continue the unprocessed process for sending and receiving.

According to a second aspect of the computer system,
At the time of start-up and restart, the device determines whether it is a master computer or a slave computer, and based on the determination result, it refers to the transmission buffer write pointer and the transmission buffer read pointer to transmit data in the shared memory device. Work to continue unprocessed processing.

A computer system according to claim 3 is
The main system computer and the slave of the computer refers to respective transmission aftertreatment pointer, the finished data transmission respectively within its own <br/> shared memory device, feed
Performs post-processing to store the received result in its own send buffer .

A computer system according to a fourth aspect is
At startup and restart, the device determines whether it is a master computer or a slave computer, and based on the determination result, it refers to the receive buffer write pointer and the receive buffer post-processing pointer to receive data from the shared memory device. Work to continue unprocessed processing.

The computer system according to claim 5 is
The main system computer and the slave of each computer, using the received buffers aftertreatment pointer, respectively
It independently executes post-processing for storing the reception result in its own reception buffer for the received data in the shared memory device.

A computer system according to claim 6 is
By referring to the register indicating whether the system is the master system or the slave system, it is determined whether to execute the process of writing data to and reading data from the shared memory device during data transmission, and the process of writing data to the shared memory device during data reception. It is determined that the processing is executed in the case of the master system, and the processing is not executed in the case of the slave system.

A computer system according to claim 7 is
The processing is executed using each pointer provided in the shared memory device.

A computer system according to claim 8 is
When the transmission buffer write pointer and the transmission buffer read pointer are compared and it is detected that there is untransmitted data in the shared memory device, the transmission buffer read pointer is referred to to read and transmit the data, while the transmission Compare the post-processing pointer with the send buffer read pointer and store the send result in its own send buffer.
If it is detected that there is data that has not been post-processed, the post-processing for the corresponding data in the shared memory is executed by referring to the post-transmission processing pointer, and when the reception data arrives, the reception data In the shared memory device by referring to the receive buffer write pointer, updating the receive buffer write pointer, comparing the receive buffer post-processing pointer with the receive buffer read pointer, and receiving
When it detects that there is data that has not been post-processed for storing the received result in its own receive buffer, it refers to the receive buffer post-processing pointer to execute post-processing for the corresponding data in shared memory, and Update the buffer post-processing pointer.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A computer system according to an embodiment of the present invention will be described below with reference to the accompanying drawings and FIGS. In the description of each drawing, the same components are denoted by the same reference numerals and redundant description will be omitted.

In FIG. 1, the computer 1-1 includes a fault detection process 10-1, a transmission process 11-1, and a reception process 12.
-1, transmission request processing 13-1, post-transmission processing 14-1, post-reception processing 15-1, transmission file 16-1, reception file 17-1, register 18-1 storing device number, main system or slave A register 19-1 that stores the system type is provided. The subordinate computer 1-2 also has the same configuration as the computer 1-1. That is, the computer 1-2 has a failure detection process 10-2, a transmission process 11-2, a reception process 12-2, and a transmission request process 13-.
2, post-transmission processing 14-2, post-reception processing 15-2, transmission file 16-2, reception file 17-2, register 18-2 that stores the device number, and a register that stores whether the master system or the slave system 19-2 is provided. Computer 1-
Any one of 1 and 1-2 communicates with an opposite computer (not shown) via the communication control device 4 and the line 3.
A switching device 5 is interposed between the communication control device 4 and the line 3, and a main computer (1-1 in this case) is selectively connected to the communication control device 5 for communication.

In this embodiment, the computers 1-1, 1-
There is provided a shared memory device 6 that both 2 can access. The shared memory device has a transmission buffer 61, a reception buffer 62, a transmission buffer pointer group 63, and a reception buffer pointer group 64. The transmission buffer pointer group 63 includes a transmission buffer write pointer 63-1, a transmission buffer read pointer 63-2, and post-transmission processing read pointers 63-3 and 63-4. The post-transmission processing read pointer 63-3 is a pointer for the computer 1-1, and the post-transmission processing read pointer 63-4 is a pointer for the computer 1-2. Further, the reception buffer pointer group 64 includes a reception buffer write pointer 64.
-1, post-reception processing read pointers 64-2 and 64-3 are included. The post-reception processing read pointer 64-2 is a pointer for the computer 1-1, and the post-reception processing read pointer 64-3 is a pointer for the computer 1-2.

FIG. 2 shows a more practical block diagram of the system of FIG. Computer system 1-
1 is composed mainly of the CPU 20-1,
-1 is the program and data used by the main storage device 21-
It is stored in 1. The main memory 21-1 is provided with registers 18-1 and 19-1.
The data of 1 is written in advance. A bus 22-1 extends from the CPU 20-1 to which the input device 23, the shared memory device 6, the switching device 24, and the communication interface 26-1 are connected. On the other hand, the computer system 1-2 is a CPU
A program and data used by the CPU 20-2 are stored in the main storage device 21-2. This program and data are stored on the computer 1-
It is the same as that of 1. The main memory 21-2 is provided with registers 18-2 and 19-2.
The data of -2 is written in advance. CPU 20-2
From there, a bus 22-2 extends, and the input device 23, the shared memory device 6, and the switching device 24 communication interface 26-2 are connected.

Then, the above two CPUs 20-1 and 20
-2 equally receives data from the input device 23, and for output data, the output of the main system side is selected by the switching device 24 and the switching device 5. CPU 20-1 and C
A failure notification line 27 is provided between the PU 20-2 and the PU 20-2 to notify the failure. Based on this notification and the like, the CPU on the master side writes data indicating that it is the master system in the register 19, and the CPU on the failure side writes data indicating that it is the slave system in the register 19. It will be. Initially, as illustrated, for example, the input device 23
Is used to specify one of the CPUs and the data of the master system and the slave system of 19-2 are written in the register 19-1. In addition, the main storage devices 21-1 and 21-2 respectively have the configuration shown in FIG.
~ Programs corresponding to the flowchart shown in Fig. 11 are stored and executed by the respective programs.

The operation of the computer system according to the embodiment of the present invention will be described below with reference to the flowcharts.
First, when the power of this system is turned on, the program of the flowchart of FIG. 5 is started. So CPU
Takes in the contents of the register 19 of the main memory (3
1) It is detected whether or not it is the main system (32). In the system as shown in FIG. 2, the CPU 20-1 branches to YES and the CPU
20-2 branches to NO. The CPU 20-1 activates the transmission process 11-1, the reception process 12-1, and the transmission request process 13-1 (33), and further activates the post-transmission process 14-1 and the post-reception process 15-1 (34). , A switching request is given to the switching devices 5 and 24 so that they can operate as a main system (3
5). On the other hand, the CPU 20-2 activates post-transmission processing 14-2 and post-reception processing 15-2 (34), and the transmission processing 11-
2, the reception process 12-2 and the transmission request process 13-2 are not activated.

In both computers 1-1 and 1-2, fault detection processing 10-1 and 10-2 shown in FIG. 6 are activated. As a result, the CPU activates the failure detection program and enters failure monitoring (41), and detects whether a failure has occurred (42). If no fault has occurred here, it is detected whether the fault has been notified from the other CPU via the line 27 (43). Here, when the notification has not been given, the process returns to step 41 and the processing is continued.
On the other hand, when notification of failure is given, if necessary,
That is, when the own device is the slave system, it is switched to the master system (44) and automatically restarted. As a result, the flowchart of FIG. 5 is activated, and the subordinate computer operates as the main system. Also, step 4
In 2, when it detects that a failure has occurred in its own device, it notifies the other CPU of the failure occurrence via line 27 (45), and when necessary, that is, when the own device is the main system. For this purpose, the system is switched to the slave system (46), and the system enters the standby state and waits for restart.

After the processing of FIG. 5, the transmission request processing 13-
As shown in FIG. 7, the CPU 20-1 monitors whether a transmission request is generated (51) (1). Then, when a transmission request occurs, the value SWP of the transmission buffer write pointer 63-1 of the shared memory device 6 is fetched (52),
The data of the file to be transmitted is written into the shared memory device according to the value SWP of the transmission buffer write pointer 63-1 (53). This state is the transmission request process 13- of FIG.
It is indicated by an arrow from 1, and as shown in FIG.
Data writing to the transmission buffer 61 starts from the address indicated by WP. When the data for one address is written, the value S of the transmission buffer write pointer 63-1 is written.
The WP is updated to detect whether one file of data has been written (55), and step 5 is performed until the writing is completed.
Steps 3 and 54 are repeated, and when writing is completed, step 5
Return to 1 and continue monitoring. As a result, as shown in FIG. 12B, the value SWP of the transmission buffer write pointer 63-1 is advanced by the address of the written data.

After the processing of FIG. 5, the transmission request processing 11-
As shown in FIG. 8, the CPU 20-1 fetches the value SWP of the transmission buffer write pointer 63-1 and the value SRP of the transmission buffer read pointer 63-2 and compares them with each other (60) to see if there is untransmitted data. Is detected (6
1). In the state of FIG. 12A, the value SWP of the transmission buffer write pointer 63-1 and the transmission buffer read pointer
There is no data to be transmitted because the values SRP of 63-2 match, but when the state of FIG.
Since it is ahead of RP, there is untransmitted data. Then, the CPU 20-1 reads the data in the shared memory device 6 from the position indicated by the value SRP of the transmission buffer read pointer 63-2 as indicated by the arrow in FIG. 3 and transmits it (62). Then, the value SRP of the transmission buffer read pointer 63-2
Is updated every time one address data is read (64),
Whether the transmission is completed or not is determined by the value SWP of the transmission buffer write pointer 63-1 and the value SR of the transmission buffer read pointer 63-2 .
It is detected by coincidence with P (64), and steps 62 and 63 are repeated until the end. When the transmission is completed, the process returns to step 60 and the operation is performed. In this way, FIG.
In the transmission buffer 61, which was in the state of (b), as shown in FIG.
As shown in (c), SWP and SRP match.

After the processing of FIG. 5, the post-transmission processing 14-1
As the CPU 20-1 and C as the post-transmission processing 14-2.
The PU 20-2 fetches the device number from the registers 18-1 and 18-2, respectively, as shown in FIG. 9 (7
1) The post-processing read pointer number is determined (72).
Specifically, it is assumed that the CPU 20-1 fetches the device number “1” from the register 18-1 and the post-processing read pointer 63-3 of the device number “1” is the corresponding pointer. Further, the CPU 20-2 fetches the device number “2” from the register 18-2, and the post-processing read pointer 63-4 of the device number “2” is the corresponding pointer. CPU2
0-1 the CPU 20-2 compares the values AP1 and AP2 of the corresponding post-processing read pointers 63-3 and 63-4 with the value SRP of the transmission buffer read pointer 63-2 (7
3), it is detected whether post-processing has been performed for all data (74). That is, as shown in FIG.
When P1 or AP2 is behind SRP,
Since there is data that has not been post-processed, the post-transmission processes 14-1 and 14-2 indicate the transmission result (date and time) for the data that has not been post-processed in the transmission buffer 61, as indicated by the arrow in FIG. (Successful or unsuccessful, backup) is stored in the transmission files 16-1 and 16-2, the transmission completion is notified to the transmission request processing 13-1, and the like (75), depending on the processed data. The values AP1 and AP2 of the post-processing read pointers 63-3 and 63-4 are updated (76).

As a result of the above post-transmission processing, post-transmission processing 14
If the CPU 20-1 as -1 and the CPU 20-2 similarly post-processes all the transmission data as post-transmission processing 14-2, post-processing read pointers 63-3, 6
The values AP1 and AP2 of 3-4 coincide with the value SRP of the transmission buffer read pointer 63-2 as shown in FIG. 12 (d). Of course, post-transmission processing 14-1, 14
-2 operates independently, so it is possible that one of them will be later.

As described above, the computers 1-1 and 1-2
Since the transmission operation proceeds, the transmission data is stored in the shared memory device 6 before the transmission, and the position of the read / write is clear by the pointer. Therefore, a failure occurs in the main computer 1-1 during the transmission. Even if the subordinate computer 1
-2 indicates each pointer of the transmission buffer pointer group 63 in FIG.
~ By using as shown in the flowchart of Fig. 9, it is possible to quickly continue transmission in place of the main computer 1-1. Further, the main system and the slave system can be configured with the same software, though there is a difference in whether or not there is a process that does not operate, which is economical and efficient.

On the other hand, after the processing of FIG.
As shown in FIG. 10, the CPU 20-1 monitors whether data arrives via the communication control device 4 as -1 (81), and when the data arrives, the value RWP of the reception buffer write pointer 64-1 is set. Capture (82), and write the received data to the receive buffer 62 of the shared memory device 6 as shown in FIG. 4 (83). Then, every time one address is written, the value RWP of the reception buffer write pointer 64-1 is updated (84), and it is detected whether reception is completed (8).
5). Here, when further data is sent, steps 83 and 84 are repeated, and when the data is not sent, the process returns to step 81 and the arrival of data is monitored. As a result of such processing, although the pointer is initially in the state shown in FIG. 13A, after the received data is written, the state shown in FIG. 13 is changed according to the amount of data written by the RWP. The procedure proceeds as shown in (b).

Further, as the post-reception processing 15-1, the CPU 2
0-1 uses the CPU 20-2 as post-reception processing 15-2.
However, as shown in FIG. 11 , the device number is fetched from the registers 18-1 and 18-2, respectively (91), and the post-processing read pointer number is determined (92). Specifically, CP
The U 20-1 fetches the device number “1” from the register 18-1 and post-processes the read pointer 64-of the device number “1”.
Let 2 be the corresponding pointer. In addition, CPU20-
2 fetches the device number “2” from the register 18-2,
It is assumed that the post-processing read pointer 64-4 for the device number “2” is the corresponding pointer. CPU20-1, CPU20
-2 is the corresponding post-processing read pointer 64-2, 64-3
Values BP1 and BP2 and receive buffer read pointer 64
The value RWP of -1 is compared (93), and it is detected whether post-processing has been performed on all data (94). That is, as shown in FIG. 13B, BP1 or BP2 is R
When it is behind the WP, there is data that has not been post-processed, and the CPU 20-1, CP
As indicated by the arrow in FIG. 4, U 20-2 receives the reception result (date and time, whether reception is successful or unsuccessful, processing target data portion, etc.) for the data that has not been subjected to post-processing of the reception buffer 62. -1, 17-2, or the arrival of data is notified to other processing (for example, arithmetic processing on the received file) (95). Further, according to the post-processed data, the post-processing read pointer 6
The values BP1 and BP2 of 4-2 and 64-3 are updated.

As a result of the above post-reception processing, when only the CPU 20-2 post-processes all the received data, the values BP1 and B of the post-processing read pointers 64-2 and 64-3 are obtained.
As for P2, as shown in FIG. 13C, only the value BP2 of the post-processing read pointer 64-3 matches the RWP. Of course, as long as the main computer 1-1 has not failed, the value BP1 of the post-processing read pointer 64-1 after this also matches the RWP by the processing of the CPU 20-1.

As described above, the computers 1-1 and 1-2
Since the receiving operation proceeds, the received data is first stored in the shared memory device 6, and even if a failure occurs in the master computer in the middle of receiving, the slave computer 1-2 can receive each of the receive buffer pointer groups 64. Pointer to Figure 10, Figure 1
It can be used as shown in the flowchart of No. 1 to quickly continue reception in place of the master computer 1-1. That is, the receive buffer write pointer 64-
The value RWP of 1 makes it possible to detect that data has been received up to the previous address, and it is possible to continue receiving data thereafter. Further, the main system and the slave system can be configured with the same software, though there is a difference in whether or not there is a process that does not operate, which is economical and efficient.

In the above embodiments, the system is composed of a total of two computers, one main system and one slave system, but in other embodiments, there are two or more slave systems.
In this way, even if a failure occurs in the subordinate system, it can be backed up.

[0042]

As described above, according to the present invention as set forth in claim 1, at the time of start-up and restart, it is judged whether the device is a main computer or a slave computer, and the pointer is determined based on the judgment result. Refer to the above, it works to continue the unprocessed processing related to the transmission / reception of data in the shared memory device, so that the same software can be used in the master system and the slave system. Etc. can be unified, and an efficient and economical system can be provided.

According to the present invention as defined in claim 2,
At the time of start-up and restart, the device determines whether it is a master computer or a slave computer, and based on the determination result, it refers to the transmission buffer write pointer and the transmission buffer read pointer to transmit data in the shared memory device. Since it works to continue the unprocessed processing, it is possible to take over the transmission processing quickly based on the transmission buffer write pointer and the transmission buffer read pointer even when the main computer fails. , Proper backup is possible.

According to the present invention as defined in claim 3,
The master computer and each slave computer refer to their respective post-transmission processing pointers to independently perform post-processing on the data for which transmission has been completed in the shared memory device, thus affecting the other processing. As a result, the post-transmission processing is not delayed, and it is guaranteed that the slave system is ready to back up the master system.

According to the present invention of claim 4,
At startup and restart, the device determines whether it is a master computer or a slave computer, and receives the data in the shared memory device by referring to the receive buffer write pointer and the receive buffer post-processing pointer based on the determination result. Since the unprocessed process is continued, it is possible to quickly continue the main system reception process based on the reception buffer write pointer even when the main system computer fails.

According to the present invention of claim 5,
Since the master computer and each slave computer individually perform post-processing on the reception-completed data in the shared memory device, using the respective reception buffer post-processing pointers, the other processing is performed. It is guaranteed that the slave system is in a state capable of backing up the master system without being delayed due to the influence of the post-reception processing.

According to the present invention as defined in claim 6,
By referring to the register indicating whether the system is the master system or the slave system, it is determined whether to execute the process of writing data to and reading data from the shared memory device during data transmission, and the process of writing data to the shared memory device during data reception. Judgment, in the case of the master system, the process is executed, and in the case of the slave system, it works so as not to execute the process. Therefore, when the system becomes the master system, the transmission data and the reception data are written to the shared memory device, Based on this, the master system and the slave system perform post-processing, so that the master system and the slave system perform the processing in synchronization with each other and have the same result.

According to the present invention of claim 7,
Since the processing is executed by using each pointer provided in the shared memory device, both the slave system and the master system can refer to the pointers to perform backup or substitution.

According to the present invention as set forth in claim 8,
When the transmission buffer write pointer and the transmission buffer read pointer are compared and it is detected that there is untransmitted data in the shared memory device, the transmission buffer read pointer is referred to to read and transmit the data, while the transmission If the post-processing pointer is compared with the send buffer read pointer and it is detected that there is data that has not been post-processed, the post-processing for the corresponding data in the shared memory is executed with reference to the post-transmission processing pointer. Further, when the reception data arrives, the reception data is written into the shared memory device by referring to the reception buffer write pointer, the reception buffer write pointer is updated, and the reception buffer post-processing pointer is compared with the reception buffer read pointer. When it detects that there is data that has not been post-processed, The post-processing for the corresponding data in the shared memory is executed by referring to the post-processing pointer, and the receive buffer post-processing pointer is updated, so that accurate processing can be executed independently with the master and slave systems. is there.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a computer system according to an embodiment of the present invention.

FIG. 2 is a more practical configuration diagram of a computer system according to an embodiment of the present invention.

FIG. 3 is a functional block diagram when transmission is performed by the computer system according to the embodiment of the present invention.

FIG. 4 is a functional block diagram when a computer system according to an embodiment of the present invention receives the data.

FIG. 5 is a flowchart for explaining the operation of the computer system according to the embodiment of the present invention.

FIG. 6 is a flowchart for explaining the operation of the computer system according to the embodiment of the present invention.

FIG. 7 is a flowchart for explaining the operation of the computer system according to the embodiment of the present invention.

FIG. 8 is a flowchart for explaining the operation of the computer system according to the embodiment of the present invention.

FIG. 9 is a flowchart for explaining the operation of the computer system according to the embodiment of the present invention.

FIG. 10 is a flow chart for explaining the operation of the computer system according to the embodiment of the present invention.

FIG. 11 is a flowchart for explaining the operation of the computer system according to the embodiment of the present invention.

FIG. 12 is a diagram for explaining the movement of the pointer during the transmission operation of the computer system according to the embodiment of the present invention.

FIG. 13 is a diagram for explaining the movement of the pointer during the receiving operation of the computer system according to the embodiment of the present invention.

FIG. 14 is a functional block diagram of a computer system according to a conventional example.

[Explanation of symbols]

1-1 Main computer 1-2 Slave computer 3 Line 4 Communication control device 5 Switching device 6 Shared memory device 11-1, 11-2 Transmission processing 12-1, 1
2-1 Reception processing 13-1, 13-2 Transmission request processing 14-1, 1
4-2 Post-Transmission Processing 15-1, 15-2 Post-Reception Processing 16-1, 1
6-2 Send File 17-1, 17-2 Receive File 61 Send Buffer 62 Receive Buffer 63 Send Buffer Pointer Group 64 Receive Buffer Pointer Group

Continuation of front page (56) Reference JP-A-1-119151 (JP, A) JP-A-4-171539 (JP, A) JP-A-5-225135 (JP, A) JP-A-63-128837 (JP , A) JP-A-4-360242 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 11/16-11/20 G06F 13/00 G06F 15/00 G06F 15/16 -15/177 H04L 29/14 H04L 1/22 JSTPLUS file (JOIS)

Claims (8)

(57) [Claims] 1. A computer system in which one main computer in a plurality of computers, each of which performs data processing , transmits and receives data to and from an opposite computer via a line, wherein the one main computer transmits and receives. And a shared memory device in which the one master computer and another slave computer can read the data, and the one master computer transmits / receives to / from the shared memory device. A pointer used for writing and reading data, and at the time of starting and restarting, determines whether the device is a master computer or a slave computer, and based on the determination result, refers to the pointer and refers to the pointer in the shared memory device. Equipped with data processing means for continuing unprocessed data transmission / reception Computer system according to claim Rukoto. 2. A computer system in which one main computer of a plurality of computers each processing data transmits and receives data to and from a facing computer via a line, wherein the one main computer transmits and receives. A shared memory device in which the one master computer and another slave computer can read the data while storing the data to be stored, and the one master computer transmits the shared memory device to the shared memory device. The transmission buffer write pointer used to write data, the transmission buffer read pointer used to read the written data for transmission , and the transmission result itself for the data that has been transmitted.
The post-transmission processing pointer that is used to indicate the end of post-processing that is stored in the transmission buffer of the device, and whether the device itself is the master computer or the slave computer at startup and restart, and based on the determination result , co If you continue the process that is the untreated relates transmission of data <br/> data in reference to the shared memory device and the transmission buffer write pointer and the transmission buffer read pointer
The post-transmission processing pointer and the transmission buffer read pointer
Stores the transmission result in its own transmission buffer by comparing with
When it detects that there is data that has not been post-processed
Refers to the post-transmission processing pointer,
Perform post-processing related to this data, and post-processing post-transmission
A computer system comprising: a data processing unit that updates a pointer . 3. A post-transmission processing pointer is provided corresponding to the main system computer and the slave of each computer, the main system computer and the slave of the computer, it
Post-processing that stores the transmission result for each completed data in the shared memory device in its own transmission buffer
The computer system according to claim 2, which executes a process. 4. A computer system in which one main computer in a plurality of computers, each of which performs data processing , transmits and receives data to and from an opposing computer via a line, wherein the one main computer transmits and receives. A shared memory device that stores the data to be read by the one master computer and another slave computer, and the one master computer receives the shared memory device from the shared memory device. a reception buffer write pointer used for non-writing data, receiving the received data
Receive buffer post-processing pointer that is used to indicate the end of post-processing that stores the received result in its own receive buffer, and when starting and restarting, determines whether the device is a master computer or a slave computer. And a data processing unit that continues an unprocessed process related to the reception of data in the shared memory device by referring to the reception buffer write pointer and the reception buffer post-processing pointer based on the determination result. And computer system. 5. A reception buffer aftertreatment pointer is provided corresponding to the main system computer and the slave of each computer, the main system computer and the slave of the computer, it
5. The computer system according to claim 4, wherein each computer system independently executes post-processing for storing the reception result in its own reception buffer for the received data in the shared memory device. 6. Each computer is provided with a register indicating whether it is a master system or a slave system and the same data processing means, and the data processing means refers to this register at the time of starting and writes data to the shared memory device at the time of data transmission. Also, it is determined whether or not to execute the data reading process and the data writing process to the shared memory device at the time of receiving the data. In the case of the master system, the process is executed, and in the case of the slave system, the process is executed. The computer system according to any one of claims 1 to 5, wherein the computer system is not executed. 7. The computer system according to claim 1, wherein each pointer is provided in a shared memory device. 8. The data processing means writes the data to be transmitted in the shared memory device according to the transmission buffer write pointer in response to the generation of the transmission request, and updates the transmission buffer write pointer, and the transmission buffer processing means. When the write pointer and the transmission buffer read pointer are compared with each other and it is detected that untransmitted data is in the shared memory device, the transmission buffer read pointer is referred to to read and transmit the data, and the transmission buffer read pointer is read. After storing the transmission result in its own transmission buffer by comparing the transmission processing means for updating the pointer with the post-transmission processing pointer and the transmission buffer read pointer.
When it is detected that there is unprocessed data, the post-transmission processing means refers to the post-transmission processing pointer to perform post-processing on the corresponding data in the shared memory, and also updates the post-transmission processing pointer. When the reception data arrives, the reception data is written in the shared memory device by referring to the reception buffer write pointer, and the reception processing means for updating the reception buffer write pointer, the reception buffer post-processing pointer and the reception buffer read pointer are provided. In comparison, the received result is stored in its own receive buffer.
When it is detected that there is data that has not been post-processed, the post-processing of the corresponding data in the shared memory is executed by referring to the post-processing pointer of the receive buffer, and the post-processing pointer of the receive buffer is updated. 7. The computer system according to claim 6, further comprising post-reception processing means.