JP3471564B2 - Negative differential resistance element logic circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultra-high speed logic circuit constructed by using a negative differential resistance element.

[0002]

2. Description of the Related Art As a conventional negative differential resistance element logic circuit, for example, there is one described in Japanese Patent Application No. 4-351114. 9 to 13 are a circuit diagram and a characteristic diagram of the above conventional example. That is, the circuit shown in FIG. 9 has a series connection of two elements A and X having a negative differential resistance characteristic, a field effect transistor M connected in parallel with X, and M.
, A signal input terminal P connected to the gate, a signal output terminal Q drawn from a connection point U between A and X, a terminal T connected to the ground, a terminal R for supplying a voltage to the circuit, and a terminal R. And a voltage source V _OSC which is inserted between the lower limit V ₁ and the upper limit V ₂ and supplies a voltage V _CK that oscillates with time between the lower limit V ₁ and the upper limit V ₂ to the circuit. As the two elements A and X having the negative differential resistance characteristic, for example, a resonant tunnel diode is used. In addition, the field effect transistor M
For example, a heterojunction FET is used.

Further, FIG. 10A shows an example of the current-voltage characteristic X (IV) of the negative differential resistance element X and the current-voltage characteristic A (IV) of the negative differential resistance element A acting as a load. showed that. In this case, the number of intersections of X (IV) and A (IV) is one, and the circuit is in the monostable state. The lower limit voltage V ₁ of V _CK is set to a value at which this circuit is in a monostable state as shown in FIG.

FIG. 10 (b) shows the current-voltage characteristic X (IV) of the negative differential resistance element X and the current-voltage characteristic A (IV) of the negative differential resistance element A acting as a load. An example is shown. In this case, there are two intersections of X (IV) and A (IV) and the circuit is in a bistable state. The upper limit voltage V ₂ of V _CK is set to a value at which this circuit is in a bistable state as shown in FIG.

To obtain a logical operation in this circuit, the voltage source V
_The input voltage V _IN is supplied to the signal input terminal P when the voltage V _{CK of the OSC} is the voltage V ₁ . Next, the voltage V _{CK of the} voltage source V _OSC
Is increased to voltage V ₂ . At this time, depending on the input signal,
An output voltage V _OUT is obtained at the signal output terminal Q (details will be described later). Further, once the voltage V _CK of the voltage source V _OSC is returned to the voltage V ₁ , the next input signal is supplied to the signal input terminal P, and then the voltage V _CK of the voltage source V _OSC is changed to the voltage V ₂ . When increased, an output voltage V _OUT according to the input signal at that time is obtained. This state is shown in FIG.

Next, the logical operation principle will be described. Figure 11
In (d), the current-voltage characteristic between the connection point U of A and X and the terminal T connected to the ground is shown with the input voltage V _IN to the signal input terminal P as a parameter. The reason why such characteristics are obtained is that the current flowing between U and T is the sum of the current flowing through the element X having the negative differential resistance characteristic and the current flowing through the field effect transistor M connected in parallel with X. This is because the latter increases as the input voltage V _IN to the signal input terminal P increases. As shown in FIG. 11 (d),
Since the peak current value I _P ^X changes depending on the input signal V _IN , the logical operation described below is obtained.

[0007] FIG. 11 (e) has a peak current value I _P ^X which varies in response to the input signal V _IN, and a peak current value I _P ^A of device A having negative differential resistance characteristics, the input voltage V _{Shown as} a function of _IN . In FIG. 11 (e), V _IN ^TH represents the input voltage at the intersection of I _P ^X and I _P ^A. If V _IN <V _IN ^TH , then I _P ^A
> I _P ^X , and V _IN > V _IN ^TH , I _P ^A <I _P ^X.

In FIGS. 12 (a) to 12 (d), V _IN ^L <V
A current-voltage characteristic X of the negative differential resistance element X when an input voltage V _IN ^L satisfying _IN ^TH is input and then the voltage V _CK of the voltage source V _OSC is increased from the voltage V ₁ to the voltage V ₂ . (IV)
And the current-voltage characteristic A (IV) of the negative differential resistance element A acting as a load. The white circle in the figure is the stable point, and the output voltage V _OUT obtained at the signal output terminal Q is
It increases from V _OUT ¹ to V _OUT ² and V _OUT ³ , showing that V _OUT ^H is finally obtained as an output when V _CK = V ₂ . This occurs as a result of the negative differential resistance element X having a small peak current switching from the peak state to the valley state in the process of shifting from FIG. 12 (b) to FIG. 12 (c). As a result, V _OUT ^H which is "high" is obtained at the output terminal Q.

On the other hand, in FIGS. 13A to 13D, an input voltage V _IN ^H satisfying V _IN ^H > V _IN ^TH is input,
After that, the voltage V _CK of the voltage source V _OSC is changed from the voltage V ₁ to the voltage V ₂
9 shows the change between the current-voltage characteristic X (IV) of the negative differential resistance element X and the current-voltage characteristic A (IV) of the negative differential resistance element A acting as a load when increasing to. The white circle in the figure is the stable point, and the output voltage V _OUT obtained at the signal output terminal Q changes from V _OUT ⁴ to V _OUT ⁵ and V _OUT ^6, and when V _CK = V ₂ , V _OUT ^L is the final point. It can be obtained as an output. This occurs as a result of the negative differential resistance element A having a small peak current switching from the peak state to the valley state in the process of shifting from FIG. 13B to FIG. 13C. This results in V _OUT ^L being "low" at the output.

As described above, in the conventional negative differential resistance element logic circuit, the inverter having the threshold value of V _IN ^TH is utilized by utilizing the inversion of the magnitude relation of the peak current accompanying the change of the input voltage. The operation has been realized. V _OUT ^H ＞ V _IN
^{If TH} and V _OUT ^L <V _IN ^TH , even if these logic circuits are connected in multiple stages, the logic operation is normally performed.

[0011]

However, the conventional negative differential resistance element logic circuit has the following problems. In FIG. 14A, similar to FIG. 11E, the peak current value I _P ^{X of the} element X having the negative differential resistance characteristic and the element having the negative differential resistance characteristic, which change depending on the input signal V _IN. The peak current value I _P ^{A of A} is shown as a function of the input voltage V _IN . The difference from FIG. 11 (e) is that in consideration of characteristic fluctuations caused by dimensional variations and the like that occur in the manufacturing process,
In that the representation to have a width delta _P of the value of I _P ^X and I _P ^A.
If there is such a variation, the threshold value of the logical operation is also shown in FIG.
As shown in (a), V _IN ^TH (low) and V _IN ^TH (h
It becomes to be distributed during the period

In such a state, V _OUT ^H > V _IN ^TH (hi
gh) and V _OUT ^L <V _IN ^TH (low) are required.
In other words, in the conventional circuit, the noise margin shown in FIG. 14A is significantly reduced as the characteristics of the elements X and A having the negative differential resistance characteristic change. Since the noise margin is reduced, if V _OUT ^H and V _OUT ^L fluctuate for some reason, V _OUT ^H > V _IN ^TH (high) or V _OUT ^L <V _IN ^TH.
If is not satisfied, the circuit malfunctions.

In order to secure a large noise margin and avoid malfunction of the circuit even when the characteristics of the elements X and A having the negative differential resistance characteristic change, as shown in FIG. 14 (b), The slope of I _P ^X should be steep. This way, V
Distance between _OUT ^H and V _IN ^TH (high), and V _OUT ^L and V
As a result of widening the distance from _IN ^TH and increasing the noise margin, malfunction of the circuit can be avoided. For this purpose, it is necessary to increase the mutual conductance gm of the field effect transistor M connected in parallel with the element X. However, in the logical operation utilizing the reversal of the magnitude relation of the peak current as in the conventional circuit, the large transconductance is large. There was a problem that it was difficult to use.

The reason will be described below. The transconductance gm of the field effect transistor M is a function gm (V _DS ) of the drain-source voltage V _DS . On the other hand, the voltage between the terminals of the element X required to obtain the peak current is V
Assuming _P , the elements M and X are connected in parallel, so the transconductance that determines the change in peak current is gm.
( _VP ). By the way, as shown in FIG. 15C, gm (V _DS ) has a property of increasing as V _DS increases. Normally, V _P is usually set low in order to prevent an increase in power consumption, and V _P is about 0.2V. This value is g
Increasing m (V _P ) is extremely difficult with conventional transistors. As described above, in order to avoid the noise margin reduction, which is a problem in the prior art, it is necessary to devise the circuit configuration and devise the circuit configuration so that the region where the transistor has a large mutual conductance can be used. There is.

The present invention has been made to solve the problems in the prior art as described above, and an object thereof is to provide a negative differential resistance element logic circuit which has a large noise margin and is less likely to malfunction.

[0016]

In order to achieve the above object, the present invention is constructed as described in the claims. Claim 1 corresponds to the embodiment shown in FIG. 1 below, claim 2 corresponds to the embodiment shown in FIG. 8 below, and claim 3 corresponds to the embodiment shown in FIG. 7 below.

The gm (V _DS ) of the field effect transistor is V
Since it has the property of increasing with increasing _DS , in the present invention, the large transconductance gm obtained in the voltage region larger than the voltage V _P between the terminals of the device X necessary to obtain the peak current is used to utilize the device. This is a circuit configuration that can obtain a large noise margin even if there is a characteristic change. Specifically, it is configured to realize a logical operation by utilizing the reversal of the magnitude relation of the valley current accompanying the change of the input voltage. As shown in FIG. 11D, the voltage V _V across the terminals of the element X required to obtain the valley current is larger than V _P , and as shown in FIG. gm
(V _V ) [gm (V _V )> gm (V _P )] can be used.

In the claims, one power supply terminal of the transistor, the other power supply terminal, and the control terminal are
For example, a field effect transistor corresponds to a source terminal, a drain terminal, and a gate terminal, and a bipolar transistor corresponds to an emitter terminal, a collector terminal, and a base terminal.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments will be described below with reference to the drawings. (First Embodiment) FIGS. 1 to 6 are views showing a first embodiment of the present invention, FIG. 1 is a circuit diagram, and FIGS. 2 to 6 are characteristic diagrams. First, in the circuit diagram shown in FIG. 1, a series connection of two elements A and X having a negative differential resistance characteristic and X
A field effect transistor M connected in parallel with the signal input terminal P connected to the gate of M, a signal output terminal Q drawn from a connection point U between A and X, and a terminal T connected to the ground. A terminal K for supplying a constant voltage V _C to the circuit, and a constant voltage V
It is composed of a voltage source V _O for supplying _DD to the circuit and a switch S connected between a connection point U and a terminal K. Resonant tunnel diodes were used as the two elements A and X having negative differential resistance characteristics, and a heterojunction FET was used as the field effect transistor M.

FIG. 2A shows the current-voltage characteristic X (IV) of the negative differential resistance element X and the current-voltage characteristic A (IV) of the negative differential resistance element A acting as a load. X (I
Although there are three intersections of V) and A (IV), the stable points are the two marked with white circles, and the circuit is in a bistable state. The constant voltage V _DD supplied to the circuit by the voltage source V _O is set to a value at which this circuit is in a bistable state as shown in FIG. At this time, the output voltage obtained at the output terminal Q is 2
V _OUT ^L or V _OUT ^H corresponding to one intersection.

To obtain a logical operation in this circuit, the input voltage V is applied to the signal input terminal P with the switch S closed (on).
Supply _IN . Next, when the switch S is turned off, the output voltage V _OUT is obtained at the signal output terminal Q according to the input signal (details will be described later). Furthermore, once the switch S is returned to the closed (on) state and the next input signal is supplied to the signal input terminal P, the switch S is opened again (of).
In the state of f), an output voltage according to the input signal at that time is obtained. The above situation is shown in FIG.

Next, the logical operation principle will be described. Figure 3 (c)
Shows the current-voltage characteristics between the connection point U of A and X and the terminal T connected to the ground, using the input voltage V _IN to the signal input terminal P as a parameter. The reason why such characteristics are obtained is the same as in the conventional circuit, but the current flowing between U and T is the current flowing in the element X having the negative differential resistance characteristic, and the field effect transistor connected in parallel with X. It is the sum of the current flowing through M, and the latter is because it increases as the input voltage V _{IN at the} signal input terminal P increases. Figure 3 (c)
As described above, since the valley current value I _V ^X changes depending on the input signal V _IN , the logical operation described below is obtained.

FIG. 3D shows an element A having a negative differential resistance characteristic and a valley current value I _V ^X which changes according to the input signal V _IN.
The valley current value I _V ^A and the valley current value are shown as a function of the input voltage V _IN . V _IN ^TH represents the input voltage at the intersection of I _V ^X and I _V ^A. V
_IN is a <V _IN ^TH in ^{_{I V A> I V X,}} V IN> V IN TH in I
_V ^A <I _V ^X.

In FIGS. 4A to 4D, a certain input voltage V _IN ^L satisfying V _IN <V _IN ^TH is input, and then the switch S is opened from the closed (on) state. current-voltage characteristic X (IV) of the negative differential resistance element X when it is turned off.
And the current-voltage characteristic A (IV) of the negative differential resistance element A acting as a load.

In FIG. 4A, the switch S is closed (on).
_Shows the state when the input voltage V _IN is 0. In this state, the circuit has a white circle in the figure. The voltage at the connection U is equal to the voltage V _{C at the} terminal K. In this embodiment,
V _C was set to V _DD / 2.

In FIG. 4B, the switch S is closed (on).
_Shows the state when the input voltage V _IN becomes V _IN ^L. Negative differential resistance element X, the difference between the current flowing in ^A (I _V A -
I _V ^X ) flows into K through switch S. From this state, the state in which the switch S is opened (off) is shown in FIG.
It is (c). When the voltage fixation from the terminal K is released,
The voltage at the connection U moves to H, which is the original stable point.
The state where the input voltage V _IN is returned to 0 from this state is shown in FIG.
It is (d). In this way, the output voltage V _OUT obtained at the signal output terminal Q changes from V _DD / 2 to V _OUT ^H ,
It can be taken out to the output terminal Q. This is shown in FIG.
This occurs as a result of the negative differential resistance element A having a large valley current changing from the valley state to the peak state in the process of shifting from (b) to FIG. 4 (c). This results in V _OUT ^H being "high" at the output.

On the other hand, in FIGS. 5A to 5D, V _IN > V
_When a certain input voltage V _IN ^H that satisfies _IN ^TH is input and then the switch S is changed from the closed (on) state to the open (off) state, the current-voltage characteristic X (of the negative differential resistance element X IV)
And the current-voltage characteristic A (IV) of the negative differential resistance element A acting as a load. White circles in the figure are stable points.

In FIG. 5A, the switch S is closed (on).
_Shows the state when the input voltage V _IN is 0. In this state, the circuit has a white circle in the figure. The voltage at the connection U is equal to the voltage V _{C at the} terminal K and is V _DD / 2.

In FIG. 5B, the switch S is closed (on).
_Shows the state when the input voltage V _IN becomes V _IN ^H. The difference between the currents flowing through the elements X and A flows from the terminal K through the switch S. From this state, open the switch S (o
ff) is shown in FIG. 5 (c). When the voltage fixation from the terminal K is released, the voltage of the connection portion U moves to the original stable point L (white circle L in FIG. 5C). The state in which the input voltage V _IN is returned to 0 from this state is shown in FIG.
Is. In this way, the output voltage V _OUT obtained at the signal output terminal Q changes from V _DD / 2 to V _OUT ^L and can be taken out to the output terminal Q. This is shown in FIG.
5C, the device X having a large valley current changes from the valley state to the peak state. This results in V _OUT ^L being "high" at the output.

As described above for the logical operation, in the negative differential resistance element logic circuit according to the present embodiment, the inversion of the magnitude relation of the valley current with the change of the input voltage is utilized to obtain V _IN.
Inverter operation with ^TH as the threshold is realized. V
_{If OUT} ^H > V _IN ^TH and V _OUT ^L <V _IN ^TH , even if these logic circuits are connected in multiple stages, the logical operation is normally performed.

Since the circuit is constructed as described above, the following effects can be obtained. In FIG. 6, FIG.
Similarly to (d), the valley current value I _V ^{X of the} element X having the negative differential resistance characteristic and the valley current value I _V ^{A of the} element A having the negative differential resistance characteristic, which change depending on the input signal V _IN , are set. , Input voltage V
_{Shown as} a function of _IN . The difference from FIG. 3D is that the values of I _V ^X and I _V ^A are expressed with a width ΔV in consideration of manufacturing variations and the like that occur in the manufacturing process. If such a variation occurs, the threshold value of the logic operation also becomes V _IN as shown in FIG.
It comes to be distributed between ^TH (low) and V _IN ^TH (high). In such a state, V _OUT ^H > V _IN ^TH (high
h) and V _OUT ^L <V _IN ^TH (low) are required. In other words, also in the present embodiment, as in the conventional circuit, the noise margin shown in FIG. 6 decreases as the characteristics of the elements X and A having the negative differential resistance characteristic change. Compared with the characteristics (see FIG. 14), the number is significantly smaller.
This is because V _P <V _V , and a large value gm (V _V ) [gm (V _V )> gm (V _P )] is used as the transconductance of the transistor M that determines the modulation degree of I _V ^X. Because you can.

As described above, in the present embodiment, even if the noise margin decreases with the characteristic change of the element, it is much smaller than that of the conventional circuit. Therefore, if V _OUT ^H , Even if V _OUT ^L fluctuates, V _OUT ^H > V _IN ^TH (h
ig) or V _OUT ^L <V _IN ^TH is less likely to be unsatisfied, and the possibility of circuit malfunctions has been dramatically reduced.

(Second Embodiment) FIG. 7 shows a second embodiment of the present invention.
3 is a circuit diagram showing an embodiment of FIG. The circuit of FIG. 7 has two elements A and X having negative differential resistance characteristics connected in series,
A field effect transistor M connected in parallel with X, a signal input terminal P connected to the gate of M, and a connection point U of A and X
A signal output terminal Q drawn from a terminal T connected to ground, inserted between the terminal R and ground, and a voltage source V _O supplied to the circuit a constant voltage V _DD, the from node U Reset terminal K drawn out through the second field effect transistor M _S (supplying a constant voltage V _C to the circuit)
Composed of and.

Two elements A having negative differential resistance characteristics,
A resonant tunneling diode was used as X, and a heterojunction FET was used as field effect transistors M and M _S. In this embodiment, instead of the switch S of the first embodiment, a second field effect transistor M _S is used, and its gate voltage is controlled via its gate terminal P _S , so that this transistor Is used as a switch. Therefore, the circuit operation is the same as that of the first embodiment, and the same effect is obtained.

(Third Embodiment) FIG. 8 shows a third embodiment of the present invention.
3 is a circuit diagram showing an embodiment of FIG. The circuit of FIG. 8 has two elements A and X having a negative differential resistance characteristic connected in series,
A field effect transistor M connected in parallel with X, a signal input terminal P connected to the gate of M, and a connection point U of A and X
A signal output terminal Q drawn from the terminal, a terminal T connected to the ground, and a terminal K for supplying a constant voltage V _C to the circuit.
And a constant voltage V inserted between the terminal R and the ground
It is composed of a voltage source V _O for supplying _DD to the circuit and a switch S connected between a connection point U and a terminal K. Resonant tunnel diodes were used as the two elements A and X having negative differential resistance characteristics, and a heterojunction FET was used as the field effect transistor M. Note that, as in the case of FIG. 7, the second field effect transistor M _S can be used instead of the switch S.

Since the logical operation is the same as that of the first embodiment, detailed description thereof will be omitted. However, in the negative differential resistance element logic circuit according to the present embodiment, reversal of the magnitude relation of the valley current due to the change of the input voltage is reversed. Utilizing this, the buffer operation with the threshold value of V _IN ^TH is realized. That is, when V _IN <V _IN ^TH , V _OUT ^L which is “low” is obtained at the output. Also, V _IN ＞
At V _IN ^TH , V _OUT ^H which is “high” is obtained at the output.

In the above embodiments, the case where a field effect transistor is used as the transistor M _S used in place of the transistor M and the switch S connected in parallel to the negative differential resistance element X has been exemplified.
It is of course possible to use a bipolar transistor.

[0038]

As described above, the present invention takes advantage of the fact that the transconductance gm (V _DS ) of a transistor increases with an increase in V _DS , so that the negative differential resistance element required to obtain a peak current is obtained. It has become possible to take advantage of the larger transconductance gm at voltage V _V, where a larger valley current is obtained than at the voltage V _P across the terminals of X. As a result, the effect that the noise margin can be kept large even if there is a change in the characteristics of the element and a malfunction can be made less likely to occur is obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a negative differential resistance element logic circuit according to the present invention.

FIG. 2 is a characteristic diagram according to the first embodiment.

FIG. 3 is a characteristic diagram according to the first embodiment.

FIG. 4 is a characteristic diagram (for V _IN ^L <V _IN ^TH ) for explaining a logical operation according to the first embodiment.

FIG. 5 is a characteristic diagram (in the case of V _IN ^H > V _IN ^TH ) for explaining the logical operation in the first embodiment.

FIG. 6 is a characteristic diagram for explaining effects in the first embodiment.

FIG. 7 is a circuit diagram showing a second embodiment of a negative differential resistance element logic circuit according to the present invention.

FIG. 8 is a circuit diagram showing a negative differential resistance element logic circuit according to a third embodiment of the invention.

FIG. 9 is a circuit diagram of an example of a conventional negative differential resistance element logic circuit.

10 is a characteristic diagram of the conventional example of FIG.

11 is a characteristic diagram of the conventional example of FIG.

FIG. 12 is a characteristic diagram (when V _IN ^L <V _IN ^TH ) for explaining a logical operation in a conventional example.

FIG. 13 is a characteristic diagram (in the case of V _IN ^H > V _IN ^TH ) for explaining the logical operation in the conventional example.

FIG. 14 is a characteristic diagram for explaining problems of the conventional example.

FIG. 15 is a characteristic diagram for explaining problems of the conventional example.

[Explanation of symbols]

A, X ... negative differential resistance element M, M _S ... field effect transistor P ... signal input terminal Q ... signal output terminal T ... ground terminal K ... reset terminal P _S ... gate terminal V of the second field effect transistor M _{S O} ... Voltage source S ... Switch V _OSC ... Voltage source R ... Connection point between voltage source and negative differential resistance element U ... Connection point between negative differential resistance element A and X

─────────────────────────────────────────────────── --- Continuation of front page (56) Reference JP-A-6-177402 (JP, A) JP-A-10-276082 (JP, A) JP-A-10-112647 (JP, A) JP-A-9- 321610 (JP, A) Maezawa K .; et al. , "Flexible and reduced-complexity logistic circuits imitated with resort nans et al. Resonant tunnel logic gate using bistable transfer, IEICE Technical Report MW92-116, Japan, January 1993, Vol. 92, No. 418, pp 1-8 (58) Fields investigated (Int.Cl. ⁷ , DB name) H03K 19/10

Claims (3)

(57) [Claims] 1. A first electrode is connected to a first constant voltage power supply, and a second electrode is a first electrode of a second negative differential resistance element, one power supply terminal of a transistor, an output terminal, and A first negative differential resistance element connected to a first terminal of the switch; a first electrode being a second electrode of the first negative differential resistance element; one power supply terminal of the transistor; A second terminal connected to the first terminal of the switch and a second terminal
Second negative differential resistance element whose electrode is connected to the ground terminal and the other power supply terminal of the transistor, and one power supply terminal is the second electrode of the first negative differential resistance element, and the second First negative electrode of the negative differential resistance element, the output terminal, and the first terminal of the switch, and the other power source terminal is the second electrode of the second negative differential resistance element and the ground. A transistor having a control terminal connected to an input terminal, a first terminal having a second electrode of the first negative differential resistance element and a first electrode of the second negative differential resistance element; A negative differential resistance element logic, comprising: an electrode, a switch connected to the one power supply terminal of the transistor, and the output terminal, and a second terminal connected to a second constant voltage power supply. circuit. 2. A first electrode is connected to a first constant voltage power supply and one power supply terminal of a transistor, and a second electrode is the first electrode of a second negative differential resistance element, and the other of the transistors. A first negative differential resistance element connected to the power supply terminal, the output terminal, and the first terminal of the switch, the first electrode being the second electrode of the first negative differential resistance element, and the output A second negative differential resistance element connected to a terminal and a first terminal of the switch, and a second electrode connected to a ground terminal; and one power supply terminal of the first constant voltage power supply and the first constant voltage power supply. 1
Connected to the first electrode of the negative differential resistance element, the other power supply terminal is the second electrode of the first negative differential resistance element, the first electrode of the second negative differential resistance element, A transistor connected to the output terminal and the first terminal of the switch and having a control terminal connected to the input terminal; a first terminal of the second electrode of the first negative differential resistance element; A switch connected to the first electrode of the negative differential resistance element of No. 2, the other power supply terminal of the transistor, and the output terminal, and the second terminal of which is connected to the second constant-voltage power supply. A negative differential resistance element logic circuit characterized by the above. 3. A second transistor is used as the switch, one power supply terminal of the second transistor is used as the first terminal of the switch, and the other power supply terminal of the second transistor is used as the second power supply terminal of the switch. 3. The negative differential resistance element logic circuit according to claim 1, wherein the second differential transistor control terminal is a terminal, and the control terminal of the second transistor is a switch control terminal.