JPH10336017A - Negative differential resistance element logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logic circuit which has a large noise margin and hardly malfunctions. SOLUTION: A negative differential resistance element logic circuit is composed of a serially connected circuit of two elements A and X having negative differential resistance characteristics, a field effect transistor M connected in parallel with the element X, a signal input terminal P connected to the gate of the transistor M, a signal output terminal Q led out from the node U between the elements A and X, a grounding terminal T, a terminal K which supplies a constant voltage VC to the logic circuit, a voltage source VO which is connected between the terminal R and the ground and supplies another constant voltage VDD to the logic circuit, and a switch S connected between the node U and terminal K. This logic circuit can realize logical operations by utilizing the inversion of the magnitudinous relation of a valley current caused by the fluctuation of an input voltage. Since the voltage VV across the terminals of the element X required for obtaining the valley current is higher than VP (a voltage across the terminals of the element X required for obtaining a peak current), a large mutual conductance gm(VV) of the field effect transistor M can be utilized and the noise margin can be increased by operating the transistor M with a large mutual conductance gm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultra-high-speed logic circuit using a negative differential resistance element.

[0002]

2. Description of the Related Art As a conventional negative differential resistance element logic circuit, for example, there is one described in Japanese Patent Application No. 4-351114. 9 to 13 are a circuit diagram and a characteristic diagram of the conventional example. That is, the circuit shown in FIG. 9 includes a series connection of two elements A and X having negative differential resistance characteristics, a field effect transistor M connected in parallel with X,
A signal input terminal P connected to the gate of the A, a signal output terminal Q drawn from a connection point U between A and X, a terminal T connected to the ground, a terminal R for supplying a voltage to the circuit, and a terminal R And a voltage source V _OSC for supplying a circuit with a voltage V _CK that oscillates with time between a lower limit V ₁ and an upper limit V ₂ . As the two elements A and X having negative differential resistance characteristics, for example, a resonant tunnel diode is used. The field effect transistor M
For example, a heterojunction FET is used.

FIG. 10A shows an example of a current-voltage characteristic X (IV) of a negative differential resistance element X and a current-voltage characteristic A (IV) of a negative differential resistance element A acting as a load. showed that. In this case, there is one intersection between X (IV) and A (IV), and the circuit is in a monostable state. Lower limit voltage V ₁ of the V _CK is set to a value that the circuit is a monostable state as shown in Figure 10 (a).

FIG. 10B shows the current-voltage characteristic X (IV) of the negative differential resistance element X and the current-voltage characteristic A (IV) of the negative differential resistance element A acting as a load. An example was shown. In this case, there are two intersections between X (IV) and A (IV), and the circuit is in a bistable state. Upper limit voltage V ₂ of V _CK is set to a value that the circuit becomes bistable state as shown in Figure 10 (b).

To obtain a logical operation in this circuit, a voltage source V
_The input voltage V _IN is supplied to the signal input terminal P when the voltage V _{CK of the OSC} is the voltage V ₁ . Next, the voltage V _{CK of the} voltage source V _OSC
The increase to the voltage V _2. At this time, according to the input signal,
An output voltage V _OUT is obtained at the signal output terminal Q (details will be described later). Further, once the voltage V _CK of the voltage source V _OSC is returned to the voltage V ₁ , the next input signal is supplied to the signal input terminal P, and then the voltage V _CK of the voltage source V _OSC is changed to the voltage V ₂ again. When it increases, an output voltage V _OUT corresponding to the input signal at that time is obtained. This state is shown in FIG.

Next, the logical operation principle will be described. FIG.
(D) shows the current-voltage characteristics between the connection point U between A and X and the terminal T connected to the ground, using the input voltage V _IN to the signal input terminal P as a parameter. The reason that such characteristics are obtained is that the current flowing between U and T is the sum of the current flowing through the element X having the negative differential resistance characteristic and the current flowing through the field effect transistor M connected in parallel with X. This is because the latter increases when the input voltage V _IN to the signal input terminal P increases. As shown in FIG.
For peak current value I _P ^X is varied by the input signal V _IN, the logical operation is obtained as described below.

[0007] FIG. 11 (e) has a peak current value I _P ^X which varies in response to the input signal V _IN, and a peak current value I _P ^A of device A having negative differential resistance characteristics, the input voltage V _{Shown as} a function of _IN . In FIG. 11 (e), V _IN ^TH indicates the input voltage of the intersection of the I _P ^X and I _P ^A. V _IN <V _IN ^TH in I _P ^A
> An I _P ^X, is the ^{_{V IN> V IN TH I P}} A <I P X.

FIGS. 12A to 12D show that V _IN ^L <V
_When the input voltage V _IN ^L that satisfies _IN ^TH is input, and then the voltage V _CK of the voltage source V _OSC is increased from the voltage V ₁ to the voltage V ₂ , the current-voltage characteristic X of the negative differential resistance element X (IV)
And a change in the current-voltage characteristic A (IV) of the negative differential resistance element A acting as a load. The white circle in the figure is a stable point, and the output voltage V _OUT obtained at the signal output terminal Q is
From V _OUT ¹ , V _OUT ² and V _OUT ³ increase, indicating that when V _CK = V ₂ , V _OUT ^H is finally obtained as an output. This occurs as a result of the negative differential resistance element X having a small peak current switching from the peak state to the valley state in the process of shifting from FIG. 12B to FIG. 12C. As a result, V _OUT ^H that is “high” is obtained at the output terminal Q.

[0009] In contrast, in FIG. 13 (a) (d) receives the input voltage V _IN ^H which satisfies V _IN ^H> V _IN ^TH,
Thereafter, the voltage V _CK of the voltage source V _OSC is changed from the voltage V ₁ to the voltage V _2.
The graph shows changes in the current-voltage characteristic X (IV) of the negative differential resistance element X and the current-voltage characteristic A (IV) of the negative differential resistance element A acting as a load when the current is increased. The white circle in the figure is a stable point, and the output voltage V _OUT obtained at the signal output terminal Q changes from V _OUT ⁴ to V _OUT ⁵ and V _OUT ^6, and when V _CK = V ₂ , V _OUT ^L is final Is obtained as an output. This occurs as a result of the negative differential resistance element A having a small peak current switching from the peak state to the valley state in the process of shifting from FIG. 13B to FIG. 13C. As a result, V _OUT ^L which is “low” is obtained at the output.

As described above, the conventional negative differential resistance element logic circuit utilizes the reversal of the magnitude relationship of the peak current caused by the change in the input voltage, and uses the inverter having V _IN ^TH as the threshold value. Operation has been realized. V _OUT ^H > V _IN
^{If TH} and V _OUT ^L <V _IN ^TH , the logic operation is performed normally even if these logic circuits are connected in multiple stages.

[0011]

However, the conventional negative differential resistance element logic circuit has the following problems. The FIG. 14 (a), the same as FIG. 11 (e), the changes due to the input signal V _IN, and the peak current value I _P ^X of the element X with negative differential resistance characteristics, elements having negative differential resistance characteristics the peak current value I _P ^a of a, shown as a function of the input voltage V _iN. 11E is different from FIG. 11E in consideration of the characteristic variation caused by the dimensional variation and the like occurring in the manufacturing process.
In that the representation to have a width delta _P of the value of I _P ^X and I _P ^A.
With such a change, the threshold value of the logical operation is also reduced as shown in FIG.
As shown in (a), V _IN ^TH (low) and V _IN ^TH (h
i)).

In such a state, when a logic circuit is connected in multiple stages, a normal logic operation requires V _OUT ^H > V _IN ^TH (hi
gh) and V _OUT ^L <V _IN ^TH (low).
In other words, in the conventional circuit, the noise margin shown in FIG. 14A is significantly reduced due to the characteristic fluctuation of the elements X and A having the negative differential resistance characteristics. Then, since the noise margin is reduced, V _OUT ^H and V _OUT ^{L further} fluctuate for some reason, and V _OUT ^H > V _IN ^TH (high) or V _OUT ^L <V _IN ^TH
Is not satisfied, the circuit will malfunction.

In order to secure a large noise margin and avoid malfunction of the circuit even when the elements X and A having the negative differential resistance characteristics fluctuate, as shown in FIG. the slope of the I _P ^X may be suddenly. This way, V
The interval between _OUT ^H and V _IN ^TH (high), and V _OUT ^L and V
As a result, the interval from _IN ^TH is increased and the noise margin is increased, so that malfunction of the circuit can be avoided. For this purpose, it is necessary to increase the transconductance gm of the field effect transistor M connected in parallel with the element X. However, as in a conventional circuit, in a logic operation utilizing the reversal of the magnitude relationship of the peak current, a large transconductance is used. There is a problem that it is difficult to use the Internet.

The reason will be described below. The transconductance gm of the field-effect transistor M is a function gm (V _DS ) of the voltage V _DS between the drain and the source. On the other hand, the voltage between the terminals of element X required to obtain the peak current is V
Assuming that _P is the element M and X are connected in parallel, the mutual conductance that determines the change in peak current is gm
(V _P ). By the way, as shown in FIG. 15C, gm (V _DS ) has a property of increasing as V _DS increases. Usually, V _P to prevent increase in power consumption is usually set lower, on the order V _P = 0.2V. G
It is extremely difficult to increase m (V _P ) with a conventional transistor. As described above, in order to avoid the reduction in noise margin, which is a problem in the conventional technology, it is necessary to devise a circuit configuration so that a transistor can use a region having a large transconductance. There is.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems in the prior art as described above, and it is an object of the present invention to provide a negative differential resistance element logic circuit having a large noise margin and being less likely to malfunction.

[0016]

In order to achieve the above object, the present invention is configured as described in the appended claims. It should be noted that claim 1 corresponds to, for example, an embodiment shown in FIG. 1 described later, claim 2 corresponds to, for example, an embodiment shown in FIG. 8 described later, and claim 3 corresponds to, for example, an embodiment shown in FIG.

The gm (V _DS ) of the field effect transistor is V
Because it has the property of increasing with increasing _DS, the present invention utilizes a large mutual conductance gm obtained in larger voltage range than the voltage V _P between the elements X required terminals to obtain the peak current, the element This realizes a circuit configuration that can provide a large noise margin even if there is a characteristic variation. Specifically, the configuration is such that a logical operation is realized by utilizing the reversal of the magnitude relationship of the valley currents due to the change in the input voltage. As shown in FIG. 11D, the voltage V _V between the terminals of the element X required to obtain the valley current is larger than V _P , and therefore, as shown in FIG. gm
(V _V ) [gm (V _V )> gm (V _P )] can be used.

In the claims, one power supply terminal, the other power supply terminal, and the control terminal of the transistor are defined as:
For example, a field effect transistor corresponds to a source terminal, a drain terminal, and a gate terminal, and a bipolar transistor corresponds to an emitter terminal, a collector terminal, and a base terminal.

[0019]

Embodiments will be described below with reference to the drawings. (First Embodiment) FIGS. 1 to 6 show a first embodiment of the present invention. FIG. 1 is a circuit diagram, and FIGS. 2 to 6 are characteristic diagrams. First, in the circuit diagram shown in FIG. 1, a series connection of two elements A and X having negative differential resistance characteristics,
A field-effect transistor M connected in parallel with the signal input terminal P connected to the gate of M, a signal output terminal Q drawn from a connection point U between A and X, and a terminal T connected to the ground. A constant voltage V is inserted between a terminal K for supplying a constant voltage V _C to the circuit and a terminal R and the ground.
It comprises a voltage source V _O for supplying _DD to the circuit, and a switch S connected between the connection point U and the terminal K. Resonant tunnel diodes were used as the two elements A and X having negative differential resistance characteristics, and a heterojunction FET was used as the field effect transistor M.

FIG. 2A shows a current-voltage characteristic X (IV) of the negative differential resistance element X and a current-voltage characteristic A (IV) of the negative differential resistance element A acting as a load. X (I
Although there are three intersections between V) and A (IV), the stable points are two of them with white circles, and the circuit is in a bistable state. The constant voltage V _DD supplied to the circuit by the voltage source V _O is set to a value at which the circuit enters a bistable state as shown in FIG. At this time, the output voltage obtained at the output terminal Q is 2
V _OUT ^L or V _OUT ^H corresponding to the two intersections.

To obtain a logical operation with this circuit, the input voltage V is applied to the signal input terminal P with the switch S closed (on).
Supply _IN . Next, when the switch S is opened (off), an output voltage V _OUT is obtained at the signal output terminal Q according to the input signal (details will be described later). Further, once the switch S is returned to the closed (on) state and the next input signal is supplied to the signal input terminal P, the switch S is then opened again (of
When in the state of f), an output voltage corresponding to the input signal at that time is obtained. The above situation is shown in FIG.

Next, the logical operation principle will be described. FIG. 3 (c)
Shows the current-voltage characteristics between the connection point U between A and X and the terminal T connected to the ground, using the input voltage V _IN to the signal input terminal P as a parameter. The reason why such a characteristic is obtained is the same as that of the conventional circuit. However, the current flowing between U and T is different from the current flowing through the element X having the negative differential resistance characteristic and the field effect transistor connected in parallel with X. M is the sum of the current flowing through M and the latter because the input voltage V _IN increases at the signal input terminal P. FIG. 3 (c)
As shown in, for valley current value I _V ^X is varied by the input signal V _IN, the logical operation is obtained as described below.

[0023] FIG. 3 (d), a valley current value I _V ^X which varies with the input signal V _IN, device A having negative differential resistance characteristics
A valley current value I _V ^A of, shown as a function of the input voltage V _IN. V _IN ^TH indicates the input voltage of the intersection of the I _V ^X and I _V ^A. V
_IN is a <V _IN ^TH in ^{_{I V A> I V X,}} V IN> V IN TH in I
_V ^A <I _V ^X.

4 (a) to 4 (d) show that a certain input voltage V _IN ^L that satisfies V _IN <V _IN ^TH is input, and then the switch S is opened from the closed (on) state. off), the current-voltage characteristic X (IV) of the negative differential resistance element X
And a change in the current-voltage characteristic A (IV) of the negative differential resistance element A acting as a load.

FIG. 4A shows that the switch S is closed (on).
_Shows a state when the input voltage V _IN is 0. In this state, the circuit is in a state indicated by a white circle in the figure. The voltage at the connection U is equal to the voltage V _{C at the} terminal K. In the present embodiment,
V _C was set to V _DD / 2.

FIG. 4B shows that the switch S is closed (on).
_Shows a state when the input voltage V _IN becomes V _IN ^L. The difference between the currents flowing through the negative differential resistance elements X and A ( _IV ^A −
I _V ^X ) flows into K through switch S. FIG. 4 shows a state in which the switch S is opened (off) from this state.
(C). When the voltage fixation from terminal K is released,
The voltage at the connection U moves to H, which is the original stable point.
FIG. 4 shows a state in which the input voltage _VIN is returned to 0 from this state.
(D). Thus, the output voltage V _OUT obtained at the signal output terminal Q changes from V _DD / 2 to V _OUT ^H ,
It can be taken out to the output terminal Q. This is illustrated in FIG.
In the process of shifting from (b) to FIG. 4 (c), the negative differential resistance element A having a large valley current changes from the valley state to the peak state. As a result, V _OUT ^H which is “high” at the output is obtained.

On the other hand, FIGS. 5A to 5D show that V _IN > V
Satisfies _IN ^TH, enter a certain input voltage V _IN ^H, then opens the switch S from a closed (on) when the state of the (off), the negative differential resistance element X of the current-voltage characteristic X ( IV)
And a change in the current-voltage characteristic A (IV) of the negative differential resistance element A acting as a load. The white circles in the figure are the stable points.

FIG. 5A shows that the switch S is closed (on).
_Shows a state when the input voltage V _IN is 0. In this state, the circuit is in a state indicated by a white circle in the figure. The voltage at the connection portion U is equal to the voltage V _{C at the} terminal K, that is, V _DD / 2.

FIG. 5B shows that the switch S is closed (on).
In, showing a state in which the input voltage V _IN becomes V _IN ^H. The difference between the currents flowing through the elements X and A flows from the terminal K through the switch S. From this state, the switch S is opened (o
ff) is shown in FIG. When the voltage fixation from the terminal K is released, the voltage of the connection portion U moves to the point L (the white circle L in FIG. 5C) which is the original stable point. FIG. 5D shows a state in which the input voltage _VIN is returned to 0 from this state.
It is. In this way, the output voltage V _OUT obtained at the signal output terminal Q changes from V _DD / 2 to V _OUT ^L and can be taken out to the output terminal Q. This is shown in FIG.
5 (c), the element X having a large valley current changes from the valley state to the peak state. As a result, V _OUT ^L which is “high” at the output is obtained.

As described above, the logic circuit of the negative differential resistance element according to the present embodiment utilizes the reversal of the magnitude relation of the valley currents due to the change in the input voltage, and uses the voltage V _IN
Inverter operation using ^TH as a threshold is realized. V
_{If OUT} ^H > V _IN ^TH and V _OUT ^L <V _IN ^TH , the logic operation is performed normally even if these logic circuits are connected in multiple stages.

With the circuit configured as described above, the following effects were obtained. FIG. 6 shows FIG.
Similarly to (d), the valley current value I _V ^{X of the} element X having the negative differential resistance characteristic and the valley current value I _V ^{A of the} element A having the negative differential resistance characteristic, which change according to the input signal V _IN , are calculated. , Input voltage V
_{Shown as} a function of _IN . The difference from FIG. 3 (d), in that in consideration of manufacturing variations or the like generated during the manufacturing process and represented to have a width ΔV of the value of the I _V ^X and I _V ^A. With such a change, the threshold value of the logic operation also becomes V _IN as shown in FIG.
^It is distributed between ^TH (low) and V _IN ^TH (high). In such a state, the normal logic operation when the logic circuits are connected in multiple stages includes V _OUT ^H > V _IN ^TH (high
h) and V _OUT ^L <V _IN ^TH (low). In other words, in the present embodiment, similarly to the conventional circuit, the noise margin shown in FIG. 6 decreases with the characteristic fluctuation of the elements X and A having the negative differential resistance characteristics. (See FIG. 14).
The reason for this is <a V _V, a large value gm (V _V) [gm _(V V) as the transconductance of the transistor M which determines the modulation degree of ^{_{I V X> V P gm (}} V P) ] is utilized This is because it can be done.

[0032] In the embodiments thus present, even the noise margin decreases with change in characteristics of the device, it is so much smaller as compared with the conventional circuit, if V _OUT ^H further for some reason, Even if V _OUT ^L fluctuates, V _OUT ^H > V _IN ^TH (h
i) or the possibility that V _OUT ^L <V _IN ^TH is no longer satisfied, and the possibility that the circuit malfunctions is drastically reduced.

(Second Embodiment) FIG. 7 shows a second embodiment of the present invention.
FIG. 3 is a circuit diagram showing an embodiment of the present invention. The circuit of FIG. 7 includes a series connection of two elements A and X having negative differential resistance characteristics,
A field effect transistor M connected in parallel with X, a signal input terminal P connected to the gate of M, and a connection point U between A and X
A terminal T connected to the ground, a terminal T connected to the ground, a voltage source V _O that supplies a constant voltage V _DD to the circuit, A reset terminal K (supplied to the circuit with a constant voltage V _C ) drawn through the second field-effect transistor M _S
It is composed of

Two elements A having a negative differential resistance characteristic,
The X, resonant tunneling diodes, also, the field effect transistors M and M _S, using a heterojunction FET. In this embodiment, a second field-effect transistor M _S is used instead of the switch S of the first embodiment, and the gate voltage is controlled via the gate terminal P _S , so that this transistor S Is used as a switch. Therefore, the circuit operation is the same as that of the first embodiment, and the same effect is obtained.

(Third Embodiment) FIG. 8 shows a third embodiment of the present invention.
FIG. 3 is a circuit diagram showing an embodiment of the present invention. The circuit of FIG. 8 includes a series connection of two elements A and X having negative differential resistance characteristics,
A field effect transistor M connected in parallel with X, a signal input terminal P connected to the gate of M, and a connection point U between A and X
, A terminal T connected to the ground, and a terminal K for supplying a constant voltage V _C to the circuit.
And a constant voltage V inserted between the terminal R and the ground.
It comprises a voltage source V _O for supplying _DD to the circuit, and a switch S connected between the connection point U and the terminal K. Resonant tunnel diodes were used as the two elements A and X having negative differential resistance characteristics, and a heterojunction FET was used as the field effect transistor M. Note that, similarly to FIG. 7, the second field-effect transistor M _S can be used instead of the switch S.

Since the logical operation is the same as that of the first embodiment, detailed description is omitted. However, in the negative differential resistance element logic circuit according to the present embodiment, the reversal of the magnitude relation of the valley current due to the change of the input voltage is performed. Utilizing this, a buffer operation using V _IN ^TH as a threshold is realized. That is, when V _IN <V _IN ^TH , V _OUT ^L which is “low” in the output is obtained. Also, V _IN >
At V _IN ^TH , V _OUT ^H which is “high” is obtained at the output.

In the above embodiments, the case where a field effect transistor is used as the transistor M _S used in place of the transistor M and the switch S connected in parallel to the negative differential resistance element X has been described.
Of course, it is also possible to use a bipolar transistor.

[0038]

As described above, the present invention takes advantage of the fact that the transconductance gm (V _DS ) of a transistor increases with an increase in V _DS , and uses the negative differential resistance element necessary for obtaining a peak current. It has become possible to use a larger transconductance gm at a voltage V _{V at which a} valley current larger than the voltage V _P between the terminals of X is obtained. As a result, even if the characteristics of the element fluctuate, the noise margin can be kept large, and the effect that a malfunction is less likely to occur can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a negative differential resistance element logic circuit according to the present invention.

FIG. 2 is a characteristic diagram according to the first embodiment.

FIG. 3 is a characteristic diagram according to the first embodiment.

FIG. 4 is a characteristic diagram for explaining a logical operation in the first embodiment (when V _IN ^L <V _IN ^TH );

[5] characteristic diagram for describing the logical operation of the first embodiment (in the case of _{^{V IN H> V IN TH)}} .

FIG. 6 is a characteristic diagram for explaining effects in the first embodiment.

FIG. 7 is a circuit diagram showing a negative differential resistance element logic circuit according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram showing a negative differential resistance element logic circuit according to a third embodiment of the present invention.

FIG. 9 is a circuit diagram of an example of a conventional negative differential resistance element logic circuit.

FIG. 10 is a characteristic diagram in the conventional example of FIG. 9;

FIG. 11 is a characteristic diagram in the conventional example of FIG. 9;

FIG. 12 is a characteristic diagram for explaining a logical operation in a conventional example (when V _IN ^L <V _IN ^TH ).

FIG. 13 is a characteristic diagram for explaining a logical operation in a conventional example (when V _IN ^H > V _IN ^TH ).

FIG. 14 is a characteristic diagram for explaining a problem of the conventional example.

FIG. 15 is a characteristic diagram for explaining a problem of the conventional example.

[Explanation of symbols]

A, X ... negative differential resistance element M, M _S ... field effect transistor P ... signal input terminal Q ... signal output terminal T ... ground terminal K ... reset terminal P _S ... gate terminal V of the second field effect transistor M _{S O} : Voltage source S: Switch V _OSC : Voltage source R: Connection point between voltage source and negative differential resistance element U: Connection point between negative differential resistance elements A and X

Claims (3)

[Claims] A first electrode connected to a first constant voltage power supply, a second electrode connected to a first electrode of the second negative differential resistance element, one power supply terminal of the transistor, an output terminal, and A first negative differential resistance element connected to a first terminal of the switch, a first electrode being a second electrode of the first negative differential resistance element, one power supply terminal of the transistor, and the output A second terminal connected to a first terminal of the switch;
A second negative differential resistance element whose electrode is connected to a ground terminal and the other power supply terminal of the transistor; one power supply terminal is a second electrode of the first negative differential resistance element; Connected to the first electrode of the negative differential resistance element, the output terminal, and the first terminal of the switch, and the other power supply terminal is connected to the second electrode of the second negative differential resistance element and the ground. A transistor having a control terminal connected to an input terminal, a first terminal connected to a second electrode of the first negative differential resistance element, and a first terminal connected to a first electrode of the second negative differential resistance element; A switch connected to the electrode, one power supply terminal of the transistor, and the output terminal, and a second terminal connected to a second constant voltage power supply. circuit. A first electrode connected to the first constant voltage power supply and one power supply terminal of the transistor, a second electrode connected to the first electrode of the second negative differential resistance element, and the other of the transistor; A first negative differential resistance element connected to a power supply terminal, an output terminal, and a first terminal of the switch; a first electrode being a second electrode of the first negative differential resistance element; A second negative differential resistance element connected to a first terminal of the switch and a first terminal of the switch, and a second electrode connected to a ground terminal; and one power supply terminal is connected to the first constant voltage power supply and the second constant voltage power supply. 1
, The other power supply terminal is connected to a second electrode of the first negative differential resistance element, a first electrode of the second negative differential resistance element, A transistor connected to the output terminal and a first terminal of the switch, and a control terminal connected to the input terminal; a first terminal connected to a second electrode of the first negative differential resistance element; A second electrode connected to a first electrode of the negative differential resistance element, the other power supply terminal of the transistor, and the output terminal, and a second terminal connected to a second constant voltage power supply. A negative differential resistance element logic circuit, characterized in that: 3. A second transistor is used as the switch, one power supply terminal of the second transistor is used as a first terminal of the switch, and the other power supply terminal of the second transistor is used as a second power supply terminal of the switch. 3. The negative differential resistance element logic circuit according to claim 1, wherein the terminal is a terminal, and the control terminal of the second transistor is a control terminal of a switch.