JP3470420B2 - Output circuit having a binarization circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit having a binarization circuit, and more particularly to an output circuit having a binarization circuit suitable for use as an output circuit of a CCD linear sensor or the like applied to a bar code reader. Regarding

[0002]

2. Description of the Related Art In a bar code reader using a CCD linear sensor, the output of a CCD linear sensor for optically reading a bar code is supplied to a binarizing circuit to combine lines with different thicknesses (bar code). Is extracted as binarized information, and this binarized information is detected as bar code information. In this binarization process, a method of obtaining binarized information by comparing the signal level of the image pickup signal with a predetermined threshold voltage by a comparator is generally adopted.

During the binarization process, the relative level difference between the image pickup signal and the threshold voltage is caused by the unevenness of the medium surface on which the bar code is printed, the difference in reflectance, or the influence of external light. Therefore, if the threshold voltage is fixed, stable binarization processing cannot be performed. For this reason, in the conventional bar code reading apparatus, a circuit for inverting the comparator when the signal level changes by a certain absolute value or more from the immediately preceding image pickup signal is formed outside the chip of the CCD linear sensor and used. .

A conventional example of a CCD linear sensor and a binarization circuit applied to a bar code reader will be described with reference to FIG. In FIG. 11, a CCD linear sensor 100 includes a sensor array 102 in which a large number of light receiving portions 101 for converting incident light into signal charges having a charge amount corresponding to the light amount and accumulating the signal charges are arranged in a line, and the sensor array 10.
2 has a configuration including a charge transfer register 104 formed of a CCD that transfers the signal charge read from each of the light receiving units 101 via the read gate 103 in one direction.

At the final stage of the charge transfer register 104, there is formed a charge-voltage conversion section 105 which detects the transferred signal charges and converts them into a voltage, for example, a floating diffusion. A buffer circuit 106 that current-amplifies the output of the charge-voltage converter 105 is provided in the subsequent stage of the charge-voltage converter 105. The buffer circuit 106 includes a sensor array 102 and a read gate 103.
And the charge transfer register 104 are formed on the same substrate (chip). The output of the buffer circuit 106 is led out as a CCD output (imaging signal) via the external terminal 107, level-amplified by the amplifier 108, and then supplied to the binarization circuit 109.

As the binarization circuit 109, a floating binarization circuit using a diode is used. The floating binarization circuit 109 includes a comparator 110 and diodes 111 and 112 that are connected in parallel between the two input terminals of the comparator 110 and have opposite polarities. The configuration is such that the comparator 110 is inverted when the signal level changes by a value or more. That is, the output of the binarization circuit 109 is inverted when the signal level of the current image pickup signal changes by ± 0.7 V (the voltage drop level of the diode) or more from the signal level of the previous image pickup signal.

[0007]

This floating binarization circuit 1
The feature of 09 is that the change in the signal is captured and binarization is performed, so that the relative brightness and darkness such as a bar code can be stably binarized without being affected by the reflectance of the bar code printed surface. However, on the other hand, since it is necessary to use an amplifier having a high amplification degree as the amplifier 108 for noise suppression, the circuit configuration becomes complicated and the circuit required for binarization is provided on the same chip as the CCD linear sensor 100. However, it was difficult to fabricate it, that is, to make it on-chip, because the circuit configuration was complicated.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an output circuit which enables on-chip circuits required for binarization and peripheral circuits thereof. It is in.

[0009]

An output circuit according to the present invention is an output circuit which has a source follower circuit and outputs an analog signal based on a predetermined input signal. The analog signal is converted into a binarized signal. Binarization circuit and this 2
A bias voltage generating circuit that generates a bias voltage corresponding to the optimum operating point potential of the binarizing circuit, a comparator that compares the analog signal with the bias voltage, and a load side transistor of the source follower circuit that smoothes the comparison output of this comparator. And a smoothing circuit for applying to the control electrode.

[0010]

In the output circuit having the above construction, the comparator compares the analog signal with the bias voltage, and the smoothing circuit smooths the comparison output and returns it to the control electrode of the load side transistor of the source follower circuit. Here, if the analog signal is higher in potential than the bias voltage, the output potential of the source follower circuit is lowered by the comparison output,
The level of the analog signal decreases and the average level approaches the bias voltage. On the contrary, if the analog signal is lower in potential than the bias voltage, the output potential of the source follower circuit rises due to the comparison output, and the level of the analog signal rises. That is, the comparator and the smoothing circuit form a feedback loop that controls so that the average level of the analog signal becomes the optimum operating point potential of the binarization circuit.

[0011]

Embodiments of the present invention applied to an output circuit of a CCD linear sensor, for example, will be described in detail below with reference to the drawings. The present invention is not limited to the application to the output circuit of the CCD linear sensor, but can be applied to all the output circuits of the CCD including the area sensor and the delay element, and not only the CCD but also a single MOS circuit. Is.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, the charge-voltage converter 1 is composed of, for example, a floating diffusion, and has a CC
It is provided as the final stage of the charge transfer unit (not shown) of the D linear sensor and detects the signal charge transferred by the charge transfer unit and converts it into a voltage. The output voltage of the charge-voltage converter 1 is applied to the buffer circuit 2 corresponding to the buffer circuit 106 of FIG. 11 as the input voltage Vin. The buffer circuit 2 includes, for example, first-stage and second-stage source follower circuits 21 and 22, a sample / hold circuit 23 that samples / holds the output voltage of the source-follower circuit, and a two-stage that sequentially inverts the sample / hold output. Inverters 24, 25
And a source follower circuit 26 in the third stage.

In the above buffer circuit 2, the first stage,
Second-stage and third-stage source follower circuits 21, 22, 26
Is a drive-side N-channel MOS transistor Q1, Q3, Q10 whose drain is connected to the power supply Vdd, and a load-side N-channel whose drain is connected to the sources of these MOS transistors Q1, Q3, Q10 and whose source is grounded. A bias voltage Vg is applied to each gate of the N-channel MOS transistors Q2 and Q11 on the load side of the first and third stages, which are composed of MOS transistors Q2, Q4 and Q11.
g is applied.

The input / output characteristics of the source follower circuits 21, 22, 26 are shown in FIG. This input / output characteristic is the load side MO
The bias voltage Vgg of each gate of the S transistors Q2, Q4, Q11 is set to V1, V2, V3 (V1 <V2 <V3).
It shows that the characteristic curve changes by changing to. As is clear from this input / output characteristic, in the source follower circuits 21, 22, 26, when the input voltage is constant, the output voltage decreases when the bias voltage Vgg increases.

In the sample / hold circuit 23, the drain is connected to the output end of the source follower circuit 22 in the second stage, and the sampling pulse ΦS / H is applied to the gate N.
Channel MOS transistor Q5 and capacitor C connected between the source of this MOS transistor Q5 and ground
It is composed of 0 and 0. The first stage inverter 24 is
A P-channel MOS transistor Q6 whose source is connected to the power supply Vdd and whose gate and drain are commonly connected, and N-channel MOS transistor Q7 whose drain is connected to the gate / drain common connection point of this MOS transistor Q6 and whose source is grounded Consists of N channel MO
The input voltage is applied to the gate of the S transistor Q7 N
It has a ch drive type inverter configuration. The input / output characteristics of the first stage inverter 24 are shown in FIG.

The second-stage inverter 25 has a power source V
The P-channel MOS transistor Q8 has a P-channel MOS transistor Q8 whose source is connected to dd, and an N-channel MOS transistor Q9 whose gate and drain are commonly connected to the drain of the MOS transistor Q8 and whose source is grounded. It has a Pch drive type inverter configuration in which an input voltage is applied to.
The input / output characteristics of the second-stage inverter 25 are shown in FIG.

The output voltage Vaout of the buffer circuit 2 is
The analog output Aout is directly output to the outside via the output terminal 3, and is supplied to the binarization circuit 4 and the comparator 5. As shown in FIG. 6, the binarization circuit 4 includes, for example, three-stage CMOS digital inverters 41,
42 and 43, the analog output voltage Vaout is binarized by using Vdd / 2 as a threshold voltage to obtain a binarized output Vdout. This CMOS
The input / output characteristics of the three stages of digital inverter are shown in FIG. As is clear from this input / output characteristic, if the operating point of the input voltage changes due to variations in the characteristics of the device, normal binarization will not be possible.

The comparator 5 has an analog output Vaou.
t is a non-inverting input (+), the bias voltage Vb generated by the bias voltage generating circuit 6 is an inverting input (-), and both inputs are compared to obtain a comparison result of "H" level or "L" level. obtain. A specific circuit example is shown in FIG. In this circuit example, a differential circuit 51 including differential pair MOS transistors Q21 and Q22 whose sources are commonly connected, and a constant current source MOS transistor Q23 connected between the source common connection point and ground; Against MO
The drain side of the S transistors Q21 and Q22 and the power supply Vd
MOS transistors Q24 and Q2 connected between
5, a current mirror circuit 52, an output MOS transistor Q26 and a constant current source MOS transistor Q27 which are connected in series between the power supply Vdd and the ground.

In the comparator 5 having the above structure, a bias voltage Vgg of about 1 V to 1.5 V is applied to the gates of the constant current source MOS transistors Q23 and Q27. Further, the differential pair MOS transistors Q21, Q
One of the gates 22 has an inverting input Vin−, the other gate has a non-inverting input Vin +, and the bias voltage Vb is applied as the inverting input Vin− and the analog output Vaout is applied as the non-inverting input Vin +.
Aout is compared with the bias voltage Vb to obtain a comparison result of "H" level or "L" level.

On the other hand, the bias voltage generating circuit 6 is for generating the bias voltage Vb corresponding to the central value of the operating point of the binarizing circuit 4 (= the optimum operating point potential of the binarizing circuit 4). For example, a circuit configuration equivalent to that of the binarization circuit 4, that is, an oscillating circuit 61 constituted by three stages of CMOS digital inverters, a resistor R1 connected between input and output ends of the oscillating circuit 61, and an oscillating circuit The capacitor C1 is connected between the input terminal of 61 and the ground. In this circuit configuration, the resistor R1 and the capacitor C1 perform a smoothing action, and thus generate a bias voltage Vb of almost direct current in a steady state. The bias voltage Vb has the same circuit configuration as the binarization circuit 4 shown in FIG. 7 as the oscillation circuit 61, and therefore has a value corresponding to the optimum operating point potential of the binarization circuit 4.

The bias voltage generating circuit 6 is as follows.
Although not limited to the above circuit configuration, the digital inverter needs to have an odd number of stages in order to configure the oscillation circuit 61. Further, in the present embodiment, the oscillation circuit 61 has the same circuit configuration as the binarization circuit 4, but
It is not limited to this. However, the binarization circuit 4
With a circuit configuration equivalent to, there is an advantage that the bias voltage Vb corresponding to the optimum operating point potential of the binarization circuit 4 can be easily set.

The comparison output of the comparator 5 is supplied to a smoothing circuit 7 including, for example, a resistor R2 and a capacitor C2. The smoothing circuit 7 smoothes the comparison output of the comparator 5 into a substantially DC voltage, and the DC voltage is, for example, the second-stage source follower circuit 2 in the buffer circuit 2.
2 is applied to the gate (control electrode) of the load side MOS transistor Q4. As described above, a feedback loop for controlling the average value of the analog signal train in the buffer circuit 2 so as to come to the optimum operating point potential (bias voltage Vb) of the binarization circuit 4 provided by the bias voltage generation circuit 6 is configured. It will be.

In the present embodiment, the configuration is such that the source follower circuit 22 in the second stage is fed back, but the present invention is not limited to this, and it is also possible to employ a configuration in which it is fed back to another stage. The comparator 5, the bias voltage generation circuit 6, the smoothing circuit 7, and the binarization circuit 4 which form this feedback system are formed on the same chip as the CCD linear sensor together with the buffer circuit 2 which is an analog part (on-chip. Be converted). In this case, the capacitor C1 of the bias voltage generating circuit 6 and the capacitor C2 of the smoothing circuit 7 can be made on-chip, but they can be externally attached.

Next, the circuit operation of the feedback system having the above configuration will be described. First, the comparator 5 compares the analog output Vaout with the bias voltage Vb,
When the analog output Vaout is higher than the bias voltage Vb, the “H” level is output, and when the analog output Vaout is lower than the bias voltage Vb, the “L” level is output as the comparison result. This “H” or “L” level comparison output is smoothed by the time constant circuit 7 and is used as a feedback voltage Vfb of a substantially DC voltage in the load side MOS of the second stage source follower circuit 22 in the buffer circuit 2.
It is fed back to the gate of the transistor Q4.

Here, if the overall analog output Vao
If ut is higher in potential than the bias voltage Vb, the output of the comparator 5 becomes the “H” level, and therefore the feedback voltage Vfb to the source follower circuit 22 in the second stage is increased.
Will be higher. That is, the second source follower circuit 2
The gate voltage (bias voltage Vgg) of the MOS transistor Q4 on the load side of No. 2 becomes high, and as is apparent from the input / output characteristics of FIG.
Output potential decreases. Then, since the output voltage similarly decreases with the total characteristic of the buffer circuit 2, the analog output Vaout decreases, and the average level of the analog signal train is the optimum operating point potential of the binarizing circuit 4, that is, the bias voltage generating circuit. The bias voltage Vb given by 6 is approached.

On the contrary, if the analog output Vaout is lower in potential than the bias voltage Vb as a whole, the output of the comparator 5 becomes "L" level, so that the feedback voltage Vfb to the source follower circuit 22 in the second stage is set. Will be lower. Then, the output potential of the second-stage source follower circuit 22 rises, and the output voltage also rises due to the total characteristics of the buffer circuit 2, so that the potential of the analog output Vaout rises.

FIG. 9 shows the total input / output characteristics of the buffer circuit 2 when the feedback voltage Vfb is used as a parameter. This input / output characteristic is the feedback voltage Vf.
b is Vfb1, Vfb2, Vfb3 (Vfb1 <Vfb
It is shown that the characteristic curve changes by changing 2 <Vfb3). As is clear from this input / output characteristic, in the buffer circuit 2, when the input voltage is constant and the feedback voltage Vfb increases, the analog output Va
It can be seen that when the potential of out decreases and the feedback voltage Vfb decreases, the potential of the analog output Vaout increases.

In this way, the feedback system operates so that the average level of the analog output Vaout becomes the optimum operating point potential (bias voltage Vb) of the binarization circuit 4,
In the stable state of the system, the waveform is as shown in FIG. 10, and the normal binarized output Vdout is obtained. That is, MO
Even if there are variations in characteristics between devices due to variations in the threshold voltage Vth of the S-transistor or changes in characteristics due to temperature changes or power supply variations, normalization can be performed by the feedback system. Become.

Further, since the structure for applying feedback is resistant to noise, it is not necessary to use an amplifier having a high amplification degree as a countermeasure against noise as in the conventional case, and it has been conventionally difficult. The binarization circuit 4 and its peripheral circuits (feedback system) can be realized on-chip. As a result, it is possible to reduce the external circuit and the power consumption.

Further, the time constant of the smoothing circuit 7 (= R2 ×
By changing C2), the responsiveness of this feedback system can be changed, so that the average value at the level of several tens of pixels is binarized or one line (for example, 2
It is possible to control the range in which the average value of the binarization is taken, such as performing the binarization on the average value at about (000 pixel level).

In the above embodiment, the case where the binarization circuit 4 is composed of three stages of simple CMOS inverters has been described, but the present invention is not limited to this.
Of course, other circuit configurations having equivalent functions may be used. However, the simple circuit configuration as shown in FIG. 6 is also a condition for easily realizing on-chip implementation.

[0032]

As described above, according to the present invention,
A feedback loop is configured to compare the analog output with the bias voltage set corresponding to the optimum operating point potential of the binarization circuit, smooth the comparison result, and return it to the control electrode of the load side transistor of the source follower circuit. Therefore, since it is resistant to noise, it is not necessary to use an amplifier with a high amplification degree as a countermeasure against noise as in the past.
The binarization circuit and its peripheral circuits, which have been conventionally difficult, can be realized on-chip. Further, the on-chip implementation makes it possible to reduce external circuits and power consumption.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is an input / output characteristic diagram of a source follower circuit.

FIG. 3 is an input / output characteristic diagram of an Nch drive type inverter.

FIG. 4 is an input / output characteristic diagram of a Pch drive type inverter.

FIG. 5 is an input / output characteristic diagram of the entire buffer circuit.

FIG. 6 is a circuit diagram showing an example of a binarization circuit.

FIG. 7 is an input / output characteristic diagram of the binarization circuit.

FIG. 8 is a circuit diagram showing an example of a comparator.

FIG. 9 is an input / output characteristic diagram of the buffer circuit when the feedback voltage Vfb is used as a parameter.

10 is a waveform diagram of each part of FIG.

FIG. 11 is a configuration diagram showing a conventional example.

[Explanation of symbols]

1 Charge-voltage converter 2 buffer circuits 4 Binarization circuit 5 comparator 6 Bias voltage generator 7 Smoothing circuit

Claims (4)

(57) [Claims] 1. An output circuit having a source follower circuit for outputting an analog signal based on a predetermined input signal, the binarization circuit converting the analog signal into a binarized signal, and the binarization circuit. A bias voltage generation circuit that generates a bias voltage corresponding to the optimum operating point potential of the circuit, a comparator that compares the analog signal with the bias voltage, and a load side of the source follower circuit by smoothing a comparison output of the comparator. An output circuit comprising: a smoothing circuit for applying to a control electrode of a transistor. 2. The binarization circuit comprises a plurality of stages of digital inverters.
The output circuit described. 3. The bias voltage generating circuit comprises an oscillating circuit composed of odd-numbered stages of digital inverters, and a circuit for connecting the input and output ends of the oscillating circuit for smoothing. The output circuit according to claim 1. 4. The output circuit according to claim 3, wherein the oscillation circuit has a circuit configuration equivalent to that of the binarization circuit.