JP3469733B2 - Display device drive control method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive control method for a display device such as a plasma display which can display only lighting and non-lighting, and whose gradation is controlled by lighting time.

[0002]

2. Description of the Related Art Plasma display panels (hereinafter referred to as P
In a display device such as a DP (plasma display panel) capable of displaying only lighting and non-lighting, gradation is controlled by controlling lighting time within one field.

For example, in an AC type PDP, when 256 gradations are realized by 8-bit video data, one field is 128: 64: 32: 16: 8:
It is divided into eight subfields having a light emission period of 4: 2: 1. Each subfield includes a writing period (address period) and a light emitting period (display period).
In the writing period, wall charges are initially formed in the discharge cells to be displayed on the entire screen. In the light emission period, the sustaining pulse is applied simultaneously to the entire screen. As a result, discharge is continuously generated only in the discharge cells in which the wall charges have been formed. A drive control method for a PDP in which the number of subfields in one field corresponds to the number of bits of data and the ratio of the light emitting period of each subfield is sequentially doubled (or 1/2 times). We will call it the normal subfield method.

By the way, when a moving image is displayed, subframes are separately recognized at a portion where gradation changes,
There is a phenomenon that becomes a pseudo contour. In this pseudo contour phenomenon, a pseudo contour having different color and brightness is generated in a portion where the gradation changes smoothly, so that the image quality is remarkably deteriorated.

Therefore, the light emitting period of the subfield corresponding to the most significant bit is divided into two, and the ratio of the light emitting period in each subfield is 64: 64: 64: 32: 16 :.
It is conceivable that the subfields are set to 8: 4: 2: 1 and rearranged so that the emission order of the two divided subfields is not continuous. However, this would increase the number of subfields. As the number of subfields increases,
Since the image quality of the PDP may be deteriorated (the contrast may be deteriorated and the high definition may be deteriorated), it is not preferable that the number of subfields is increased.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a drive control method for a display device which can prevent the generation of pseudo contours and can reduce the number of subfields.

[0007]

According to the drive control method for a display device of the present invention, the first step of performing error diffusion processing of at least two systems in which the obtained bit numbers are different from each other is performed on the video data. The number of subfields is set to a number corresponding to the largest number of bits in the error diffusion processing of each system, and 1 of the light emitting period of the subfield corresponding to at least the most significant bit of data having the number of bits is set.
The ratio of all the light emitting periods in the field is made smaller than the ratio of the light emitting period of the subfield corresponding to the most significant bit in the normal subfield method to the data of the number of bits to all the light emitting periods in one field, And the second step of arranging the subfields within one field so that the subfield corresponding to the most significant bit and the subfield corresponding to the bit one lower than the most significant bit are not continuous, and the gradation of the video data It is characterized by comprising a third step in which the output of the error diffusion processing of each system is switched and selected according to the level and the drive processing of each subfield is performed based on the selected output.

In the first step, for example, the error diffusion process of the system is performed on the video data so as to perform the error diffusion process of two systems in which the number of obtained bits is m bits and (m-1) bits. In the second step, for example, when the number of subfields in one field is m, 1 of the light emitting period of the subfield corresponding to the most significant bit of the data of m bits is set.
The ratio to the total light emitting period in the field is 1 of the light emitting period of the subfield corresponding to the most significant bit in the normal subfield method for m-bit data.
The sub-field within one field should be smaller than the ratio of all the light emitting periods in the field, and the sub-field corresponding to the most significant bit and the sub-field corresponding to one bit below the most significant bit should not be continuous. Arrange the fields. In the third step, for example, for video data having a predetermined gradation or less, the output of the error diffusion processing that obtains m-bit data is selected from the error diffusion processing of two systems, and the predetermined gradation is selected. For video data having a larger gradation or less, the output of the error diffusion processing that obtains (m-1) -bit data is selected, and the drive processing of each subfield is performed based on the selected output.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

[1] Description of Basic Embodiment

FIG. 1 shows the configuration of a drive control circuit for a PDP.

The inverse gamma correction circuit 1 performs inverse gamma correction processing on the RGB video signal. That is, in the television transmission system, γ correction is performed in advance on the sending side so that the emission brightness of the CRT changes linearly. Since the display device is a PDP instead of a CRT, the inverse gamma correction circuit 1 returns the video signal after the γ correction sent from the sending side to the video signal before the γ correction. Here, it is assumed that an AC PDP is used.

The output of the inverse gamma correction circuit 1 is converted by the A / D converter 2 into a digital signal of 8 bits for each of RGB. Each 8-bit signal obtained by the A / D converter 2 is gradation-corrected by the gradation correction circuit 3. As will be described later, in this embodiment, the data converted into 5 bits by the error diffusion process is used for the data of the gradation below a certain gradation, and the data for the gradation larger than the certain gradation is used. On the other hand, data converted into 4 bits by the error diffusion process is used.

Therefore, when the gradation correction circuit 3 does not perform the gradation correction, the signal level after the inverse gamma correction and the brightness level of the PDP change linearly, as shown by the polygonal line a in FIG. Will not do. Therefore, the tone correction circuit 3 changes the signal level after the inverse gamma correction and the brightness level of the PDP so that they change linearly as indicated by a straight line b in FIG. To correct the gradation.

The output of the gradation correction circuit 3 is sent to the pseudo gradation circuit 4. The pseudo gradation circuit 4 includes a first error diffusion processing unit 41 (5-bit output processing unit) and a second error diffusion processing unit (4-bit output processing unit) 42. The first error diffusion processing section 41 performs an error diffusion processing to reduce the input 8-bit data to 5-bit data. The second error diffusion processing unit 42 performs an error diffusion processing to reduce the input 8-bit data to 4-bit data. Details of the error diffusion processing will be described later.

The outputs of the error diffusion processing units 41 and 42 are sent to the selection circuit 5. The selection circuit 5 uses the error diffusion processing unit 4 for each data according to a predetermined rule.
One of the outputs of 1 and 42 is selected and sent to the conversion circuit 6. That is, the most significant bit of 5-bit data is "0"
In the case of, the 5-bit data is selected, and when the most significant bit of the 5-bit data is "1", the 4-bit data is selected.

Therefore, for the video data (00000000 to 01111111) for the gradation numbers 0 to 127, 5-bit data is selected as shown in Table 1. In this example, the 5-bit data selected by the selection circuit 5 is from "00000" to "5" as shown in Table 1.
There are 16 types up to 01111 ". Also, the number of gradations is 12
Video data for 8 to 255 (10000000 to 1
11111111), 4-bit data is selected as shown in Table 1. In this example, as shown in Table 1, the 4-bit data selected by the selection circuit 5 is of eight types from "1000" to "1111".

[0018]

[Table 1]

The conversion circuit 6 generates 5-bit data for any data according to a predetermined conversion rule. In this example, as shown in Table 1, when 5-bit data is input, the conversion circuit 6 outputs the input 5-bit data as it is. When 4-bit data is input, the conversion circuit 6 adds the most significant bit representing “1” to the input 4-bit data and outputs it.

The output of the conversion circuit 6 is sent to the signal processing circuit 7. The signal processing circuit 7, as shown in FIG.
In order that the ratio of the light emitting period of each subfield in one field in 8 is 8: 8: 4: 2: 1 and the two subfields of the light emitting period “8” are not continuous,
Control PDP8. That is, the subfields corresponding to 8: 8: 4: 2: 1 are S1, S2, S3, S4, S5.
Then, the PDP 8 is controlled so that the subfields are arranged in the order of S2, S3, S1, S4, and S5.

Note that S1 is 5 output from the conversion circuit 6.
Corresponds to the most significant bit of bit data, S2 corresponds to the second bit from the most significant bit, S3 corresponds to the third bit from the most significant bit, and S4 corresponds to the fourth bit from the most significant bit. However, S5 corresponds to the least significant bit. In FIG. 3, α indicates a writing period and β indicates a light emitting period. Further, the signal processing circuit 7 controls the PDP 8 to perform writing / light emission control of the corresponding subfield for each bit of the transmitted data.

The error diffusion method used in the pseudo gradation circuit 4 will be described. The error diffusion method is a method used to increase the number of display colors in the first place.
It is a liquid crystal panel that can display only 12 colors, and is used to simulate full-color (for example, 262,000 colors or more). "P13 of Nikkei Electronics 1994.8.22 (no.615)
1-142).

FIG. 4 shows an example of an error diffusion processing procedure by the first error diffusion processing section 41. Further, FIG. 5 schematically shows the content of error diffusion processing by the first error diffusion processing unit 41.

Further, E of the frame n in FIG. 6 represents input data for the pixel to be processed. B in frame n
Represents the error signal in the frame obtained as a result of the error diffusion processing of the input data for the pixel on the left of the pixel to be processed. C of the frame n represents an in-frame error signal obtained as a result of the error diffusion processing of the input data E for the pixel to be processed. In addition, the frame (n-
A of 1) represents an inter-frame error signal obtained as a result of the error diffusion processing of the input data for the pixel having the same coordinates as the processing target pixel in the frame (n-1). Further, D of the frame (n + 1) represents an inter-frame error signal obtained as a result of the error diffusion processing of the input data for the processing target pixel.

The error diffusion processing by the first error diffusion processing section 41 will be described with reference to FIGS. 4 to 6.

When the image data (E: 8 bits) for the pixel to be processed in frame n is input, the in-frame error data (B: 2 bits) from the pixel adjacent to the left is added to the image data (E). (Step 1).

Then, the lower 2 bits of the obtained 8-bit data are extracted as error data (C) in the frame distributed to the pixel to the right of the pixel to be processed (step 2).

The upper 6 bits of the 8-bit data obtained in step 1 (interframe processing data)
, The inter-frame error data (A: 1) from the pixel of the same coordinates as the current processing target pixel in the previous frame (n-1).
Bits) are added (step 3).

Of the obtained 6-bit data, the upper 5 bits are output as the display data (G) for the pixel to be processed this time, and the lower 1 bit is the same as the pixel to be processed this time in the next frame (n + 1). It is extracted as inter-frame error data (D) distributed to the pixel of the coordinate (step 4).

That is, the 8-bit input data (E) is
It is output as 5-bit display data (G). Originally, with 5 bits, only 32 gradations can be expressed, but since 5 bits of display data are obtained from 8-bit data by error diffusion processing, 256 gradations are pseudo-represented by this 5 bits of display data. It

As shown in FIG. 7, an error diffusion processing method using only intraframe error data may be used. In this case, when the image data (E: 8 bits) for the pixel to be processed in the frame n is input, the intra-frame error data (B: 3 bits) from the pixel adjacent to the left of the image data (E) is input. Is added. Then, the upper 5 bits of the obtained 8-bit data are output as the display data (G) for the pixel to be processed this time, and
The lower 3 bits are extracted as error data (C) in the frame distributed to the pixel to the right of the pixel to be processed next.

The error diffusion processing by the second error diffusion processing section 42 will be described with reference to FIGS. 8 and 9.

When the image data (E: 8 bits) for the pixel to be processed in frame n is input, the in-frame error data (B: 3 bits) from the pixel adjacent to the left of the image data (E) is added. (Step 11).

Then, the lower 3 bits of the obtained 8-bit data are extracted as error data (C) in the frame distributed to the pixel on the right of the pixel to be processed (step 12).

The upper 5 bits of the 8-bit data obtained in step 11 (interframe processing data)
, The inter-frame error data (A: 1) from the pixel of the same coordinates as the current processing target pixel in the previous frame (n-1).
Bits) are added (step 13).

Of the obtained 5-bit data, the upper 4 bits are output as the display data (G) for the pixel to be processed this time, and the lower 1 bit is the same as the pixel to be processed this time in the next frame (n + 1). It is extracted as inter-frame error data (D) distributed to the pixel of the coordinate (step 14).

The second error diffusion processing section 42 may also use the error diffusion processing method using only the intra-frame error data.

Now, assume that the PDP 8 is driven by a normal subfield method based on only 5-bit data obtained by error diffusion processing for 8-bit video data. In the normal subfield method, FIG.
As shown in, each subfield S in one field
The ratio of the light emitting periods of 1, S2, S3, S4, and S5 is 16:
It is set to 8: 4: 2: 1. The value of 5-bit data is "10"
In a still image of 000 ″ (luminance 50%), only the subfield S1 emits light, as shown in FIG.

When the brightness of the moving image changes smoothly, the following problems occur. That is, it is assumed that the value of 5-bit data is a moving image in which the value changes between “10000” and “01111”. In the field where the 5-bit data value is "10000", only the sub-field S1 emits light, and in the field where the 5-bit data value is "01111", all the sub-fields S2, S3 other than the sub-field S1,
S4 and S5 emit light. When the gradation changes at such a change point in a certain pixel, as shown in FIG. 11B, the luminance of 50% originally appears to be 0% or 100%. As a result, accurate gradation expression cannot be performed and a pseudo contour is generated.

Therefore, the light emitting period of the subfield corresponding to the most significant bit is divided into two, and the ratio of the light emitting period in each subfield within one field is 8: 8: 8: 4 :.
It is conceivable that the subfields are rearranged so that the light emission order of the subfields divided into two is set to 2: 1 so as not to continue. However, in this case, the number of subfields becomes 6, and the number of subfields increases.

In the above embodiment, 1 in PDP8 is used.
The PDP 8 is controlled so that the ratio of the light emitting period of each subfield in the field is 8: 8: 4: 2: 1 and the two subfields of the light emitting period “8” are not continuous. In a still image in which the value of the 5-bit data obtained from the selection circuit 5 is "10000", as shown in FIG.
1 emits light.

When the value of 5-bit data is "10000"
Assume a case of a moving image that changes between 0111 "and" 01111 ". In the field in which the value of the 5-bit data obtained from the selection circuit 5 is" 10000 ", the subfields S2 and S1 emit light, In the field whose 5-bit data value is "01111", all the subfields S2, S3, S4 other than the subfield S1.
And S5 emits light. Therefore, in adjacent fields, light emission does not continue or non-light emission does not continue, and pseudo contours are prevented. Moreover, the number of subfields is 5, and the number of subfields can be reduced as compared with the case where the light emitting period of the subfield corresponding to the most significant bit is divided into two.

In this embodiment, for low gradation (input video data: 00000000-01111111), 5-bit data (00000-01111) output from the pseudo gradation circuit 4 is selected and high gradation is selected. (Input video data: 10000000-11111111)
In, the 4-bit data (1000 to 1111) output from the pseudo gradation circuit 4 is selected. Therefore, when no correction processing is performed, as shown by the polygonal line a in FIG. 2, the signal level after inverse gamma correction and P
The brightness level of DP does not change linearly.

Therefore, as described above, the gradation correction circuit 3 performs gradation correction so that the signal level after the inverse gamma correction and the brightness level of the PDP change linearly as shown by the straight line b in FIG. Is being carried out. As a result, as shown in FIG. 2, the 4-bit data has a display characteristic with respect to the number of bits larger than 4 bits, and the 5-bit data has a display characteristic with the number of bits smaller than 5 bits. The display characteristic as if converted into data of about 4.5 bits is obtained by the error diffusion processing.

[2] Description of First Modification

The first modification will be described. The structure of the drive control circuit of the PDP is the same as that of FIG. However, the operations of the gradation correction circuit 3, the selection circuit 5, the conversion circuit 6, and the signal processing circuit 7 are different from those in the above-described embodiment. As shown in Table 2, the selection circuit 5 includes 00000000 to 010111111.
Input video data of 5 bits data output from the pseudo gradation circuit 4 (0000 to 01011)
And the 4-bit data (0110-1111) output from the pseudo gradation circuit 4 is selected for the input video data of 01100000-111111111. Further, the conversion circuit 6 performs conversion as shown in Table 2 and outputs 5-bit data.

[0047]

[Table 2]

In the signal processing circuit 7, the ratio of the light emitting period of each subfield in one field in the PDP 8 is 8:
The light emission period is "8" and "6: 4: 2: 1".
PD so that two 6 "subfields are not consecutive
Control P8. That is, if the subfields corresponding to 8: 6: 4: 2: 1 are S1, S2, S3, S4, and S5, the PDP8 is arranged such that the subfields are arranged in the order of S2, S3, S1, S4, and S5. To control.

S1 corresponds to the most significant bit of the 5-bit data output from the conversion circuit 6, S2 corresponds to the second most significant bit, and S3 corresponds to the most significant 3 bits.
The S4 corresponds to the 4th bit from the most significant bit, and the S5 corresponds to the least significant bit. In addition, the signal processing circuit 7, for each bit of the transmitted data,
The PDP 8 is controlled so as to perform writing / light emission control of the corresponding subfield.

In this case, when no correction processing is performed, the signal level after the inverse gamma correction and the brightness level of the PDP do not change linearly, as shown by the broken line a in FIG. Therefore, as described above, the signal level after the inverse gamma correction and the brightness level of the PDP are the straight line b in FIG.
Gradation correction circuit 3 so that it changes linearly as shown in FIG.
The gradation correction is performed with.

[3] Description of Second Modification

The second modification will be described. The structure of the drive control circuit of the PDP is the same as that of FIG. However, the operations of the gradation correction circuit 3, the selection circuit 5, and the conversion circuit 6 are different from those in the above embodiment.

The selection circuit 5, as shown in Table 3,
For input video data of 0000 to 01101111, 4-bit data (0000 to 0110) output from the pseudo gradation circuit 4 is selected, and 01110,000 is selected.
For the input video data of ˜11111111, the 5-bit data (011
10-11110) is selected. In addition, the conversion circuit 6
Conversion as shown in Table 3 is performed and 5-bit data is output.

[0054]

[Table 3]

In the signal processing circuit 7, the ratio of the light emitting period of each subfield in one field in the PDP 8 is 8:
8: 4: 2: 1 and the emission period "8" and "
PD so that two subfields of 8 "are not consecutive
Control P8. That is, if the subfields corresponding to 8: 8: 4: 2: 1 are S1, S2, S3, S4, and S5, the PDP 8 is arranged such that the subfields are arranged in the order of S2, S3, S1, S4, and S5. To control.

S1 corresponds to the most significant bit of the 5-bit data output from the conversion circuit 6, S2 corresponds to the second most significant bit, and S3 corresponds to the most significant bit to three.
The S4 corresponds to the 4th bit from the most significant bit, and the S5 corresponds to the least significant bit. In addition, the signal processing circuit 7, for each bit of the transmitted data,
The PDP 8 is controlled so as to perform writing / light emission control of the corresponding subfield.

In this case, when no correction processing is performed, the signal level after the inverse gamma correction and the brightness level of the PDP do not change linearly, as shown by the polygonal line a in FIG. Therefore, as described above, the signal level after the inverse gamma correction and the brightness level of the PDP are the straight line b in FIG.
Gradation correction circuit 3 so that it changes linearly as shown in FIG.
The gradation correction is performed with.

[4] Description of Third Modification

The third modification will be described. The structure of the drive control circuit of the PDP is the same as that of FIG. However, the gradation correction circuit 3, the pseudo gradation conversion circuit 4, the selection circuit 5, and the conversion circuit 6
And the operation of the signal processing circuit 7 is different from that of the above-described embodiment.

The pseudo gradation circuit 4 performs the error diffusion processing for reducing the input 8-bit data to 5-bit data, and the first error diffusion processing unit (5-bit output processing unit) 4 described above.
In addition to the second error diffusion processing unit (4 bit output processing unit) 42 that performs the error diffusion process of reducing 1 and the input 8 bit data to 4 bit data, it also reduces the input 8 bit data to 3 bit data. A third error diffusion processing unit (3-bit output processing unit) that performs error diffusion processing is provided.

As shown in Table 4, the selection circuit 5 uses 000
For the input video data of 0000 to 01111111, 5-bit data (0000 to 01111) output from the pseudo gradation circuit 4 is selected, and 100000 is selected.
For input video data of 00 to 10111111,
The 4-bit data (1
000 to 1011), and 11,000,000 to 11
For the input video data of 111111, 3-bit data (110 to 11) output from the pseudo gradation circuit 4 is input.
Select 1). The conversion circuit 6 also performs conversion as shown in Table 4 and outputs 5-bit data.

[0062]

[Table 4]

In the signal processing circuit 7, the ratio of the light emitting period of each subfield in one field in the PDP 8 is 8:
The light emission period is "8" and "6: 4: 2: 1".
PD so that two 6 "subfields are not consecutive
Control P8. That is, if the subfields corresponding to 8: 6: 4: 2: 1 are S1, S2, S3, S4, and S5, the PDP8 is arranged such that the subfields are arranged in the order of S2, S3, S1, S4, and S5. To control.

S1 corresponds to the most significant bit of the 5-bit data output from the conversion circuit 6, S2 corresponds to the second bit from the most significant bit, and S3 corresponds to 3 from the most significant bit.
The S4 corresponds to the 4th bit from the most significant bit, and the S5 corresponds to the least significant bit. In addition, the signal processing circuit 7, for each bit of the transmitted data,
The PDP 8 is controlled so as to perform writing / light emission control of the corresponding subfield.

In this case, if no correction processing is performed, the signal level after the inverse gamma correction and the brightness level of the PDP do not change linearly, as shown by the broken line a in FIG. Therefore, as described above, the signal level after the inverse gamma correction and the brightness level of the PDP are the straight line b in FIG.
Gradation correction circuit 3 so that it changes linearly as shown in FIG.
The gradation correction is performed with.

[0066]

According to the present invention, it is possible to obtain a drive control method for a display device capable of preventing the occurrence of false contours and reducing the number of subfields.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a drive control circuit of a PDP.

FIG. 2 is a graph for explaining correction processing by a gradation correction circuit.

[FIG. 3] Subfields S1 to S5 in one field
It is a schematic diagram which shows.

FIG. 4 is a flowchart showing an error diffusion processing procedure by a first error diffusion processing unit.

FIG. 5 is a schematic diagram schematically showing the content of error diffusion processing by a first error diffusion processing unit.

FIG. 6 is a schematic diagram showing data of a pixel to be processed, intra-frame error data, and inter-frame error data used in the description of the error diffusion processing by the first error diffusion processing unit.

FIG. 7 is a schematic diagram showing another example of the error diffusion processing by the first error diffusion processing unit.

FIG. 8 is a flowchart showing an error diffusion processing procedure by a second error diffusion processing unit.

FIG. 9 is a schematic diagram schematically showing the content of error diffusion processing by a second error diffusion processing unit.

FIG. 10 is a time chart showing drive control timing of the PDP according to the embodiment.

FIG. 11 is a time chart showing drive control timing of a PDP according to a normal drive method.

FIG. 12 is a graph for explaining correction processing by the gradation correction circuit in the first modified example.

FIG. 13 is a graph for explaining correction processing by the gradation correction circuit in the second modification.

FIG. 14 is a graph for explaining correction processing by the gradation correction circuit in the third modification.

[Explanation of symbols]

1 Inverse gamma correction circuit 2 A / D converter 3 gradation correction circuit 4 Pseudo-gradation circuit 5 selection circuit 6 conversion circuit 7 Signal processing circuit 8 PDP 41 First Error Diffusion Processing Unit 42 Second error diffusion processing unit

Continuation of front page (51) Int.Cl. ⁷ Identification code FI H04N 5/66 101 G09G 3/28 K (56) References JP-A-9-81072 (JP, A) JP-A-10-98663 (JP, A) JP-A-8-254965 (JP, A) JP-A-8-190360 (JP, A) JP-A-7-64501 (JP, A) JP-A-6-118921 (JP, A) JP-A-8- -106279 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G09G 3/00-5/42 H04N 5/66

Claims (2)

(57) [Claims] 1. A first step of performing error diffusion processing of at least two systems in which the obtained bit numbers are different from each other for video data, and the number of subfields in one field is the largest among the error diffusion processing of each system. The number corresponding to the number of bits is set, and the ratio of the light emitting period of the subfield corresponding to at least the most significant bit of the data having the bit number to the total light emitting period in one field is the normal subfield for the data having the bit number. The ratio of the light emitting period of the subfield corresponding to the most significant bit to the total light emitting period in one field is set to be smaller than that of the sub-field corresponding to the most significant bit and one bit below the most significant bit. The second subfield that arranges the subfields within one field so that the subfields A third step in which the output of the error diffusion processing of each system is switched and selected according to the step and the gradation level of the video data, and the driving processing of each subfield is performed based on the selected output. Drive control method for display device. 2. The first step is for image data,
The number of bits obtained is 2 of m bits and (m-1) bits.
System error diffusion processing is performed. In the second step, the number of subfields in one field is set to m, and one of the subfield emission periods corresponding to the most significant bit of data consisting of m bits is set. The ratio of the light emission period of the subfield corresponding to the most significant bit in the usual subfield method to the data of m bits to the total light emission period of the field is made smaller than the ratio of the light emission period of the subfield to the total light emission period of one field, and The subfields within one field are arranged so that the subfield corresponding to the most significant bit and the subfield corresponding to the bit one lower than the most significant bit are not continuous. For the image data of, the error diffusion processing that obtains m-bit data from the error diffusion processing of two systems is performed. Selects the output of, for the predetermined large gradation following the video data from the gradation, (m-
1) The drive control method for a display device according to claim 1, wherein an output of an error diffusion process that obtains 1-bit data is selected, and the drive process of each subfield is performed based on the selected output.