JP3466842B2 - Integrated circuit layout method and apparatus - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit layout method and apparatus, and more particularly to a method and apparatus for arranging simultaneously operating elements in a distributed manner.

[0002]

2. Description of the Related Art CAD (CO
As a device automatically arranged by MPUTER AIDED DESIGN) or the like, there has conventionally been a device having a configuration as shown in FIG.

A library 500 having information about elements constituting an integrated circuit and connection information 501 indicating a connection state of elements are given to a delay analysis section 502, and timing information indicating operation timing of each element in the delay analysis section 502. 503 is generated and output. Timing information 503
Is input to the weighting information calculation unit 504, and the weighting information 505 for prioritizing the placement of the wiring is generated and output for the portion with a large delay. The weighting information 505, the library 500, and the connection information 501 are input to the automatic layout unit 506, and the layout result 507 indicating the element layout is output.

As described above, the conventional automatic layout apparatus performs the layout in consideration of the wiring delay.

[0005]

However, conventionally, the layout has not been performed in consideration of the operation information obtained as a result of the logic simulation. For this reason, there is a possibility that elements operating at the same time are concentrated in a specific portion and the temperature of this portion rises, resulting in failure. Therefore, in a package encapsulating an integrated circuit, it is necessary to take measures against high temperature in order to prevent melting or destruction of the element. A cooling device such as a cooling fan is required to cool the high temperature area,
Further, there is a problem in that soundproof equipment for noise generated by the cooling device is required, which leads to an increase in peripheral devices, and the addition of these devices increases the power consumption of the entire system.

The present invention has been made in view of the above circumstances, and when elements are laid out, elements that operate simultaneously are prevented from concentrating in one place, and defects due to thermal destruction of an integrated circuit are prevented. And improve reliability,
An object of the present invention is to provide a layout method of an integrated circuit and a device thereof which can reduce costs and power consumption by eliminating the need for a cooling device, a soundproofing device and the like.

[0007]

The layout method of an integrated circuit according to the present invention is used when testing an integrated circuit, element information relating to elements constituting the integrated circuit, connection information indicating a logical connection relationship of the elements. Input the test data to the logic simulator unit to verify the logic operation, obtain the operation result, and give the connection information and the operation result to the simultaneous operation analysis unit to operate simultaneously within a predetermined unit time. The step of analyzing the elements to obtain the simultaneous operation information, and inputting the simultaneous operation information to the simultaneous operation position predicting unit to obtain the position information of the local region in which the signal lines to which the elements operating simultaneously are connected in a predetermined number or more. Obtaining the simultaneous operation position information shown, inputting the element information, the connection information, and the simultaneous operation position information into the layout unit, A step of obtaining a layout result of arranging the respective elements so that the elements to be operated are separated by a predetermined distance or more, and the step of obtaining the simultaneous operation information includes a signal to which the elements to be operated are connected every predetermined unit time. The step of obtaining a line includes the step of obtaining the simultaneous operation position information. The step of obtaining the simultaneous operation position information is performed by dividing the integrated circuit into predetermined unit areas, and the number of signal lines to which elements operating within the predetermined unit time are connected. And a step of setting the unit area in which the calculated number of signal lines is a predetermined number or more as the local area.

Here, instead of the test data, a test pattern used for analyzing the simultaneous operation may be generated and input to the logic simulator section.

The method may further include the step of setting the predetermined unit time to a desired length, and the step of obtaining the simultaneous operation information may use the set predetermined unit time. The method may further include the step of setting the unit area to a desired size, and in the step of obtaining the simultaneous operation position information, the set predetermined unit area may be used.

The integrated circuit layout device of the present invention provides element information regarding elements forming the integrated circuit, connection information indicating a logical connection relationship of the elements, and test data used when testing the integrated circuit. A logic simulator that outputs a result of an operation and outputs the result of the operation, and the connection information and the result of the operation are given, and the elements that operate simultaneously within a predetermined unit time are analyzed and the simultaneous operation information is output. And a simultaneous operation position predictor that outputs the simultaneous operation position information indicating the position information of a local area where a predetermined number or more of signal lines to which the elements that operate simultaneously are connected, given the simultaneous operation information And the element information, the connection information, and the simultaneous operation position information are given, and the elements included in the local region and operating simultaneously are separated by a predetermined distance or more. And a layout unit that outputs layout information for arranging the respective elements, the simultaneous operation analysis unit obtains a signal line to which the operating elements are connected for each predetermined unit time, and the simultaneous operation position prediction unit , The integrated circuit is divided into predetermined unit areas, the number of signal lines to which elements operating within the predetermined unit time are connected is found, and the number of the obtained signal lines is greater than or equal to a predetermined number. The unit area is the local area.

Here, in the logic simulator section, instead of the test data, a test pattern used for analyzing the simultaneous operation may be generated and the logic operation may be verified using this test pattern.

Further, the simultaneous operation analysis unit may be provided with time width setting data to set the length of the predetermined unit time, and further, the simultaneous operation position predicting unit may be arranged in a unit area. The size of the predetermined unit area may be set by being given setting data.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an integrated circuit layout device according to the first embodiment. Information about each element forming the integrated circuit, for example, a library 100 showing the type and size of the element, and connection information 1 showing the connection relationship of each element
01, and further the test data 101 is given to the logic simulator unit 103. Here, the test data 101 is generally used when testing the actual operation of the circuit at the stage of designing the integrated circuit.

The logic simulator unit 103 simulates a logic operation and outputs the operation result 104. The operation result 104 and the connection information 101 are input to the simultaneous operation analysis unit 105, the combination of elements that operate within a predetermined unit time such as 25 nsec is analyzed, and the simultaneous operation information 106 is generated and output.

The simultaneous operation information 106 is input to the general layout and wiring section 107a in the simultaneous operation position prediction section 107. The rough placement and routing unit 107a shows the rough placement and routing result 10 indicating the rough positions of the elements that operate simultaneously for each unit time.
7b is output to the local motion analysis unit 107c. The local motion analysis unit 107c generates, based on the rough position wiring result 107b, the simultaneous motion position information 108 indicating the coordinate positions of the elements that simultaneously operate for each unit time, and outputs the simultaneous motion position information 108 to the layout unit 109. Here, the coordinate position of the element is displayed for each local area having a predetermined area.

The layout unit 109 uses the simultaneous operation position information 108, the library 100, and the connection information 101 to perform layout so that elements that operate simultaneously are not concentrated in one place. For example, two or more elements that operate within one unit time are provided with a layout constraint such that they are laid out at a predetermined distance or more to reduce the concentration of elements that operate simultaneously. The final layout result 110 thus obtained is output from the layout unit 109.

An example of the simultaneous operation information 106 is shown in FIG. In FIG. 2, 25 nsec is set as a unit time, and the presence of elements that operate simultaneously within this unit time is indicated by
The signal lines are shown by Z, and the operating signal lines are indicated by "1" and the inactive signal lines are indicated by "0". For example, in the first unit time of 25 nsec, the signal lines B, Y and Z are operating at the same time. Taking 175 nsec as an example, not all signal lines are in operation.

FIG. 3 shows an example of the simultaneous operation position information 108. Areas 811 and 81 with 10 square μm as one unit
, 821, ..., 821, ..., For example, in the area 811, there are signal lines A, B, and C, and in the area 812.
Signal lines F and G exist. Then, it is assumed that the count "1" is performed when there are three or more signal lines that operate simultaneously in each unit time in each region.

For example, in the area 811, the number of simultaneous operations of all three signal lines A to C is 200 nsec from FIG.
And 500 nsec. The number of simultaneous operations for each area thus obtained is tabulated in FIG. For example, in the area 812, the number of simultaneous operations is 0.
And the region 834 is 9 times.

Next, FIG. 5 shows the configuration of the layout apparatus according to the second embodiment of the present invention. In the first embodiment, the logic simulator unit 103 is used by using the test data 102 created to test the actual operation at the time of designing the integrated circuit.
I'm doing a logic simulation. On the other hand, in the second embodiment, the test data 102 for general test is used.
Is different in that a test pattern that is more suitable for detection of simultaneous operation points is generated and used so that even undetectable simultaneous operation points can be found.

Library 200 and connection information 201,
The signal setting data 202 for generating the above-mentioned test pattern is given to the test pattern automatic generation and logic simulator unit 203. In the automatic test pattern generation and logic simulator unit 203, a test pattern suitable for the detection of the simultaneous operation portion is generated, and a logic simulation is performed using this test pattern. The operation result and the connection information 201 obtained by this logic simulation are input to the simultaneous operation analysis unit 205, the combination of elements that operate simultaneously within a unit time is analyzed, and the simultaneous operation information 206 is generated and output. Subsequent processing,
Similar to the first embodiment, the simultaneous operation information 2 is stored in the general placement and wiring section 207a in the simultaneous operation position prediction section 207.
06 is input, the rough placement and routing result 207b is generated and output to the local motion analysis unit 207c, and the simultaneous motion position information 208 is generated and output to the layout unit 209. The layout unit 209 uses the simultaneous operation position information 20.
8 and the library 200 and the connection information 201 are used to perform layout so that elements that operate simultaneously are dispersed, and a final layout result 210 is output.

FIG. 6 shows the arrangement of a layout device according to the third embodiment of the present invention. In the second embodiment, the unit time length is fixed, for example, 25 nsec. In contrast, the third embodiment is different in that the unit of time can be set to a desired length by giving the time width setting data 301 to the simultaneous operation analysis unit 205. The same elements as those of the other second embodiment are designated by the same reference numerals and the description thereof will be omitted.

For example, when the conditions for the temperature are strict and it is necessary to detect the simultaneous operation points with higher accuracy, the width of the unit time is set to be short. On the contrary, when giving priority to processing the layout processing at a higher speed than the accuracy, the length of the unit time is set to be long. Here, in the third embodiment, the time width setting data 301 is given to the simultaneous operation analysis unit 205 in the second embodiment. However, the length of the unit time may be changed by giving the time width setting data 301 to the simultaneous operation analysis unit 205 in the first embodiment shown in FIG.

FIG. 7 shows the arrangement of a layout apparatus according to the fourth embodiment of the present invention. In the second embodiment,
For example, the size of the local area that operates simultaneously is 10 square μ
It is fixed like m. On the other hand, in the fourth embodiment, the local area setting data 401 is given to the simultaneous operation position predicting unit 207, so that the size of the local area can be changed as necessary. The local area is set small to increase the accuracy, and conversely set large to increase the processing speed. In addition, in the fourth embodiment, the second
Although the local area setting data 401 is given to the simultaneous operation position predicting unit 207 in the first embodiment, the local area setting data 401 is given to the simultaneous operation position predicting unit 107 in the first embodiment to determine the size of the local area. May be changed.

According to the above-mentioned first to fourth embodiments, the elements which simultaneously operate in the local region are detected within the unit time,
Since the layout is separated by a certain distance or more so as not to concentrate at one place, heat is generated at a specific place and the temperature rises,
It is possible to prevent a failure from occurring and improve reliability. In addition, it is possible to reduce the manufacturing cost and the power consumption by eliminating the need to take measures against high temperature in the package enclosing the integrated circuit and to eliminate the need to provide various cooling equipments and soundproofing devices.

Each of the above-described embodiments is an example,
It does not limit the invention. For example, the simultaneous operation information shown in FIG. 2 and the simultaneous operation position information shown in FIG. 3 and FIG. 4 are examples, respectively, and if they indicate the points that operate at the same time, they have different forms. May be.

[0028]

As described above, according to the integrated circuit layout method and apparatus of the present invention, a combination of elements operating simultaneously in a local area is detected every unit time, and such an element is determined to be a predetermined value. By laying out so as to be separated by a distance or more, it is possible to prevent the temperature of a specific portion from rising and causing a failure, and to suppress the increase in cost and power consumption due to the addition of the cooling device and the soundproof device. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a layout device for an integrated circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing simultaneous operation information in the layout device.

FIG. 3 is an explanatory diagram showing simultaneous operation position information in the layout device.

FIG. 4 is an explanatory diagram showing a table of simultaneous operation position information in FIG.

FIG. 5 is a block diagram showing a configuration of an integrated circuit layout device according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of an integrated circuit layout device according to a third embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of an integrated circuit layout device according to a fourth exemplary embodiment of the present invention.

FIG. 8 is a block diagram showing the configuration of a conventional integrated circuit layout device.

[Explanation of symbols]

100, 200 Library 101, 201 Connection information 102 Test data 103 Logic simulator section 104, 204 Operation result 105, 205 Simultaneous operation analysis section 106, 206 Simultaneous operation information 107, 207 Simultaneous operation position prediction section 107a, 207a General placement and wiring section 107b 207b Approximate placement and routing result 107c, 207c Local operation analysis unit 108, 208 Simultaneous operation position information 109, 209 Layout unit 110, 210 Layout result 202 Signal setting data 203 Automatic test pattern generation and logic simulator unit 301 Time width setting data 401 Local Area setting data

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 G06F 17/50 H01L 21/822 H01L 27/04

Claims (8)

(57) [Claims] 1. Logic operation by inputting element information about elements constituting an integrated circuit, connection information indicating a logical connection relationship of the elements, and test data used when testing the integrated circuit to a logic simulator section. Performing verification, obtaining an operation result, giving the connection information and the operation result to the simultaneous operation analysis unit, analyzing the elements operating simultaneously within a predetermined unit time, and obtaining the simultaneous operation information, Inputting the simultaneous operation information to the simultaneous operation position prediction unit, obtaining the simultaneous operation position information indicating the position information of the local region where the signal lines connected to the simultaneously operating elements are present in a predetermined number or more, the element information, The connection information and the simultaneous operation position information are input to the layout unit, and each element included in the local region and operated simultaneously is separated by a predetermined distance or more. A step of obtaining a layout result of placing, the step of obtaining the simultaneous operation information includes a step of obtaining a signal line to which an operating element is connected, for each predetermined unit time, and a step of obtaining the simultaneous operation position information. Is a step of dividing the integrated circuit into predetermined unit areas, and obtaining the number of signal lines to which the elements operating within the predetermined unit time are connected; and the obtained number of signal lines is a predetermined number. A method of laying out an integrated circuit, comprising: setting the unit area as above as the local area. 2. A logic simulator comprising a step of generating a test pattern used for analyzing simultaneous operations, the test pattern, element information regarding elements forming an integrated circuit, and connection information indicating a logical connection relationship of the elements. Input to the unit to verify the logical operation and obtain an operation result, and the connection information and the operation result are given to the simultaneous operation analysis unit to analyze the elements that operate simultaneously within a predetermined unit time. The step of obtaining the simultaneous operation information, and inputting the simultaneous operation information to the simultaneous operation position prediction unit, the simultaneous operation position information indicating the position information of the local area in which a predetermined number or more of signal lines to which the elements operating at the same time are connected, The step of obtaining, and inputting the element information, the connection information, and the simultaneous operation position information into a layout unit, and selecting elements included in the local region and operating simultaneously. A step of obtaining a layout result of arranging the respective elements so as to be separated by a predetermined distance or more, and the step of obtaining the simultaneous operation information is to obtain a signal line to which the operating elements are connected, every predetermined unit time. In the step of obtaining the simultaneous operation position information, the step of dividing the integrated circuit into predetermined unit areas, and obtaining the number of signal lines to which elements operating within the predetermined unit time exist And a step of setting the unit area having the obtained number of signal lines equal to or larger than a predetermined number as the local area, the integrated circuit layout method. 3. The method according to claim 1, further comprising the step of setting the predetermined unit time to a desired length, and the step of obtaining the simultaneous operation information uses the set predetermined unit time. 2. The layout method of the integrated circuit according to 2. 4. The method according to claim 1, further comprising the step of setting the predetermined unit area to a desired size, and the step of obtaining the simultaneous operation position information uses the set predetermined unit area. Alternatively, the layout method of the integrated circuit described in 2. 5. A logic operation is verified by being provided with element information regarding elements constituting an integrated circuit, connection information indicating a logical connection relationship of the elements, and test data used when testing the integrated circuit. A logic simulator unit that outputs an operation result, a simultaneous operation analysis unit that is given the connection information and the operation result, analyzes the elements that operate simultaneously within a predetermined unit time, and outputs the simultaneous operation information, Simultaneous operation position prediction unit that outputs simultaneous operation position information that is given the simultaneous operation information and that indicates the position information of the local area where the signal lines to which the elements that operate at the same time are connected exist in a predetermined number or more, the element information and the connection Information and the simultaneous operation position information are given, and layout information for arranging the elements included in the local region and operating simultaneously is separated by a predetermined distance or more. And a layout unit for outputting the signal, the simultaneous operation analysis unit obtains a signal line to which an operating element is connected, for each predetermined unit time, and the simultaneous operation position prediction unit sets the integrated circuit in a predetermined unit. The number of signal lines to which the elements that operate within the predetermined unit time are connected is determined by dividing each region, and a unit region in which the number of the obtained signal lines is a predetermined number or more is set as the local region. An integrated circuit layout device characterized by the above. 6. A test pattern used to analyze simultaneous operations is generated, and the logic is given a test pattern, element information regarding elements forming an integrated circuit, and connection information indicating a logical connection relationship of the elements. A logic simulator section that verifies the operation and outputs the operation result, and a simultaneous operation that outputs the simultaneous operation information by analyzing the elements that are simultaneously operated within a predetermined unit time given the connection information and the operation result. An analysis unit, and the simultaneous operation position prediction unit that is provided with the simultaneous operation information and outputs the simultaneous operation position information indicating the position information of the local region in which the signal lines to which the elements operating simultaneously are connected in a predetermined number or more, Given the element information, the connection information, and the simultaneous operation position information, each element included in the local region and operating simultaneously is separated by a predetermined distance or more. A layout unit that outputs layout information for arranging children, the simultaneous operation analysis unit obtains a signal line to which an operating element is connected, for each predetermined unit time, and the simultaneous operation position prediction unit includes: A unit area in which the integrated circuit is divided into predetermined unit areas, the number of signal lines to which the elements that operate within the predetermined unit time are present is determined, and the number of the obtained signal lines is equal to or greater than a predetermined number. A layout device for an integrated circuit, wherein: 7. The layout of an integrated circuit according to claim 5, wherein the simultaneous operation analysis unit is provided with time width setting data and sets the length of the predetermined unit time. apparatus. 8. The integrated circuit according to claim 5, wherein the simultaneous operation position predicting unit is provided with unit area setting data and sets the size of the predetermined unit area. Layout equipment.