JP3456073B2 - Manufacturing method of nonvolatile semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a so-called virtual ground type memory cell array structure.
The present invention relates to a method of manufacturing a device.

[0002]

2. Description of the Related Art In recent years, large-capacity non-volatile semiconductor memory devices such as mask ROMs, EPROMs and flash memories have been required for storing programs and file data. Then, in these nonvolatile semiconductor memory devices, in order to reduce the manufacturing cost per bit, it is necessary to reduce the memory cell area as much as possible to achieve miniaturization.

In order to meet such demands, a so-called virtual ground type memory cell array configuration in which an equivalent circuit of an EPROM is shown in FIG. 13 is proposed as a memory cell array configuration in which memory cells can be densely packed. ing.
In this virtual ground type memory cell array configuration, bit lines /
The wirings 11a to 11d to be the source lines and the word lines 12a,
12b and 12b are arranged in a grid pattern, and the wirings 11a to 11
The memory cells 13a to 13f are arranged in a matrix between d.

When writing data to, for example, the memory cell 13b of the EPROM shown in FIG. 13, only the word line 12a is set to a high potential of 12V, and all the other word lines 12b are grounded. Then, the wiring 11c connected to the drain of the memory cell 13b and all wirings 11d on the right side in FIG. 13 are set to 5V, and all the remaining wirings 11a and 11b on the left side in FIG. 13 are grounded. To do. As a result, current flows only in the memory cell 13b, and data is written by hot electron injection.

On the other hand, when reading data from the same memory cell 13b, only the word line 12a is set to 5V, for example, and all the other word lines 12b are grounded. Then, the wiring 11c connected to the drain of the memory cell 13b and all the wirings 11 on the right side of the wiring 11c in FIG.
Then, d is set to 2V and then floated, and all the wirings 11a and 11b on the left side in FIG. 13 are grounded.

In this case, if the memory cell 13b is in the erased state, the wiring 11c is connected to the wiring 1 through the memory cell 13b.
Since the electric charge is discharged to 1b, when the potential of the wiring 11c drops to an intermediate potential between 2V and 0V, the potential drop is detected to read the data.

In the non-volatile semiconductor memory device having the virtual ground type memory cell array structure as described above, the word line 12a is connected to each of the wirings 11a to 11d to be a bit line / source line.
Two memory cells 13a-1 each sharing 12b
Since 3f is connected, it is possible to arrange the memory cells 13a to 13f with the most efficient area.

In order to realize a nonvolatile semiconductor memory device having such a virtual ground type memory cell array structure,
Layout configuration called contactless type, and X
Two types are considered: a layout configuration called a mold.

In the contactless layout configuration of these, the diffusion layer formed on the semiconductor substrate is the wiring 1
It is used as 1a-11d. On the other hand, in FIG.
An X-type layout configuration is shown. In this layout configuration, the element active region 14 of the semiconductor substrate and the word lines 12a and 12b extending while bending are arranged obliquely to each other as a whole.

[0010]

However, the bit line /
In the contactless layout configuration in which the diffusion layers are used for the wirings 11a to 11d as the source lines, the high-speed operation is difficult because the wiring resistance of the bit line / source line is high. Further, it is necessary to form a diffusion layer as the wirings 11a to 11d before the word lines 12a and 12b, and the diffusion layer is self-aligned with the word lines 12a and 12b, and therefore, the peripheral circuit portion. Since they cannot be formed at the same time, the number of manufacturing steps is increased and the manufacturing cost is increased.

Further, in the X-type layout configuration shown in FIG. 14, the element active regions 14 and the word lines 12a and 12b are arranged obliquely with respect to each other as a whole, and the word lines 12a and 12b with respect to the element active regions 14 are arranged. Since the gate length fluctuates due to misalignment, the performance of the memory cell transistor is unstable and the reliability is low. Moreover, the overhead of the area occupied by the memory cells 13a to 13f is large, and the memory cell area cannot be sufficiently reduced, which makes miniaturization difficult.

[0012]

[Means for Solving the Problems] Claim 1 No Volatile semiconductor
The method of manufacturing the body memory device is such that the stripe-shaped element isolations parallel to each other are separated.
A step of forming a film on the surface of a semiconductor substrate, and the element isolation
Striped words parallel to each other extending in a direction orthogonal to the membrane
Forming the lines and said word lines being adjacent to each other
The element isolation film between them should be parallel to the word line.
Every other in both the direction and the orthogonal direction,
Removing using the word line as a mask, and
Then, using the word line and the device isolation film as a mask,
A step of forming a diffusion layer by introducing impurities into the semiconductor substrate
And formed in a region where the element isolation film is removed,
The diffusion layers arranged in the direction orthogonal to the word line are
And a step of forming wiring for electrically connecting
Is characterized by.

A method of manufacturing a non-volatile semiconductor memory device according to a second aspect is the method of manufacturing a non-volatile semiconductor memory device according to the second aspect, wherein a step of depositing an insulating film after forming the word line and the element isolation film. In the region where the removal is performed, a step of performing the removal while forming a side wall made of the insulating film on a side surface of the word line is characterized.

[0014] In the manufacturing method of the nonvolatile semiconductor memory device according to claim 1, the connecting portion of the wiring of the bit line / source lines, because it is shared by four memory cell transistors with a focus on the connection part, a virtual A grounded memory cell array configuration can be realized.

Despite this, part of the striped element isolation film is removed by using the word line as a mask in order to obtain a region for forming a diffusion layer which will be a connection portion of the wiring as the bit line / source line. Therefore, the element isolation film is formed in self-alignment with the word line. Therefore, even if the alignment margin is not secured in the element isolation film, the misalignment of the word lines with respect to the element isolation film does not occur, the gate length does not change, and the performance of the memory cell transistor is affected by the variation in the gate length. There is no stabilization.

In the method of manufacturing a non-volatile semiconductor memory device according to the second aspect of the present invention, since the element isolation film is removed while forming the side wall of the insulating film on the side surface of the word line, the semiconductor substrate at the side edge portion of the word line. Is not damaged by etching.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION First to third embodiments of the present invention applied to an EPROM and a fourth embodiment of the present invention applied to a NOR type mask ROM of an ion implantation programming system will be described below.
Specific examples will be described with reference to FIGS.

1 to 3 show a first specific example. In this first specific example, as shown in FIGS. 1A and 3A, parallel striped field oxide films 22 are formed on the surface of the semiconductor substrate 21 by the LOCOS method or the like, and Striped element active regions 23 parallel to each other are formed between the field oxide films 22. Then, a gate oxide film 24 is formed on the surface of the element active region 23.

Next, as shown in FIGS. 1 (b) and 3 (a), a conductive film for forming the floating gate 25 is processed into a pattern covering each element active region 23, and thereafter, for capacitive coupling. The insulating thin film 26 is formed on the entire surface.

Then, the word line 27a which becomes the control gate
To 27c are formed in parallel stripes extending in the direction orthogonal to the element active region 23, and the conductive film for forming the floating gate 25 is also patterned using the masks for the word lines 27a to 27c. And the memory cells 31a arranged in a matrix
An isolated floating gate 25 is formed every ~ 31i.

Next, as shown in FIG. 2A, the field oxide film 22 between the word lines 27a to 27c adjacent to each other is formed in a direction parallel to and perpendicular to the word lines 27a to 27c. In every case, every other one is covered with the photoresist 32. Then, by RIE using the word lines 27a to 27c and the photoresist 32 as a mask, FIG.
As shown in FIGS. 3A and 3B, the field oxide film 2
Remove 2.

Next, after removing the photoresist 32,
Arsenic is ion-implanted into the semiconductor substrate 21 using the word lines 27a to 27c and the field oxide film 22 as a mask. As a result, as shown in FIG. 3C, in the element active region 23 formed from the beginning, not only the regions other than under the word lines 27a to 27c but also the field oxide film in the process of FIG. The diffusion layer 33 is also formed in the region where 22 is removed.

Therefore, up to this point, each memory cell 31a
31i are completed, and one source / drain diffusion layers of the transistors adjacent to each other in the extending direction of the word lines 27a to 27c are electrically connected.

Next, an interlayer insulating film (not shown) is formed on the entire surface, and as shown in FIG. 2B, it is formed in the region where the field oxide film 22 is removed in the step of FIG. 3B. Contact holes 34a and 34b reaching the diffusion layer 33 are formed in the interlayer insulating film. Then, by patterning a metal wiring (not shown) such as an Al wiring which is in contact with the diffusion layer 33 through the contact holes 34a and 34b arranged in the direction orthogonal to the word lines 27a to 27c, a bit line / source line is formed. Form.

EPR manufactured by the first embodiment as described above
The OM has four memory cells 31 with four contact holes 34a.
The transistors b, 31c, 31e, and 31f are shared, and the contact hole 34b also has four memory cells 31.
Since it is shared by the transistors d, 31e, 31g, and 31h, it has a virtual ground type memory cell array configuration.

FIG. 4 shows a second specific example. In the second specific example, as shown in FIG. 4A, word lines 27a ...
After forming 27c and the floating gate 25, the film thickness is 50n.
After depositing an insulating film 35 of about m in thickness on the entire surface,
Substantially the same steps as the first specific example shown in FIGS. 1 to 3 are performed except that the step of removing the field oxide film 22 shown in FIGS. 3A and 3B is performed.

In the second embodiment as described above, even if the RIE for removing the field oxide film 22 is performed in the region not covered with the photoresist 32, as shown in FIG. The sidewalls composed of 35 are word lines 27a to 27c
Of the word lines 27a to 27c, the semiconductor substrate 21 is not exposed to the plasma for RIE.

Therefore, the semiconductor substrate 21 at the side edge portions of the word lines 27a to 27c is not damaged, and the EPROM can be manufactured without deterioration of data retention characteristics and increase of power consumption due to leakage current.

FIG. 5 shows a third specific example. This third specific example also uses the word line 2 as shown in FIGS.
Until the formation of 7a to 27c and the floating gate 25, substantially the same steps as those of the first specific example shown in FIGS.

However, in this third embodiment, immediately after this state, arsenic is ion-implanted into the semiconductor substrate 21 using the word lines 27a to 27c and the field oxide film 22 as a mask, and the element formed from the beginning. The diffusion layer 33 is formed only in a region of the active region 23 other than under the word lines 27a to 27c.

After that, an insulating film (not shown) is deposited on the entire surface, and in the direction parallel to the word lines 27a to 27c, the word lines 27a to 27c have a width across the element active regions 23 adjacent to each other. In the direction orthogonal to the word line 27a
A photoresist (not shown) having an opening with a width wider than the interval between the ~ 27c is formed.

Then, RIE using this photoresist as a mask is applied to the insulating film, and side walls made of this insulating film are formed on the side surfaces of the word lines 27a to 27c.
As shown in FIG. 5A, every other word line 27a to 27c in every direction parallel and orthogonal to each other,
Contact holes 36a and 36b reaching the element active region 23
To open a hole. Then, wiring layers 37a and 37b contacting the element active region 23 through the contact holes 36a and 36b are formed.

Next, an interlayer insulating film (not shown) is formed on the entire surface, and contact holes 38a and 38b reaching the wiring layers 37a and 37b are opened in the interlayer insulating film as shown in FIG. 5B. . Then, a metal wiring (not shown) such as an Al wiring, which is in contact with the wiring layers 37a and 37b through the contact holes 38a and 38b arranged in the direction orthogonal to the word lines 27a to 27c, is patterned to form a bit line / source. Form a line.

EPR manufactured by the above third embodiment
The OM, like the EPROM manufactured in the first example,
The contact hole 38a has four memory cells 31b, 31
It is shared by the transistors c, 31e, and 31f,
The contact hole 38b also has four memory cells 31d and 31.
Since it is shared by the transistors e, 31g, and 31h, it has a virtual ground type memory cell array configuration.

6 to 12 show a fourth specific example.
In the fourth specific example, as shown in FIGS. 6A and 9A, a SiO ₂ film 42 as a striped field oxide film is formed on the surface of a Si substrate 41 in parallel with each other by the LOCOS method or the like. As a result, stripe-shaped element active regions 43 parallel to each other are formed between the SiO ₂ films 42. And
SiO as a gate oxide film on the surface of the element active region 43
_Two films 44 (FIG. 12) are formed.

Next, as shown in FIGS. 6B and 9B, parallel striped word lines extending in the direction orthogonal to the element active region 43 are formed into tungsten polycide layers 45.
To form. Then, as shown in FIGS. 7A and 9C, the tungsten polycide layers 4 adjacent to each other are formed.
The SiO ₂ film 42 between the five is covered with the photoresist 46 in every other direction in both the direction parallel to the tungsten polycide layer 45 and the direction orthogonal thereto.

Next, by etching using the tungsten polycide layer 45 and the photoresist 46 as a mask, FIG.
As shown in FIG. 10B and FIG. 10A, the SiO ₂ film 42 is removed. Then, a low-concentration diffusion layer 47 is formed by ion implantation of impurities using the tungsten polycide layer 45, the photoresist 46, and the SiO ₂ film 42 as a mask.

Next, as shown in FIG. 10B, after removing the photoresist 46, a sidewall protective film made of a SiO ₂ film 48 or the like is formed on the side surface of the tungsten polycide layer 45, and the tungsten polycide layer is formed. 45 and SiO ₂ film 4
A high-concentration diffusion layer 51 is formed by ion implantation of impurities using the masks 2 and 48.

As a result, in the element active region 43 formed from the beginning, not only the region other than under the tungsten polycide layer 45 but also the region shown in FIG.
Diffusion layers 47 and 51 are also formed in the regions where the SiO ₂ film 42 is removed in the steps of (b) and FIG. 10A.

Therefore, up to this point, the transistors forming the memory cells 52 are completed, and one source / drain diffusion layers of the transistors adjacent to each other in the extending direction of the tungsten polycide layer 45 are electrically connected to each other. Connected to. After that, an interlayer insulating film 53 is formed on the entire surface, and as shown in FIGS. 8A and 10B, as shown in FIG.
A contact hole 54 reaching the diffusion layer 51 formed in the region where the SiO ₂ film 42 is removed in the steps of (b) and FIG. 10A is opened in the interlayer insulating film 53.

Next, as shown in FIG. 11A, the contact hole 54 is filled with a plug 55, and a barrier metal film 56a,
The metal film 56b and the antireflection film 56c are sequentially formed.
Then, as shown in FIG. 8B, the contact holes 54 arranged in a direction orthogonal to the tungsten polycide layer 45.
Metal wiring 56 electrically connected to the diffusion layer 51 via
Are patterned to form bit lines / source lines.

Next, as shown in FIG. 11B, a flat interlayer insulating film 57 is formed, and a wafer in this state is prepared and stored. Then, when the code data is received from the user, as shown in FIG. 12, a photoresist 58 having an opening 58a is formed on the memory cell 52 to be programmed, and impurities are ion-implanted using the photoresist 58 as a mask. . After that, a second-layer metal wiring (not shown) and a surface protection film (not shown) are formed, and openings for the electrode pads are formed in the surface protection film.

In the fourth embodiment described above, the programming is performed by ion implantation after the interlayer insulating film 57 is formed. However, the programming should be performed at the same time when the SiO ₂ film 42 as an element isolation film is formed. The programming may be performed by forming a thick SiO ₂ film 44 as a gate oxide film in the memory cell 52. Further, the programming may be performed by ion implantation after forming the SiO ₂ film 44 as the gate oxide film.

The above-mentioned first to fourth concrete examples are EPRs.
Although the invention of the present application is applied to an OM and a mask ROM, an EEPROM, a flash EEPROM, and a MON
The invention of the present application can be applied to all nonvolatile semiconductor memory devices such as OS memory and ferroelectric memory.

[0045]

In the manufacturing method of the nonvolatile semiconductor memory device according to claim 1 according to the present invention, despite it is possible to realize a virtual ground type memory cell array structure, without first ensuring alignment margin in the isolation layer However, since the performance of the memory cell transistor is not destabilized, a fine nonvolatile semiconductor memory device can be manufactured.

In the method of manufacturing a non-volatile semiconductor memory device according to the second aspect , since the semiconductor substrate at the side edge portion of the word line is not damaged by etching, deterioration of data retention characteristics and increase in power consumption due to leakage current are caused. A non-volatile semiconductor memory device can be manufactured.

[Brief description of drawings]

FIG. 1 is a plan view sequentially showing a first half process of a first specific example of the invention of the present application.

FIG. 2 is a plan view sequentially showing the latter half of the steps of the first specific example.

3A to 3C sequentially show steps of the first specific example, and FIG.
It is a perspective view containing the cross section in the position which follows the AA line of 2.

FIG. 4 is a side sectional view showing a step in the middle of a second specific example of the invention of the present application in order and taken along a line BB in FIGS.

FIG. 5 is a plan view corresponding to FIG. 2, showing the latter half steps of the third specific example of the invention of the present application in order.

FIG. 6 is a plan view sequentially showing the initial step of the fourth example of the invention of the present application.

FIG. 7 is a plan view sequentially showing the middle step of the fourth specific example.

FIG. 8 is a plan view sequentially showing the final step of the fourth specific example.

FIG. 9 sequentially shows the initial steps of the fourth specific example,
It is a sectional side view in the position which follows the CC line of FIGS.

FIG. 10 is a side cross-sectional view showing the middle-stage step of the fourth specific example in order and at a position along the line CC of FIGS.

FIG. 11 is a side cross-sectional view showing the final step of the fourth specific example in order and at a position along the line CC of FIGS. 6 to 8;

FIG. 12 shows a programming process of a fourth specific example,
It is a sectional side view in the position which follows the DD line of Drawing 8 (b).

FIG. 13E having a virtual ground type memory cell array configuration
It is an equivalent circuit diagram of PROM.

FIG. 14 is a plan view of a conventional example of the invention of the present application.

[Explanation of symbols]

21 semiconductor substrate 22 field oxide film 23 element active regions 27a to 27c word line 33 diffusion layer 35 insulating films 36a, 36b contact holes 37a, 37b wiring layer 41 Si substrate 42 SiO ₂ film 43 element active region 45 tungsten polycide layer 47 diffusion Layer 51 Diffusion layer 56 Metal wiring

Claims (2)

(57) [Claims] 1. A step of forming mutually parallel striped element isolation films on a surface of a semiconductor substrate, and a step of forming mutually parallel striped word lines extending in a direction orthogonal to the element isolation film. A step of removing the element isolation film between the word lines that are adjacent to each other by using the word line as a mask, in every other direction parallel to and orthogonal to the word line, A step of forming a diffusion layer by introducing impurities into the semiconductor substrate using the word line and the device isolation film as a mask after the removal; and the word formed in the region where the device isolation film is removed. And a step of forming a wiring for electrically connecting the diffusion layers arranged in a direction orthogonal to a line, the method for manufacturing a nonvolatile semiconductor memory device. 2. A step of depositing an insulating film after forming the word line, and a step of forming the sidewall of the insulating film on a side surface of the word line in the region where the element isolation film is removed. method of manufacturing a nonvolatile semiconductor memory device according to claim 1, characterized by comprising a step of performing.