JP3455684B2 - Semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ROM for adjusting variations in standard characteristics inside an IC, for example, a bipolar or BICMOS (Vice Moss) having a built-in Zener-Zap type PROM (Programmable ROM) circuit.
The present invention relates to a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Semiconductor integrated circuits
Then, in order to realize the adjustment-free operation in which the user does not need to adjust the variations of the standard characteristics including the output amplitude and the output frequency inside the IC, a ROM device holding adjustment data for adjusting those variations is used. Known to be built-in. In recent years, it is difficult to embed an electrical or optical ROM device in a bipolar or BI device.
Even in a semiconductor integrated circuit using a CMOS process,
In response to the above-mentioned demand for no adjustment, for example, it has become common to incorporate a Zener-Zap type PROM circuit. Furthermore, in such a semiconductor integrated circuit, in order to suppress the effect of characteristic shift (characteristic change) due to resin encapsulation, during the prober test (at the end of diffusion)
Instead, a device for writing adjustment data to a built-in PROM circuit at the time of shipping inspection has been developed and put into practical use. Further, in such a semiconductor integrated circuit, it is common to write adjustment data in the PROM circuit by a serial control signal in order to reduce the number of pins.

Here, regarding the conventional semiconductor integrated circuit,
This will be specifically described with reference to FIG. It should be noted that in the following description, a case will be described in which adjustment data having a value of m bits (m is an integer) is used. FIG. 10 is a circuit block diagram showing a configuration example of a conventional semiconductor integrated circuit. Figure 10
As shown in FIG. 1, the conventional semiconductor integrated circuit 101 has a CPU
A serial / parallel conversion circuit 102 connected to the CPU 100 for converting adjustment data input by the serial control signal from the CPU 100 into a parallel signal, and a PROM circuit 105 connected to the serial / parallel conversion circuit 102 and storing the adjustment data. ing. Further, the conventional semiconductor integrated circuit 101 is connected to the PROM circuit 105, and a D / A converter circuit 1 for converting the adjustment data from the PROM circuit 105 into an analog signal.
07, and an adjusted circuit 108 which is connected to the D / A converter circuit 107 and inputs the adjustment data converted into an analog signal. The circuit to be adjusted 8 has
First for adjusting each of n characteristics (n is an integer)
Through the nth blocks 181 to 18n, the characteristics of the output amplitude and the output frequency are adjusted.

The serial / parallel conversion circuit 102 includes:
Adjustment data and bit selection output circuit 26 is provided. The adjustment data and bit selection output circuit 26 has a first data for indicating the value of the adjustment data in bit units.
The to nth blocks 261 to 26n are provided corresponding to the first to nth blocks 181 to 18n in the adjusted circuit 108, respectively. Serial / parallel conversion circuit 10
After converting the serial control signal from the CPU 100 into a parallel signal, 2 outputs the adjustment data and the adjustment data from the bit selection output circuit 26 to the PROM circuit 105 in parallel according to the address of the serial control signal. Specifically, for example, the first block 261 determines whether the outputs 2611 to 261m are at a high level (hereinafter also referred to as “H”) or a low level (hereinafter also referred to as “L”) based on the serial control signal. It is a level. This allows the value of the adjustment data to be selected in bit units. Also, PROM
When writing the value of the adjustment data to the circuit 105, the first block 261 sets the output to L only for the write target bit and sets the output to H for the other bits. Furthermore, P
After writing the value of the adjustment data in the ROM circuit 105, the first block 261 outputs all the outputs 2611 to 261.
Let m be L. Note that, here, writing the value of the adjustment data means applying a predetermined write voltage or current to a PROM write terminal 151 described later to fix the output from the PROM circuit 105 as H.

The PROM circuit 105 stores the value of each adjustment data for the first to n-th blocks 181 to 18n in bit units and outputs either the H level or the L level to the D / A converter circuit 107. ing. Specifically,
The PROM circuit 105 outputs, for example, the outputs 1511 to 151m as the value of the adjustment data for the first block 181 in bit units. These outputs 1511-151 m are
The level is either H or L and indicates the value of the adjustment data in bit units. The PROM circuit 105 is provided with a PROM write terminal 151 for inputting a predetermined write voltage or current. Once the above-mentioned write voltage or current is input, all outputs of the PROM circuit 105 are at either H or L level (value of 1 or 0).
Fixed to and held in. D / A converter circuit 107
Are the first to nth blocks 181 in the adjusted circuit 108.
To 18n, the first to nth blocks 171 to 17n are provided. In the D / A converter circuit 107, for example, the first block 171 outputs 15
The value of the adjustment data designated by the level of 11 to 151 m is input from the PROM circuit 105, and the analog signal 17
Convert to 01. The first block 171 outputs the analog signal 1701 to the first block 181 of the adjusted circuit 108. As a result, the first block 181 can adjust the characteristic of the output amplitude in the semiconductor integrated circuit 101, for example, to suppress the variation.

Here, the detailed configuration of the PROM circuit 105 will be described with reference to FIG. In the following description, for simplification of the description, a circuit configuration that stores the value of the adjustment data of the first bit to the third bit for the first block 181 will be described as an example. FIG. 11 is a circuit diagram showing a detailed configuration of a part of the PROM circuit shown in FIG. In FIG. 11, for example, the circuit configuration for storing the value of the adjustment data of the first bit is one Zener diode 2
511, three current sources 7511 to 7513, eight transistors 8511 to 8518, and three resistors 9511.
˜9513. The output 2611 from the serial / parallel conversion circuit 102 (FIG. 10) is configured to be input to the base of the transistor 8511 and the base of the transistor 8517 via the resistors 9511 and 9512, respectively. A predetermined write voltage or current from the PROM write terminal 151 causes a transistor 851 to a Zener diode 2511 connected in the opposite direction to the PROM write terminal 151.
It is configured to input via 3. That is, the cathode of the Zener diode 2511 is the transistor 851.
3 is connected to the emitter and the anode is the transistor 85
It is connected to 12 collectors. The value of the adjustment data of the first bit is stored with the level of the output 1511 fixed to either the H or L level depending on the state of the Zener diode 2511.

More specifically, when the Zener diode 2511 is changed from the high impedance state to the low impedance state by the write voltage or current, the value of the adjustment data of the first bit is written and the level of the output 1511 is written. Is fixed at H. On the other hand, when the Zener diode 2511 is maintained in a high impedance state, the level of the output 1511 is fixed to L without writing the value of the adjustment data of the first bit. Similarly, 2
The circuit configuration for storing the value of the adjustment data of the bit is Zener diode 2521, current sources 7521 to 7523,
Transistors 8521 to 8528 and resistors 9521 to
It is composed of 9523. The circuit configuration for storing the value of the adjustment data of the third bit is composed of a Zener diode 2531, current sources 7531-7533, transistors 8531-8538, and resistors 9531-9533.

The operation of the conventional semiconductor integrated circuit 101 will be specifically described below with reference to FIGS. 10 and 11.
In the following description, for simplification of the description, the operation of selecting and writing the value of the first bit for the first block 181 will be mainly illustrated and described. First, the selection operation for selecting the optimum write value before writing the adjustment data value in the PROM circuit 105 will be described. When performing this selection operation, a predetermined write voltage or current is not supplied to the PROM write terminal 151. Therefore, PRO
Inside the M circuit 105, the Zener diode 2511
Is a high impedance state, and the transistor 851
The base 4 and the emitter of 4 are also in a high impedance state. Therefore, all the current from the current source 7512 flows toward the transistor 8515. In this situation,
Output 2 from the adjustment data and bit selection output circuit 26
When 611 is H, the base of the transistor 8517 is H and the collector of the transistor 8517, that is, the base of the transistor 8518 is L. Therefore, the collector of the transistor 8518 becomes H and the output 1511 also becomes H.

On the other hand, when the output 2611 is L, the base of the transistor 8517 is L and the collector of the transistor 8517, that is, the base of the transistor 8518 is H. Therefore, transistor 8518
The collector of L becomes L and the output 1511 also becomes L.
Thus, in the conventional semiconductor integrated circuit 101, the output 2
By changing the level of 611, the output 1511
The optimum value can be selected by changing the level of. Then, in the conventional semiconductor integrated circuit 101, the same operation is performed for the values of the other bits, and the characteristics of the first to nth blocks 181 to 18n of the adjusted circuit 108 can be adjusted, respectively, which is optimal. Adjustment data can be selected.

Next, the operation of writing the value of the adjustment data in the PROM circuit 105 will be described. PROM circuit 10
At the time of writing the adjustment data to 5, the adjustment data and bit selection output circuit 26 outputs only the bit of the block to be written to L and outputs the other bits to H, as described above. As a result, the PROM circuit 105
In the inside of the transistor, since the output 2611 is L, the transistor 85
11 is cut off, and all the current from the current source 7511 is supplied to the base of the transistor 8512. As a result, the transistor 8512 is turned on, the collector of the transistor 8512 is saturated, and a low impedance state is set. In this state, PROM writing terminal 1
When a predetermined write voltage or current is supplied to 51, the Zener diode 2511 changes from a high impedance state to a low impedance state. At this time, since the output 2612 is H, the transistor 8521 is on, and the collector of the transistor 8521 is L. Therefore, the transistor 8522 is cut off, and the collector of the transistor 8522 is in a high impedance state. Therefore, even if a predetermined write voltage or current is applied to the PROM write terminal 151, the Zener diode 2521 remains in a high impedance state and does not change. Similarly, the Zener diodes of the other bits are also kept in the high impedance state. That is, the values of other bits are not written.

Next, the operation when the semiconductor integrated circuit 101 is normally used after the value of the adjustment data is written in the PROM circuit 105 will be described. When this operation is performed, all outputs of the adjustment data and bit selection output circuit 26 are L. Therefore, in the PROM circuit 105, for example, in FIG.
521 and 8531 are cut off, and the transistors 8512, 8522, and 8532 are turned on.
When only the value of the first bit for the first block 181 is written, the Zener diode 2511 is in a low impedance state, so that the current from the current source 7512 flows toward the transistor 8514 and the transistor 8515 does. Does not flow to. Therefore, the transistor 8
518 is cut off, and the output 1511 becomes H.

On the other hand, since the Zener diode 2521 is in a high impedance state, the current from the current source 7522 does not flow to the transistor 8524 but to the transistor 8525. Therefore, the transistor 85
28 is turned on, the collector of the transistor 8528 is saturated, and the output 1512 becomes L. By the same reason, the output 1513 of the third bit also becomes L. As described above, when the semiconductor integrated circuit 101 is normally used after the value of the adjustment data is written in the PROM circuit 105, the P bit is changed to P when the state of the Zener diode is changed.
The output of the ROM circuit 105 is always H, and the output of the PROM circuit 105 is always L for a bit whose zener diode state has not changed. As a result, the characteristics of the first to nth blocks 181 to 18n are adjusted to the optimum ones.

As described above, in the conventional semiconductor integrated circuit 101, the adjustment data and bit selection output circuit 26 is provided.
However, it is configured to instruct the value of the adjustment data in bit units for all blocks to be adjusted.

[0014]

In the conventional semiconductor integrated circuit 101 as described above, after the value of the adjustment data is written in the PROM circuit 105, the output of the PROM circuit 105 is changed from the high level by the external control from the CPU 100. There was a problem that it could not be changed to low level. Specifically, before writing the value of the adjustment data to the PROM circuit 105, for example, on the assumption that no current flows through the transistor 8514, the transistor 8517 is turned on / off by the serial control signal from the CPU 100 and output. It was possible to change the level of 1511. However, this conventional semiconductor integrated circuit 1
In 01, when the value of the adjustment data was written to bring the Zener diode 2511 into a low impedance state, the transistor 8518 was cut off regardless of the level of the output 2611 based on the serial control signal. Therefore, in the conventional semiconductor integrated circuit 101, the output 151
It was not possible to forcibly change to low level after setting 1 to high level, and it was impossible to readjust the value of the adjustment data. As a result, the conventional semiconductor integrated circuit 1
In 01, the standard characteristics inside the IC could not be readjusted.

The present invention has been made in order to solve the above-mentioned conventional problems, and even after the value of the adjustment data is written in the ROM (PROM circuit), it is bit-unit-wise by using the external control. An object of the present invention is to provide a semiconductor integrated circuit capable of optimizing the value of written adjustment data.

[0016]

This onset bright [Means for solving problems], a semiconductor integrated circuit incorporating a plurality of blocks for adjusting ROM, and a plurality of standard characteristics respectively for adjusting the variation in the standard characteristics of the internal IC, the semiconductor integrated circuit includes an input circuit, said control signal includes a ROM control and external control switching signal and the block selection signal and a block selection decode circuit for generating a decode signal by decoding for inputting a control signal from the outside, And one of the plurality of blocks is selected based on the decode signal, and the ROM data from the ROM and the external control data included in the control signal are switched and output to the selected block. ROM data / external control data selector switch and the latch circuit, Bei example, said
The block selection decoding circuit is based on the ROM control / external control.
Control signal is ROM mode and the control signal
Outputs a low level when the
M control / external control switching signal is in external control mode or above
High level when the control signal is in light mode
OR circuit for outputting and decoding the block selection signal
The first logic circuit group that becomes active at low level
And the output of the OR circuit and the output of the first logic circuit group.
The ROM having the NAND circuit group for each input,
Data / external control data changeover switch and latch circuit
Stores the ROM data and the external control data in the R
Second theory of switching by OM control / external control switching signal
Latch input to the output of the logic circuit group and the NAND circuit group
Input the output of the second logic circuit group to the D input respectively.
And a latch circuit group for applying a force . With this configuration, it is possible to readjust and preset only the bit value of a necessary portion by the delivery destination or the end user while making the adjustment by ROM data at the delivery destination as standard.

[0017]

[0018]

A semiconductor integrated circuit according to another aspect of the invention is
A delay circuit is connected to the ROM data / external control data changeover switch and latch circuit so that the ROM data / external control data changeover switch and latch circuit selects a block before inputting external control data. With such a configuration, for example, when the latch input of the latch circuit is in a high level and in an active state, switching of the external control data becomes slower than the fall of the latch input, and malfunction can be prevented in advance.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments showing a semiconductor integrated circuit of the present invention will be described below with reference to the drawings.

<< First Embodiment >> FIG. 1 is a circuit block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. In FIG. 1, a semiconductor integrated circuit 1 of this embodiment
Is connected to the CPU 9 and converts a serial control signal from the CPU 9 into a parallel signal.
The parallel conversion circuit 2 is provided. The serial / parallel conversion circuit 2 changes the output level to a high level (hereinafter, also referred to as “H”) or a low level (hereinafter, also referred to as “L”) based on the input serial control signal. Read switching output circuit 21, RO
An M control / external control switching signal output circuit 22, a block selection output circuit 23, a bit selection output circuit 24, and an external control data output circuit 25 are provided. Further, the semiconductor integrated circuit 1 of the present embodiment has a write / read switching output circuit 21, a ROM control / external control switching signal output circuit 2.
2, a block selection decoding circuit 3 connected to the block selection output circuit 23, a PROM write control signal decoding circuit 4 connected to the block selection decoding circuit 3, the write / read switching output circuit 21, and the bit selection output circuit 24, And a PROM circuit 5 connected to the PROM write control signal decoding circuit 4. Further, in the semiconductor integrated circuit 1 of this embodiment, the block selection decoding circuit 3, the PROM circuit 5, the ROM control /
ROM data / external control data changeover switch and latch circuit 6 connected to the external control changeover signal output circuit 22 and external control data output circuit 25, and D connected to the ROM data / external control data changeover switch and latch circuit 6. An A / A converter circuit 7 and an adjusted circuit 8 connected to the D / A converter circuit 7 are provided.

The write / read switching output circuit 21 includes
The output 211 is used as the block selection decoding circuit 3 and the PROM.
The write control signal is output to the decode circuit 4 to output the PROM.
Instructing switching of data writing (write mode) or reading (read mode) in the circuit 5. This data is data for adjusting the standard characteristic inside the semiconductor integrated circuit 1, for example, the variation of the output amplitude characteristic and the output frequency characteristic, and is the first and second data provided in the adjusted circuit 8.
It is supplied to blocks 81 and 82. The ROM control / external control switching signal output circuit 22 outputs an output 221 which is a ROM control / external control switching signal to the block selection decoding circuit 3, the ROM data / external control data changeover switch and the latch circuit 6. As a result, the ROM data / external control data changeover switch and the latch circuit 6 switch the data between the ROM mode and the external control mode.
The block selection output circuit 23 outputs outputs 231 to 233 which are block selection signals to the block selection decoding circuit 3 to select and instruct a block for writing or reading data. The bit selection output circuit 24 outputs the outputs 241 and 242 to the PROM write control signal decoding circuit 4 to select and instruct a bit of data. The external control data output circuit 25 outputs the outputs 251 to 253 to R
It outputs to the OM data / external control data changeover switch and the latch circuit 6, and transmits the external control data from the outside included in the serial control signal.

Since the number of outputs of the block selection output circuit 23 is configured to be 3 bits (outputs 231 to 233), the number of outputs of the block selection decoding circuit 3, that is, the number of controllable blocks is 8 (= maximum). 2 ³ ) It becomes a block. However, in the following description, in order to simplify the description, the blocks to be controlled are the first and second blocks 81,
There are two blocks 82. Similarly, since the number of outputs of the bit selection output circuit 24 is configured to be 2 bits (outputs 241 and 242), the number of outputs of the external control data output circuit 25,
That is, the maximum number of controllable data bits is 4 (=
Up to 2 ² ) bits are possible, but 3 bits.

The block selection decoding circuit 3 includes the RO
The M control / external control switching signal and the block selection signal are decoded, and the outputs 31 and 32 are PRO as decoding signals.
The M write control signal is output to the decoding circuit 4. These outputs 31 and 32 are the first block 6 provided in the ROM data / external control data changeover switch and latch circuit 6.
It is also output to 1 and 62, respectively. In the write mode, the PROM write control signal decoding circuit 4 decodes the outputs 31 and 32 and the outputs 241 and 242 to output the outputs 411 to 413 for the first block 81 and the outputs 421 to 423 for the second block. Output to the PROM circuit 5. The PROM circuit 5 includes the first and second blocks 8
The data values for 1 and 82 are stored in bit units, and either the H level or the L level is output to the D / A converter circuit 7. Specifically, the PROM circuit 5 outputs 51 as the value of the ROM data for the first block 81, for example.
1 to 513 are output in bit units. These outputs 51
1 to 513 are levels of either H or L,
Specify the data value in bit units. The PROM circuit 5 is provided with a PROM write terminal 51 for inputting a predetermined write voltage or current. When the above-mentioned write voltage or current is input, all the outputs of the PROM circuit 5 are fixed to either H or L level (value of 1 or 0) and held.

Now, referring to FIG. 2, the PROM circuit 5
The detailed configuration of will be described. In the following explanation,
For simplification of description, a circuit configuration for storing the values of the first to third bits of ROM data for the first block 81 will be exemplified and described. Further, in order to facilitate comparison with the conventional example shown in FIG. 11, an example in which the PROM circuit 5 is configured by using the Zener zap method will be described.
FIG. 2 is a circuit diagram showing a detailed configuration of a part of the PROM circuit shown in FIG. In FIG. 2, for example, the circuit configuration for storing the value of the ROM data of the first bit has one Zener diode 3511 and three current sources 4511-4.
513, eight transistors 5511 to 5518, and two resistors 6511 and 6512.
The output 411 from the PROM write control signal decoding circuit 4 (FIG. 1) is supplied to the transistor 5 via the resistor 6511.
It is configured to be input to the base of 511. PR
A predetermined write voltage or current from the OM write terminal 51 is configured to be input to the Zener diode 3511 connected in the opposite direction to the PROM write terminal 51 via the transistor 5513. That is,
The cathode of the Zener diode 3511 is connected to the emitter of the transistor 5513, and the anode is connected to the collector of the transistor 5512. The collector current flowing when the transistor 5518 is in the ON state is set to a value larger than the current value of the current source 4513.
Thus, the output 511 is L when the transistor 5518 is in the ON state, and the output 511 is H when the transistor 5518 is in the OFF state. The levels of these outputs 511 are fixed and stored according to the state of the Zener diode 3511.

More specifically, when the Zener diode 3511 is changed from a high impedance state to a low impedance state by the write voltage or current, the value of the ROM data of the first bit is written and the level of the output 511 is written. Is fixed at H. On the other hand, when the Zener diode 3511 is maintained in a high impedance state, the value of the ROM data of the first bit is not written and the level of the output 511 is fixed at L. Similarly, 2
The circuit configuration for storing the ROM data value of the bit is the Zener diode 3521 and the current sources 4521 to 452.
3, transistors 5521 to 5528, and a resistor 652
1, 6522. The circuit configuration for storing the value of the ROM data of the third bit is the Zener diode 3531, the current sources 4531 to 4533, the transistors 5531 to 5538, and the resistors 6531 and 653.
It is composed of two.

Returning to FIG. 1, the ROM data / external control data changeover switch and the latch circuit 6 are provided in correspondence with the first and second blocks 81 and 82 in the adjusted circuit 8, respectively. Two blocks 61 and 62 are provided.
The ROM data / external control data changeover switch and the latch circuit 6 includes a decode signal from the block selection decode circuit 3 and a ROM control / external control changeover signal output circuit 22.
R from the PROM circuit 5 based on the output 221 from
The OM data and the external control data from the external control data output circuit 25 are switched and output to the D / A converter circuit 7. Specifically, for example, the first block 61 outputs the outputs 511 to 511 from the PROM circuit 5 based on the output 31 from the block selection decoding circuit 3 and the output 221 from the ROM control / external control switching signal output circuit 22. 513 or outputs 251 and 2 from the external control data output circuit 25
53 is selected and output as outputs 611 to 613. R
The OM data / external control data changeover switch and the latch circuit 6 have a function of retaining data (latch function), as will be described later, and in the external control mode, the first and second blocks 61, The data of the blocks of 62 which are not selected by the decode signal are held. As described above, in the semiconductor integrated circuit 1 of this embodiment, the ROM data / external control data changeover switch and the latch circuit 6 switch between the ROM control and the external control based on the decode signal from the block selection decode circuit 3. Therefore, it is not necessary to provide the PROM circuit 5 with an external control function for selecting the optimum write value before writing the adjustment data in the PROM circuit 5.

The D / A converter circuit 7 includes an adjusted circuit 8
The first and second blocks 71 and 72 are provided corresponding to the first and second blocks 81 and 82, respectively. In the D / A converter circuit 7, for example, the first block 71 inputs a data value designated by the levels of the outputs 611 to 613 from the ROM data / external control data changeover switch and the latch circuit 6 and converts it into an analog signal 701. The first block 71 outputs the analog signal 701 to the first block 81 of the adjusted circuit 8. As a result, the first block 81 can adjust the characteristic of the output amplitude in the semiconductor integrated circuit 1, for example, and suppress the variation thereof.

The operation of the semiconductor integrated circuit 1 of this embodiment will be described below with reference to FIGS. Figure 3
3 is a timing chart showing the operation of the semiconductor integrated circuit shown in FIG. 1. In the following description, the outputs 411 to 413, 4 from the PROM write control signal decoding circuit 4 will be described.
It is assumed that 21 to 423 are active at a low level and outputs from all other circuits are active at a high level. First, the PROM circuit 5
The operation in the external control mode for selecting the optimum write value before writing will be described below. In the external control mode, as shown in FIG. 3A, the ROM control / external control switching signal output circuit 22 of the serial / parallel conversion circuit 2 is output.
Output 221 of H becomes H indicating the external control mode. At this time, the output 211 of the write / read switching output circuit 21 becomes L, which indicates the read mode in which the writing of data to the PROM circuit 5 is prohibited. Further, the block selection output circuit 23 selects a block designated by the serial control signal from the CPU 9 and activates the output of only the selected block at a high level. That is, as shown in FIG.
33, 232, and 231 are set to L, L, and H, and the first block 81 (= 001) is selected. As a result, the block selection decoding circuit 3 sets the output 31 to H and the output 32 to L.
Leave it unchanged.

Subsequently, in the ROM data / external control data changeover switch and latch circuit 6, based on the output 31 and the output 221, the outputs 511 to 511 from the PROM circuit 5 are outputted.
The outputs 251 to 253 from the external control data output circuit are selected without selecting 513. The ROM data / external control data changeover switch and the latch circuit 6 have outputs 251 ...
The outputs 611 to 613 are changed according to 253. At this time, since the output 32 from the block selection decoding circuit 3 is L, the ROM data / external control data changeover switch and the latch circuit 6 do not change the outputs 621 to 623. Thus, in the external control mode, the block is selected and the output 25 from the external control data output circuit is selected.
1 to 253 are RO as data for the selected block
It is output from the M data / external control data changeover switch and latch circuit 6 to the D / A converter circuit 7. afterwards,
The D / A converter circuit 7 converts the input data into an analog signal and outputs it to the first block 81. Then, in the first block 81, the variation of the characteristics can be adjusted, and the optimum value can be selected.

Next, the operation of writing ROM data to the PROM circuit 5 will be described. In this behavior,
The output 211 of the write / read switching output circuit 21 is H, that is, the write mode, and the output 221 of the ROM control / external control switching output circuit 22 is L, that is, R.
The OM mode is set. Similarly to the external control mode, the block selection output circuit 23 selects a block designated by the serial control signal from the CPU 9 and activates the output of only the selected block at a high level. For example, when the first block 81 is selected, the block selection decoding circuit 3 sets the output 31 to H, as shown in FIG. Then, in the PROM write control signal decoding circuit 4, the output 31 of the block selection decoding circuit 3 and the outputs 241 to 242 of the bit selection output circuit 24.
And decode. Specifically, as shown in FIG. 3B, the outputs 241 and 242 of the bit selection output circuit 24 are output.
Are both H, and the third bit is selected. The output 31 of the book selection decoding circuit 3 is H,
The first block 81 is selected. Therefore, PRO
In the M write control signal decoding circuit 4, as a result of decoding the output 31 and the outputs 241, 242, only the output 413 is activated at the low level and the third bit of the data for the first block 81 is selected. The outputs 411, 412, 412 of the PROM write control signal decoding circuit 4 are
When a predetermined write voltage or current is applied to the PROM write terminal 51 when 413 is H, H, L, the value of the third bit of the data for the first block 81 is P.
It is written in the ROM circuit 5. As a result, FIG. 3 (b)
The output 513 becomes H as shown in FIG.

More specifically, in the PROM circuit 5, the output 4 of the PROM write control signal decoding circuit 4 is provided.
When only 13 becomes active at a low level, the transistor 5531 is cut off. As a result, the current source 45
All the current of 31 is supplied as the base current of the transistor 5532, and the transistor 5532 is turned on. Then, the collector of the transistor 5532 is saturated and is in a low impedance state. At this time, PROM
When a predetermined write voltage or current is applied to the write terminal 51, the Zener diode 3531 changes from a high impedance state to a low impedance state. At this time, since the output 412 of the PROM write control signal decoding circuit 4 is H, the collector of the transistor 5521 is L, the transistor 5522 is cut off, and the collector is in a high impedance state. Therefore, the Zener diode 3521 remains in a high impedance state even when a predetermined write voltage or current is applied. Similarly, the Zener diodes of the other bits and blocks are also kept in the high impedance state, and no data is written.

Next, the operation in normal use after writing data in the PROM circuit 5 will be described. In this normal use, as shown in FIG. 3C, the output 211 of the write / read switching output circuit 21 becomes L, and PR
A read mode is instructed to prohibit writing of data to the OM circuit 5. Further, the output 221 of the ROM control / external control switching output circuit 22 also becomes L to indicate the ROM mode. As a result, in the ROM data / external control data changeover switch and latch circuit 6, the PROM circuit 5
Select ROM data from. Specifically, as shown in (c) of FIG. 3, since only the third bit for the first block 81 is written, only the output 613 of the ROM data / external control data changeover switch and the latch circuit 6 is H.
Becomes

Next, the operation in the case of returning to the external control mode again after the operation of writing data in the PROM circuit 5 will be described. In FIG. 3D, first, RO
When the output 221 of the M control / external control switching output circuit 22 is returned to the external control mode by setting it to H, the ROM data / external control data changeover switch and the latch circuit 6 only output the external control data of the block selected by the block selection decoding circuit 3. It operates to select the external control data from the output circuit 25. Specifically, as shown in FIG. 3D, the block selection output circuit 23 outputs, for example, the output 233.
232 and 231 are set to L, L, and H, and the first block 81
When (= 001) is selected, the output 31 of the block selection decoding circuit 3 is H. Therefore, in the ROM data / external control data changeover switch and latch circuit 6, the outputs 621 to 623 are output from the PROM circuit 5 to the ROM.
The data is left as it is, and only the outputs 611 to 613 are changed according to the outputs 251 to 253 from the external control data output circuit 25. At this time, since the ROM data / external control data changeover switch and the latch circuit 6 have a latch function, the outputs 31 and 32 change and the selected block changes from the first block 81 to the second block 82. However, the value of the external control data for the first block 81 is retained. When the first block 81 is selected again in the external control mode and the outputs 251 to 253 of the external control data output circuit 25 are given different values, the held external control data is in the normal mode or the ROM mode. It is cleared when returning to the above or when the power supply is restarted, but otherwise it is retained.

Specifically, FIG. 3D and FIG.
(E), the outputs 233, 232 and 231 of the block selection output circuit 23 are changed from L, L, H to L, H, L.
When the block selected from the first block 81 (= 001) to the second block 82 (= 010) changes, the outputs 31 and 3 of the block selection decoding circuit 3 change.
2 changes from H, L to L, H, respectively. At this time,
In the ROM data / external control data changeover switch and latch circuit 6, the output 6 which is the data for the first block 81 is output.
Reference numerals 13, 612 and 611 hold the values L, H and L before change, respectively. Then, as shown in (e) of FIG.
The M data / external control data changeover switch and latch circuit 6 receives data 251 to 253 from the external control data output circuit 25 as data for the second block 82.
Only the outputs 621 to 623 are changed. In this way, when performing external control of a plurality of blocks, another block may be continuously selected in the external control mode. The operation shown in (e) of FIG. 3 is an operation of selecting the adjustment data before writing to the PROM circuit 5 as the data for the second block 82. Therefore, in the semiconductor integrated circuit 1 of the present embodiment, the external control mode can be independently performed regardless of the data writing operation to the PROM circuit 5.

Further, in the PROM circuit 5, (c) of FIG.
The operation shown in FIG. 3E is in the read mode for reading the written ROM data. In this read mode, the outputs 411 to 413 of the PROM write control signal decoding circuit 4 are L, and the zener diode 35
Since 31 is in a low impedance state, the current of the current source 4532 flows to the transistor 5514 and does not flow to the transistor 5515. Therefore, the transistor 5538 is cut off and the output 51
3 becomes H. On the other hand, since the Zener diode 3521 is in a high impedance state, the current source 452
The current of 2 flows to the transistor 5525, the transistor 5528 is turned on, and the output 512 becomes L. In this way, from the PROM circuit 5, the written bit is read as H, and the unwritten bit is read as L. However, in the external control mode shown in FIGS. 3D and 3E, the ROM data from the PROM circuit 5 is first output by the output 31 of the block selection decoding circuit 3 as described above. The block 81 is selected as an external control target. Therefore, the subsequent ROM data / external control data changeover switch and the latch circuit 6 are
External control is performed according to the outputs 251 to 253 of the external control data output circuit 25 regardless of the ROM data from the PROM circuit 5. As described above, in the semiconductor integrated circuit 1 of the present embodiment, the PROM circuit 5 simply needs to read the write value in the read mode regardless of before and after writing the data, and does not need a circuit for external control.

As described above, in the semiconductor integrated circuit 1 of this embodiment, the serial / parallel conversion circuit 2 for converting the serial control signal from the CPU 9 into parallel signals and the RO signal.
External control from the serial / parallel conversion circuit 2 with respect to the block selection decoding circuit 3 that decodes the M control / external control switching signal and the block selection signal and outputs the decoding signal, and the block selected using the decoding signal. A ROM data / external control data changeover switch for switching between data and ROM data from the PROM circuit 5 and latching the value and a latch circuit 6 are provided. As a result, in the semiconductor integrated circuit 1 of the present embodiment, the PROM
Even after the data is written in the circuit 5, the data can be changed bit by bit only by external control of the selected block. As a result, in the semiconductor integrated circuit 1 of the present embodiment, the PROM circuit 5 does not require adjustment at the customer's destination as a standard, but if necessary and with a minimum increase in the CPU load, the necessary parts are not required. Only the bit value can be readjusted and preset by the customer or end user.

In the above description, the number of outputs of the block selection output circuit 23 is 3 bits, the number of outputs of the block selection decoding circuit 3, that is, the number of controllable blocks is 2, and the number of outputs of the bit selection output circuit 24 is. 2 bits, the number of outputs of the external control data output circuit 25, that is, the number of controllable bits is 3 bits. However, in the semiconductor integrated circuit 1 of the present embodiment, the number of outputs of the block selection output circuit 23 is j bits, and the block selection decoding circuit 3
, The number of controllable blocks is n blocks, the number of outputs of the bit selection output circuit 24 is k bits, and the number of outputs of the external control data output circuit 25, that is, the number of controllable bits is m bits. is there. That is,
As shown in FIG. 4, it is possible to configure the semiconductor integrated circuit 1 of this embodiment. In FIG. 4, the block selection output circuit 23, the bit selection output circuit 24, and the external control data output circuit 25 output an output 23j, an output 24k, and an output 25m, respectively. Further, the block selection decoding circuit 3, the PROM write control signal decoding circuit 4, the PROM circuit 5, the ROM data / external control data changeover switch and latch circuit 6, and the D / A converter circuit 7 have outputs 3n, 4nm, and 4nm, respectively. 51
It outputs m to 5 nm, output 61 m to 6 nm, and output 70n. Further, at this time, j, k, m, and n are integers, and the values of j and k can be set to arbitrary values, and n is n.
≦ 2 ^j and m can be set to arbitrary values within the range of m ≦ 2 ^k .

<Second Embodiment> FIG. 5 is a circuit diagram showing a detailed structure of a part of a block selection decode circuit and a PROM write control signal decode circuit in a semiconductor integrated circuit according to a second embodiment of the present invention. is there. FIG. 6 shows a second embodiment of the present invention.
FIG. 6 is a circuit diagram showing a detailed configuration of a part of a ROM data / external control data changeover switch and a latch circuit in the semiconductor integrated circuit of the example of FIG. In this embodiment, a specific configuration example in which the block selection decoding circuit, the PROM write control signal decoding circuit, the ROM data / external control data changeover switch and the latch circuit are configured by using a logic circuit will be described. The other parts are the same as those in the first embodiment, and the duplicated description thereof will be omitted. As shown in FIG. 5, the block selection decoding circuit 3
Is an OR element 1301 and inverter elements 1311 to 13
13, and NAND elements 1321, 1322, 133
1, 1332. The PROM write control signal decoding circuit 4 includes inverter elements 1411, 141.
2, NAND elements 1431 to 1436, and AND elements 1421 to 1423, 1441 to 1446. As shown in FIG. 6, the ROM data / external control data changeover switch and the latch circuit 6 includes an inverter element 16
01, NAND elements 1611 to 1616, 1621-1
626, 1631 to 1636, and a latch circuit 1641
.About.1646.

The operation of the semiconductor integrated circuit of the second embodiment configured as described above will be described with reference to FIGS. 5 and 6. In the following description, first, a case where no delay occurs in each element will be described with reference to the timing chart shown in FIG. Further, as in the first embodiment, outputs 411 to 413 and 421 to 423 from the PROM write control signal decoding circuit 4 are active at a low level, and outputs from all other circuits are the same. Described as being active at a high level. First, the operation in the external control mode for selecting the optimum write value before writing to the PROM circuit 5 will be described. In this external control mode, the output 221 from the ROM control / external control switching signal output circuit 22 is H, and OR
The output of the element 1301 also becomes H. At this time, the output of only the block selected by the block selection output circuit 23 becomes active at the high level. That is, (a) of FIG.
, The outputs 233, 232, 231 are L,
L and H, all inputs of the NAND element 1321 are H and its output is L. Therefore, the NAND element 1
The output 31 of 331 becomes H. In this way, the first block 81 is selected. Further, in the NAND element 1322, the output 232 of the three inputs is L, so the output thereof is H. Further, since the output of the OR element 1301 is also H, the output 32 of the NAND element 1332 is L.
As a result, the second blocks 82 other than the first block 81 are not selected.

Next, in the ROM data / external control data changeover switch and latch circuit 6, since the output 221 from the ROM control / external control changeover signal output circuit 22 is H, the outputs of the NAND elements 1621-1623 are external. It becomes a value obtained by inverting the outputs 251 to 253 from the control data output circuit 25. Further, since the output of the inverter element 1601 is L, the outputs of the NAND elements 1611 to 1613 are H. Therefore, the NAND elements 1631 to
The outputs of 1633 are NAND elements 1621-1623, respectively.
Output is inverted to have the same value as the outputs 251 to 253. At this time, since the H of the output 31 is input to the L inputs of the latch circuits 1641 to 1643, the latch circuit 164
The outputs 611 to 613 from the Q outputs 1 to 1643 also have the same values as the outputs 251 to 253, respectively. In this way, the outputs 611 to 613 change in association with the outputs 251 to 253, the external control data is selected as the data for the first block 81, and is output to the D / A converter circuit 7. At this time, as described above, since the output 32 of the block selection decoding circuit 3 is L and the second block 82 is not selected, the latch circuits 1644 to 1646 do not operate and the output from the Q output thereof. 621 to 623 do not change.

Next, the operation of writing ROM data to the PROM circuit 5 will be described. In this behavior,
The output 211 of the write / read switching output circuit 21 becomes H, that is, the write mode, and the output 221 of the ROM control / external control switching signal output circuit 22 becomes L, that is, the ROM mode. Also in this case, as in the external control mode, the output of the OR element 1301 is H, so that the output of only the block selected by the block selection output circuit 23 becomes active at a high level. That is, NAN
The output 31 of the D element 1331 also becomes H, and the first block 81 is selected. Then, the PROM write control signal decoding circuit 4 causes the block selection decoding circuit 3
Output 31 and outputs 241, 2 of the bit selection output circuit 24
Decoding with 42. As shown in FIG. 3B, outputs 241 and 242 from the bit selection output circuit 24
When both are H, the outputs of the AND elements 1421 and 1422 are L, the output of the AND element 1423 is H, and the third bit is selected. Since the output 31 of the NAND element 1331 is H, the NAND element 1433 and A
Both outputs of the ND element 1443 become L. Also, NA
In the ND elements 1431, 1432, 1434 to 1436, one of the two inputs is L, so each output is L. Therefore, the AND element 144
The output of 1, 1442, 1444 to 1446 becomes H.
Since the outputs 411 to 413 and 421 to 423 from the PROM write control signal decoding circuit 4 become active at the low level as described above, the AND element 1
When only the output of 443 is L, it means that the third bit for the first block 81 is selected. When a predetermined write voltage or current is applied to the PROM write terminal 51 in this state, only the value of the third bit for the first block 81 is written in the PROM circuit 5. As a result,
The output 513 becomes H as shown in FIG.

Next, an operation in normal use after writing data in the PROM circuit 5 will be described. In this normal use, as shown in FIG.
Since the output 211 from the read switching output circuit 21 and the output 221 from the ROM control / external control switching signal output circuit 22 are both L, the output of the OR element 1301 is also L. Therefore, the outputs 31 and 32 of the NAND elements 1331 and 1332 both become H. At this time, in the ROM data / external control data changeover switch and latch circuit 6, since the output 221 is L, the NAND element 1621
Each output of ˜1626 becomes H. Further, since the output of the inverter element 1601 is H, the NAND element 1611
The outputs of 1616 are output 51 from the PROM circuit 5, respectively.
It is a value obtained by inverting 1 to 523. Therefore, NAND
The outputs of the elements 1631 to 1636 are the NAND elements 1 respectively.
The outputs of 611 to 1616 are inverted to output 511 to 52.
It will be the same value as 3. At this time, the latch circuits 1641 to 1
Since the outputs 31 and 32 which are H are input to the L input of 643 and the L inputs of the latch circuits 1644 to 1646, respectively, the outputs 611 to 613, 621 to 623 from the Q outputs of the latch circuits 1641 to 1646 are also input. Also PR
Outputs 511 to 513, 521 to 523 from the OM circuit 5
It will be the same value as. Thus, in normal use, the ROM
Data / external control data changeover switch and latch circuit 6
RO from the PROM circuit 5 in all blocks
M data is selected. Then, the ROM data from the PROM circuit 5 is output to the D / A converter circuit 7. As a result, each adjustment of the first and second blocks 81 and 82 is performed by the ROM data held in the PROM circuit 5. As shown in FIG. 3C, the first block 8
Since only the third bit for 1 is written in the PROM circuit 5, only the output 613 of the ROM data / external control data changeover switch and latch circuit 6 is H. still,
When the serial / parallel conversion circuit 2 is configured so that the output 211 of the writing / reading switching output circuit 21 and the output 221 of the ROM control / external control switching signal output circuit 22 become L when the power is turned on, selection from the CPU 9 It is possible to set the default mode to the normal mode (ROM data read mode) without waiting.

Next, the operation in the case of returning to the external control mode again after the operation of writing data in the PROM circuit 5 will be described. As shown in FIG. 3D, R
Output 221 of OM control / external control switching signal output circuit 22
When H is set to H and the external control mode is returned to again, the OR element 1
The output of 301 also becomes H. At this time, as in the case before the data is written in the PROM circuit 5, the block selection output circuit 23
The output of only the block selected by becomes active at the high level. That is, as shown in FIG. 3D, the outputs 233, 232, and 231 are L, L, and H,
The inputs of the NAND element 1321 all become H, and the output thereof becomes L. Therefore, the output of the NAND element 1331 becomes H. In this way, the first block 81 is selected. In the NAND element 1322, output 2 out of 3 inputs
Since 32 is L, its output is H. Also, OR
Since the output of the element 1301 is also H, the NAND element 13
The output 32 of 32 becomes L. In this way, the second blocks 82 other than the first block 81 are not selected.

In the ROM data / external control data changeover switch and latch circuit 6, the output 221 from the ROM control / external control changeover signal output circuit 22 is H, so NA
The outputs of the ND elements 1621 to 1626 are values obtained by inverting the outputs 251 to 253 from the external control data output circuit 25, respectively. Since the output of the inverter element 1601 is L, the outputs of the NAND elements 1611 to 1616 are H.
Becomes Therefore, the NAND elements 1631 to 1633 are
Output is the same as the outputs 251 to 253 by inverting the outputs of the NAND elements 1621 to 1623, respectively. At this time, since the H of the output 31 is input to the L inputs of the latch circuits 1641 to 1643, the latch circuits 1641 to 16
Outputs 611 to 613 from the Q output of 43 are also output 25, respectively.
It has the same value as 1 to 253. On the other hand, the latch circuit 1644
Since the L input of the output 32 is input to the L inputs of ˜1646, the outputs 621 to 623 from the Q outputs of the latch circuits 1644 to 1646 are latched with the ROM data shown in FIG. Output 52 from each PROM circuit 5
It holds the same value as 1 to 523. Thus, output 61
1 to 613 change in conjunction with the outputs 251 to 253,
External control data is selected as data for the first block 81 and output to the D / A converter circuit 7. Also,
At this time, as described above, since the output 32 of the block selection decoding circuit 3 is L and the second block 82 is not selected, the latch circuits 1644 to 1646 do not operate, and the outputs 621 to 621 from its Q output. 623 outputs the same value as the ROM data and does not change.

As shown in (d) of FIG. 3 and (e) of FIG. 3, outputs 233 from the block selection output circuit 23.
When 232 and 231 change from L, L, H to L, H, L respectively, the output of the NAND element 1321 changes from L to H.
, And the output of the NAND element 1322 changes from H to L. Therefore, the output 31 of the NAND element 1331 changes from H to L, and the output 32 of the NAND element 1332 changes from L to H. Further, the latch circuits 1641 to 16
Since the output 31 changed to L is input to the L input of 43, the outputs 611 to 613 from the Q output do not change and are held at L, H, and L. Latch circuit 1644-1
Since the output 32 changed to H is input to the L input of 646, the outputs 621 to 623 from the Q output thereof are the outputs of the NAND elements 1634 to 1636, that is, the output 251 from the external control data output circuit 25. It becomes the same value as ˜253. In this way, when performing external control on a plurality of blocks, another block may be selected subsequently. When returning to ROM (internal) control, write /
The output 211 from the read switching output circuit 21 and the RO
Output 22 from M control / external control switching signal output circuit 22
By setting 1 to L, the above-mentioned normal mode (ROM read mode) is set, and all blocks are set to ROM
Data / external control data changeover switch and latch circuit 6
Selects ROM data from the PROM circuit 5.

Next, with reference to FIG. 7, the operation in consideration of the delay of the element will be described. FIG. 7 is an explanatory diagram showing an operation in a transient state when the operation shown in FIG. 3D is changed to the operation shown in FIG. When the L inputs of the latch circuits 1641 to 1643, that is, the output 31 of the block selection decoding circuit 3 changes from the active state at the high level to the L level, the Q output of the latch circuit holds the value (state) immediately before that. Therefore, the blocks to be adjusted are changed from the first block 81 to the second block.
When changing to the block 82, as shown in FIG. 7A, the second block 8 from the external control data output circuit 25
The external control data for 2 is latch circuits 1641 to 1643.
Output to the L input of the latch circuits 1641 to 1643 rather than being transmitted to the D input of the block selection decoding circuit 3.
If the input is delayed, the first external control data L, H, L for the second block 82 will be transferred to the latch circuits 1641 to 1641.
1643 Q output, that is, the output 611 from the ROM data / external control data changeover switch and the latch circuit 6
It is output as 613. That is, the second block 82
The first external control data for
It is held and output as ROM data for use in. In order to prevent such an erroneous operation, in the present embodiment, FIG.
, The block selection signal (output 231) is set on the CPU 9 side so that the output 31 from the block selection decoding circuit 3 changes before the external control data output circuit 25, for example.
˜233) and the transmission timing of the external control data are controlled.

As described above, in the semiconductor integrated circuit of this embodiment, the block selection decoding circuit 3 has the ROM control / external control switching signal (output 221) in the ROM mode and the output 211 of the write / read switching output circuit 21. Includes an OR element 1301 which outputs a low level in the read mode and outputs a high level when the ROM control / external control switching signal is in the external control mode or the output 211 of the write / read switching output circuit 21 is in the write mode. There is. Further, the block selection decoding circuit 3 includes inverter elements 1311 to 1313 and NAND elements 1321, 1
A first logic circuit group constituted by 322, which decodes the outputs 231 to 233 from the block selection output circuit 23 and becomes active at a low level, and the OR element 1
The output of 301 and the NAND element 132 of the first logic circuit group
NAND element 133 having each output of 1, 1322 as an input
1, a NAND circuit group composed of 1332. Further, the ROM data / external control data changeover switch and the latch circuit 6 outputs the ROM data outputs 511 to 511.
NAND element 161 that switches 523 and outputs 251 to 253 that are external control data by output 221 from ROM control / external control switching signal output circuit 22.
1-1616, 1621-1626, 1631-163
A second logic circuit group consisting of 6 and outputs 31 and 3 from the NAND elements 1331 and 1332 of the NAND circuit group.
2 is input to the latch input (L input), and the latch circuits 1641 to 1646 are provided to input the outputs of the NANDs 1631 to 1636 of the second logic circuit group to the D input, respectively. As a result, in the semiconductor integrated circuit of this embodiment,
Even after writing the data to the PROM circuit 5, only the selected block can be changed in bit units by external control from the outside. As a result, in the semiconductor integrated circuit of the present embodiment, the PROM circuit 5 does not require adjustment at the delivery destination as a standard, but if necessary and with a minimum increase in the CPU load, bits of the required portion are set. Only the value can be readjusted and preset by the customer or end user.

<< Third Embodiment >> FIG. 8 is a circuit diagram showing a detailed structure of a part of a ROM data / external control data changeover switch and a latch circuit in a semiconductor integrated circuit of a third embodiment of the present invention. is there. In this embodiment, in the structure of the semiconductor integrated circuit, the ROM data / external control data changeover switch and the latch circuit select the block before inputting the external control data. It was connected to the changeover switch and the latch circuit. The other parts are the same as those in the second embodiment, and thus their duplicated description will be omitted. As shown in FIG. 8, in the semiconductor integrated circuit of this embodiment, the delay circuit 10 including the inverter elements 1001 to 1006 is provided between the external control data output circuit 25 and the ROM data / external control data changeover switch and the latch circuit 6. Has been. The inverter elements 1001, 1003, 1005 are connected in series to the inverter elements 1002, 1004, 1006, respectively, and output from the outputs 251 to 251 of the external control data output circuit 25.
253 are input respectively. The inverter element 1002 is the NAN of the second logic circuit group described above.
It is connected to the D elements 1621 and 1624. Similarly,
The inverter element 1004 is a NAND of the second logic circuit group.
Inverter element 1 connected to elements 1622 and 1625
006 is the NAND elements 1623, 1 of the second logic circuit group
It is connected to 626. As a result, in the semiconductor integrated circuit of the present embodiment, the ROM data / external control data changeover switch and the latch circuit 6 become the external control data output circuit 2
Before inputting the external control data from 5, the block can be selected based on the block selection signal from the block selection decoding circuit 3. As a result, in the semiconductor integrated circuit of this embodiment, the transmission timing of the block selection signal and the external control data can be optimized inside the semiconductor integrated circuit, and the load on the CPU 9 can be reduced.

The operation of the semiconductor integrated circuit of the third embodiment configured as above will be described with reference to FIGS. 8 and 9. FIG. 9 is a timing chart showing the operation of the semiconductor integrated circuit shown in FIG. As shown in FIG. 9, the outputs 251 to 253 of the external control data output circuit 25 are H,
When L, H changes to L, H, L, respectively, the outputs of the inverter elements 1002, 1004, 1006 and the D inputs of the latch circuits 1641-1643 also change.
However, the timing at which the D inputs of the latch circuits 1641 to 1643 change is determined by the delay circuit 10 from the active state in which the respective latch inputs (L inputs) of the latch circuits 1641 to 1643 are at the high level as shown in FIG. It is delayed from the timing of changing to low level. Therefore, the outputs 611 to 613 from the Q outputs of the latch circuits 1641 to 1643 do not change even if the outputs 251 to 253 are transmitted to the D inputs of the latch circuits 1641 to 1643, respectively. As a result, R for the first block 81
The OM data is retained without being accidentally rewritten with the first external control data for the second block 82.

As described above, in the semiconductor integrated circuit of the third embodiment, the delay circuit is arranged so that the ROM data / external control data changeover switch and the latch circuit 6 select the block before inputting the external control data. 10 was connected to the ROM data / external control data changeover switch and the latch circuit 6. As a result, in the semiconductor integrated circuit of the present embodiment, the transmission timing of the block selection signal and the external control data can be optimized inside the semiconductor integrated circuit, and the load on the CPU 9 can be reduced. In the above description, the example in which the delay circuit is configured by the inverter element has been described, but the delay circuit may be configured by using the filter circuit including the resistor and the capacitor. Furthermore, in the configuration of the delay circuit, an example using two inverter elements connected in series has been described, but the delay of a predetermined delay time is achieved without changing the level of each output from the external control data output circuit. Any configuration can be used. That is, the delay circuit may have a configuration in which an even number of inverter elements are connected in series so that each output described above is delayed by a predetermined delay time.

In the first to third embodiments described above, the CPU
The configuration for inputting the serial control signal from the serial / parallel conversion circuit has been described, but the present invention is not limited to this, and the control including at least the external control data, the ROM control / external control switching signal, and the block selection signal. Any input circuit that inputs a signal from the outside may be used.

[0053]

As described above, the semiconductor integrated circuit of the present invention includes an input circuit for inputting a control signal from the outside,
A block selection decoding circuit that decodes a ROM control / external control switching signal and a block selection signal included in the control signal to generate a decoding signal, and selects one block from a plurality of blocks based on the decoding signal In addition, a ROM data / external control data changeover switch for switching between ROM data from the ROM and external control data included in the control signal and outputting to the selected block, and a latch circuit are provided. With this configuration, it is possible to readjust and preset only the bit value of a necessary portion by the delivery destination or the end user while making the adjustment by ROM data at the delivery destination as standard.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration of a part of the PROM circuit shown in FIG.

FIG. 3 is a timing chart showing the operation of the semiconductor integrated circuit shown in FIG.

FIG. 4 is a circuit block diagram showing a configuration of a modified example of the semiconductor integrated circuit shown in FIG.

FIG. 5 is a circuit diagram showing a detailed configuration of a part of a block selection decoding circuit and a PROM write control signal decoding circuit in a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 6 shows R in the semiconductor integrated circuit according to the second embodiment of the present invention.
Circuit diagram showing a detailed configuration of a part of the OM data / external control data changeover switch and the latch circuit.

FIG. 7 is an explanatory diagram showing an operation in a transient state when the operation shown in FIG. 3D is changed to the operation shown in FIG.

FIG. 8 shows R in the semiconductor integrated circuit according to the third embodiment of the present invention.
Circuit diagram showing a detailed configuration of a part of the OM data / external control data changeover switch and the latch circuit.

9 is a timing chart showing the operation of the semiconductor integrated circuit shown in FIG.

FIG. 10 is a circuit block diagram showing a configuration example of a conventional semiconductor integrated circuit.

11 is a circuit diagram showing a detailed configuration of a part of the PROM circuit shown in FIG.

[Explanation of symbols]

1 semiconductor integrated circuit 2 serial / parallel conversion circuit 3 block selection decoding circuit 4 PROM write control signal decoding circuit 5 PROM circuit 6 ROM data / external control data changeover switch and latch circuit 7 D / A converter circuit 8 adjusted circuit 9 CPU 10 Delay circuit 21 Write / read switching output circuit 22 ROM control / external control switching signal output circuit 23 Block selection output circuit 24 Bit selection output circuit 25 External control data output circuit

─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-9-330135 (JP, A) JP-A-1-57498 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 11/22-11/26 G06F 9/06

Claims (2)

(57) [Claims] 1. A semiconductor integrated circuit including a ROM for adjusting variations in standard characteristics inside an IC and a plurality of blocks for respectively adjusting a plurality of standard characteristics, wherein the semiconductor integrated circuit transmits a control signal. input circuit for inputting from outside, the control signal includes a ROM control and external control switching signal and the block selection signal and a block selection decode circuit for generating a decode signal by decoding, and based on the decode signal, the A ROM data / external control data changeover switch for selecting one block from a plurality of blocks, switching between ROM data from the ROM and external control data included in the control signal, and outputting to the selected block, and latch circuits, the <br/> Bei example, the block select decode circuit, said ROM Control / outside
Part control switching signal is in ROM mode, and the control
Outputs low level when the signal is in read mode,
ROM control / external control switching signal is in external control mode or
High level when the control signal is in write mode
And an OR circuit that outputs a block selection signal
The first logic circuit that becomes active at low level
The output of the OR circuit and the output of the first logic circuit group
And a NAND circuit group for inputting, respectively, the ROM data / external control data changeover switch and the latch.
Switch circuit, the ROM data and the external control data
Is switched by the ROM control / external control switching signal
The outputs of the second logic circuit group and the NAND circuit group are latched.
Output to the D input.
A semiconductor integrated circuit comprising: a latch circuit group for inputting each . 2. The ROM data / external control data switching
Switch and latch circuits input external control data
In order to select the block before, the delay circuit is set to the RO
M data / external control data changeover switch and latch circuit
The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is connected to .