JP3453614B2 - Method of forming fine pattern gap in semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly to a method of forming a fine pattern gap in a semiconductor device.

[0002]

2. Description of the Related Art Due to high integration of semiconductor devices, respective patterns forming the semiconductor devices are miniaturized, and a process margin is also reduced in consideration of misalignment. Generally, patterning of a semiconductor device is performed through a lithography process using a photoresist. However, the smallest size that is commercially available and can be stably processed is a chemically amplified deep ultraviolet (DUV) photoresist. , 0.25 μm obtained by a method of exposing using a KrF light source having a wavelength (λ) of 248 nm. This is KrF
It corresponds to the limit of the resolution of the light source, and it can be said that it is almost impossible to stably form a fine pattern of 0.25 μm or less using the KrF light source due to the wavelength limit.

1 and 2 attached herewith show an electron microscope (S) for examining a lithography process according to the prior art.
It is a photograph of EM). First, FIG. 1 shows a state in which a photoresist pattern for patterning the already formed polysilicon film is formed thereunder, and FIG. 2 shows a cross section of the polysilicon film patterned using the photoresist pattern as an etching barrier. 3 is a photograph of an electron microscope showing the above.

From the figure, the line width of the photoresist pattern and that of the polysilicon film which is the etching target layer are 22.
It can be seen that almost the same pattern is formed at 00Å (the formation of such a pattern having a line width of 2200Å is experimentally possible, but remains stable and reproducible in the actual process. , It's almost impossible to get this).

For a 0.25 μm DRAM process,
As one method for overcoming the refresh characteristic and the lack of a process margin when forming a contact hole, a self-aligned pad connected to a bonding layer is formed,
A method of connecting through a self-aligning pad during the subsequent contact hole formation is used.

3 to 5 attached herewith are views showing a conventional self-aligned contact forming process.

First, as shown in FIG. 3, a polysilicon film for a self-aligning pad is formed on the entire lower structure in which a gate 13 having a sidewall spacer 11 and a mask oxide film 12 is formed on a silicon substrate 10 through a series of transistor forming processes. 1
4 and an anti-reflective nitride film 15 are deposited, and a photoresist pattern 1 for forming a self-aligned pad is formed thereon.
It is a figure which shows the state in which 6 was formed.

At this time, the right side of the figure shows a state in which a gap of 0.25 μm or more is secured between the photoresist patterns 16, but the left side shows the photoresist pattern 16.
The gap between them is 0.25 μm or less, and the photoresist pattern 16 is not correctly formed due to the limit of resolution of the exposure source (A portion).

Next, FIG. 4 shows a photoresist pattern 1.
6, the nitride film 15 and the polysilicon film 14 are selectively etched to form a self-aligning pad, the photoresist pattern 16 is removed, and then an interlayer insulating film 17 is formed on the entire structure. There is.

FIG. 5 shows bit line 1 on the self-aligning pad.
8 and the charge storage electrode 19 are shown in contact with each other, illustrating that the photoresist pattern 16 is not correctly formed in the portion A of FIG. 3 to induce a bridge between the self-aligned pads (portion B). ing. Reference numeral 20 in the drawing denotes an interlayer insulating film.

In order to secure a sufficient gap between the photoresist patterns 16, the line width of the self-aligning pad is reduced (see the SEM photograph of FIG. 6) and the overlap margin is reduced, which causes the gate 13 and the self-aligning pad. There was a problem that the possibility that the bridge (part C) would be induced increases. In addition, there is a lithography technology that uses X-rays as an exposure source as a next-generation technology for overcoming the problems associated with the resolution limit of the lithography process, but there is no commercialized device for performing the process. There are still many technical limitations. Thus, until now, there has been no technique capable of stably forming a fine pattern of 0.25 μm or less using a photoresist.

Further, US Pat. No. 5,476,807 discloses that a polymer is formed on a photoresist pattern by using CF ₄ and CHF ₃ gas to use it as an etching mask. Since the polymer cannot have sufficient durability in the subsequent etching process, there is a problem that it cannot perform the role of an etching mask.

[0013]

SUMMARY OF THE INVENTION The present invention uses current exposure techniques to provide a durable polymer to resolve the resolution limits of current lithographic processes (eg,
It is an object of the present invention to provide a method of forming a fine pattern gap of a semiconductor device capable of forming a fine pattern gap of 0.25 μm or less.

[0014]

In order to achieve the above technical object, a method of forming a fine pattern gap of a semiconductor device according to the present invention comprises a step of forming a predetermined etching target layer on a semiconductor substrate, and the etching. Silicon nitride on target layer
And forming a photoresist pattern to expose a partial region of the etching barrier layer, applying a bias power to the semiconductor substrate, and exposing the exposed etching barrier layer. It said etching object and depositing a polymer - <br/> over a layer on a sidewall of the etch barrier layer and the photoresist pattern while etching, the photoresist pattern and <br/> before Kipo Rimmer as an etch barrier the layers were etched, the spacing of the etched interlayer
Narrower than the corresponding spacing of the photoresist pattern
Forming .

A gas (eg, H 2) that reacts with carbon components in the photoresist to easily generate a polymer.
C—F series gas such as Br, N ₂ , O ₂ , CF ₄ and C
In a variety of substances forming plasma, which are formed by using C-H-F series gas such as HF ₃ ) alone or in combination, charged ions and the like are formed on a base film such as a silicon layer, a silicon oxide film and a silicon nitride film. The incident ions cause scattering, and the ions and the like that are incident at this time are Si, O, and
Reacts with components and carbon components of the photoresist, such as N
So to generate a port Rimmer.

[0016] Such port Rimmer, increases the size of the photoresist pattern on the surface (mainly sidewall portion) photoresist pattern is deposited, it will decrease relatively spaces between the photoresist patterns Accordingly Like

[0017] Po Rimmer, photoresist pattern not only on the surface of, but also is deposited on the exposed surface of the etched layer, the polymer deposited on the surface of the thus etched layer, subsequent etching step Since it acts as an etching barrier and complicates the process, it is important to proceed with the process such that the photoresist is selectively deposited only on the sidewall portion of the photoresist pattern and the etching barrier layer when the polymer is deposited.

To selectively deposit the polymer, a bias power supply is applied to the electrode on which the wafer is placed during plasma formation for polymer deposition to enhance the rectilinearity of the incident ions, ie By increasing the energy, the exposed surface of the etching barrier layer is bombarded with high-energy ions so that the polymer is not deposited on the exposed portion of the etching barrier layer, and the deposition is concentrated only on the sidewall portion of the photoresist pattern. To

In practice, the polymer is not deposited on the surface of the layer to be etched, but is decomposed by the ions that are incident at the same time as the deposition. Therefore, in order to apply such a principle to an actual lithographic process, it is necessary to study the conditions of selective polymer deposition in consideration of the characteristics of an etching apparatus.

[0020]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

FIGS. 7 and 8 attached show HBr and N ₂
It is an electron microscope photograph after polymer vapor deposition using gas.

As shown in the figure, a polymer is deposited on the sidewall of the photoresist pattern (PR),
If the line width of the overall pattern is the minor axis (see Fig. 7), 2
From 000Å to 3450Å, in the case of the long axis (see Fig. 8),
It is clearly seen that it increases from 6500Å to 8100Å. Also, the line width of the pattern can be easily adjusted by adjusting the polymer deposition time.

FIGS. 9 and 10 attached hereto are electron micrographs of an etching barrier layer obtained by etching using a photoresist pattern having a polymer deposited on its side wall as an etching barrier. As shown in FIG.
It can be seen that both the line width of the pattern and the long axis (see FIG. 10) greatly increase the line width of the pure photoresist pattern and the line width of the pattern gap decreases accordingly.

Here, the line width of the pattern formed by etching seems to be smaller than the line width (PR + polymer) shown in FIGS. 7 and 8 because the polymer on the sidewall of the photoresist pattern appears. This is because they cannot all act as etching barriers. Further, the lower part of the pattern is formed larger than the upper part is due to the influence of the polymer generally generated during dry etching.

Comparing the photoresist pattern and the etched pattern shown in FIGS. 7 and 9 with FIGS. 1 and 2, a line width gain of approximately 1000 Å or more can be obtained when the present invention is carried out. In the end, it means that the line width of the pattern gap can be reduced by 1000 Å or more.

11 to 14 attached herewith show a process of forming a self-aligned contact according to an embodiment of the present invention, and the process will be described below with reference to this.

First, as shown in FIG. 11, a gate 33 having a sidewall spacer 31 and a mask oxide film 32 is formed on a silicon substrate 30 through a series of transistor forming processes.
A polysilicon film 34 for a self-aligning pad and a silicon nitride film 35 which is an antireflection film (or an etching barrier layer) are sequentially deposited on the entire lower structure in which the layers are formed.

Next, a photoresist pattern 36 for forming a self-aligned pad is formed on the silicon nitride film 35. At this time, the gap between the photoresist patterns 36 is formed to be about 0.30 μm. The photoresist pattern 36 may be formed using a dissolution suppressing i-line photoresist or a chemically amplified deep ultraviolet (DUV) photoresist in consideration of the type of the lower layer and a polymer deposition target. FIG. 15 is an electron micrograph showing the structure in which the photoresist pattern 36 is formed in this manner.
Shown in.

Next, as shown in FIG. 12, depositing a port Rimmer 37 on the side wall of the photoresist pattern 36. Po deposition of Li <br/> mer 37, reactive ion etching (RIE)
Type etching apparatus, plasma is formed using HBr gas, and the chamber pressure is set to 1 to 100 mT.
orr , the temperature of the electrode and the chamber wall is -30 to + 80 ° C.
And a bias power of 500 to 2000 W is applied to the electrode on the wafer side to expose the surface of the lower layer.
Po Rimmer 37 without being deposited, to be only selectively deposited on the sidewalls of the photoresist pattern 36.

[0030] At this time, the silicon nitride film 35 is consumed in the deposition process of Po Rimmer 37, the polysilicon film 34 is exposed. Then, the line width control of the polysilicon pad 34 is possible by adjusting the deposition thickness of the port Rimmer 37. An electron micrograph at this time is shown in FIG.

Next, as shown in FIG. 13, Po Rimmer 37 deposited on the photoresist pattern 36 and the sidewall thereof
Is used as an etching barrier to dry-etch the polysilicon film 34, which is the etching target layer, to form the polysilicon pad 34, and then the photoresist pattern 36 is removed. At this time, dry etching can be performed in an apparatus that was used during the deposition of the port <br/> Rimmer 37 in situ (in-situ). An electron micrograph at this time is shown in FIG. From the figure, it can be seen that the bridge between the polysilicon pads 34 does not occur.

Next, FIG. 14 shows a polysilicon pad 34.
The state where the bit line 38 and the charge storage electrode 39 are in contact with each other is shown in FIG.
4 can be increased to ensure a sufficient overlap margin, and the gate 33 and the polysilicon pad 3 can be secured.
No bridge between four also occurred. Note that reference numeral 4
Reference numerals 0 and 41 respectively denote interlayer insulating films.

FIG. 18 attached herewith is an electron micrograph showing a cross-sectional structure of a self-aligning pad formed according to another embodiment of the present invention. forming a nitride film is the antireflection film as an etching barrier layer, its after forming a photoresist pattern on top and proceeded etching after depositing port Rimmer photoresist pattern sidewalls by applying the present invention The latter state is shown.

[0034] In this embodiment, the etching of the deposition and polysilicon film Po Rimmer, ICP (inductively
TCP-9 manufactured by Lam Research, which is a coupled plasma type polysilicon etching device.
Using 408, selective polymer deposition is performed under the following conditions.

HBr and N ₂ gas were added at 1:10 to 10: 1.
To form plasma, the chamber pressure is set to 1 to 50 mTorr , the electrode temperature is set to −30 to + 80 ° C., the source power is 100 to 600 W, and the bias power is 300 W or less. set, as Po Rimmer the exposed surface of the lower layer is hardly deposited, to be selectively deposited to focus only on the sidewalls of the photoresist pattern. It can be seen from the drawing that the line width of the polysilicon pad is increased by 1000 Å or more as compared with FIG.

In the present invention, as shown in FIG. 19 attached, since the polymer deposition time (ie, plasma exposure time) and the line width increase are directly proportional to each other in a specific range, the polymer exposure time can be adjusted by adjusting the polymer exposure time. The line width of the layer pattern can be easily controlled, and the line width of the pattern can be controlled by adjusting the deposition thickness of the polymer.

Here, it can be seen that the line width drastically increases when the polymer deposition time is 100 seconds. This is because the nitride film (etching prevention film) in the lower layer of the photoresist pattern is completely etched during the polymer deposition process to expose the polysilicon film existing thereunder, thereby increasing the polymer deposition rate. Therefore, the desired pattern line width can be easily controlled by adjusting the type and thickness of the lower layer.

The present invention described above is not limited by the above-described embodiments and the accompanying drawings, and various substitutions, modifications and changes can be made without departing from the technical idea of the present invention. This is apparent to those of ordinary skill in the art to which the present invention pertains.

For example, in the above-described embodiments, the case where the silicon nitride film is used as the antireflection film for forming the pattern has been described as an example, but the silicon nitride film is not essential. Further, the formation of the fine pattern gap of the present invention described above is not particularly limited to the form of the pattern of the contact hole, the charge storage electrode, the electrode pad and the like.

[0040]

The present invention described above uses the equipment and techniques currently in use to limit the lithographic process (eg,
A line width of 0.25 μm or less can be achieved relatively easily, and the line width can be easily controlled. Also, the present invention has an effect of preventing the misalignment by securing an overlap margin by reducing an unnecessary space between patterns by an application method.

[Brief description of drawings]

FIG. 1 is a first electron micrograph for considering a lithography process according to a conventional technique.

FIG. 2 is a second electron micrograph for considering a lithography process according to the related art.

FIG. 3 is a first cross-sectional view of an element for explaining a self-aligned contact forming process according to a conventional technique.

FIG. 4 is a second cross-sectional view of a device for explaining a self-aligned contact forming process according to a conventional technique.

FIG. 5 is a third cross-sectional view of the device for explaining the self-aligned contact forming process according to the conventional technique.

FIG. 6 is an electron micrograph after etching a self-aligned pad according to the prior art.

FIG. 7 is a first electron microscopic photograph after polymer deposition according to the present invention.

FIG. 8 is a second electron micrograph after vapor deposition of a polymer according to the present invention.

FIG. 9 is a first electron micrograph after pattern etching according to the present invention.

FIG. 10 is a second electron micrograph after pattern etching according to the present invention.

FIG. 11 is a first cross-sectional view of a device for explaining a self-aligned contact forming process according to an embodiment of the present invention.

FIG. 12 is a second cross-sectional view of the device for explaining the self-aligned contact forming process according to the embodiment of the present invention.

FIG. 13 is a third cross-sectional view of the device for explaining the self-aligned contact forming step according to the embodiment of the present invention.

FIG. 14 is a fourth cross-sectional view of the device for explaining the self-aligned contact forming step according to the embodiment of the present invention.

15 is an electron micrograph corresponding to the process described with reference to FIG.

16 is an electron micrograph corresponding to the process described with reference to FIG.

FIG. 17 is an electron micrograph corresponding to the process described with reference to FIG.

FIG. 18 is an electron micrograph after etching a polysilicon pad according to another embodiment of the present invention.

FIG. 19 is a graph showing the relationship between the polymer deposition time and the increase in the pattern line width.

[Explanation of symbols]

30 a silicon substrate 31 sidewall spacers 31 mask oxide film 33 gate 34 polysilicon film (polysilicon pads) 35 silicon nitride film 36 a photoresist pattern 3 7 Po Rimmer 38 bit lines 39 charge storage electrode 40, 41 interlayer insulating film

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor ▲ Bei ▼ Kei Ken, 136-1, Fengsatoyama, Haba-eup, Icheon-gun, Gyeonggi-do, Republic of Korea (72) Inventor Kim Shun, East Icheon-gun, Gyeonggi-do, Republic of Korea 136-1 Hibasato Famisatoyama Hyundai Electronics Industry Co., Ltd. (56) Reference JP-A-7-130680 (JP, A) JP-A-9-129595 (JP, A) JP-A-9-270416 (JP , A) JP-A-8-339986 (JP, A) JP-A-9-237777 (JP, A) JP-A-3-196623 (JP, A) '96 Latest semiconductor process technology, Japan, Press Journal, Inc. September 8, 1995, P97-101, P123 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/3065 G03F 7/26 G03F 7/40 521 H01L 21/3213

Claims (12)

(57) [Claims] 1. A step of forming a predetermined etching target layer on a semiconductor substrate, and an antireflection coating made of silicon nitride on the etching target layer.
Forming an etching barrier layer that also functions as a stop film , forming a photoresist pattern so as to expose a partial region of the etching barrier layer, applying a bias power supply to the semiconductor substrate, and exposing the semiconductor substrate. Depositing a polymer on the sidewalls of the etching barrier layer and the photoresist pattern while etching the etched etching barrier layer, and etching the etching target layer using the photoresist pattern and the polymer as an etching barrier,
Forming a gap between the layers to be etched narrower than a corresponding gap of the photoresist pattern. 2. The step of depositing the polymer comprises adding HBr.
Gas, N ₂ gas, O ₂ gas, C-F series gas, C-H-F
The method of claim 1, wherein at least one of the series gases is used to form plasma. 3. The method for forming a fine pattern gap in a semiconductor device according to claim 1, wherein the etching barrier layer is an antireflection film. 4. The fine pattern gap of a semiconductor device according to claim 1, wherein the photoresist pattern is formed using a dissolution suppressing i-line photoresist or a chemically amplified deep ultraviolet photoresist. Forming method. 5. The method of claim 1, wherein the polymer is deposited in an inductively coupled plasma etching apparatus. 6. The method of claim 1, wherein depositing the polymer is performed in a reactive ion etching apparatus. 7. The method for forming a fine pattern gap in a semiconductor device according to claim 5, wherein the step of depositing the polymer and the step of etching the layer to be etched are performed in the same apparatus. . 8. The method of depositing the polymer, wherein HBr is used.
The method of claim 5, wherein the plasma is formed by using a gas in which the gas and the N ₂ gas are mixed in a ratio of 1:10 to 10: 1. 9. The step of depositing the polymer comprises 100.
7. The method of claim 5, wherein the source power of W to 600 W and the bias power of not exceeding 300 W are used. 10. The step of depositing the polymer is 1 m.
Pressure of Torr to 50 mTorr and -30 ° C to +
The method for forming a fine pattern gap in a semiconductor device according to claim 5, wherein the method is performed under a condition of an electrode temperature of 80 ° C. 11. The step of depositing the polymer comprises 50.
7. The method of claim 6, wherein the method is performed using a bias power source of 0 W to 2000 W and a pressure condition of 1 mTorr to 100 mTorr. 12. The temperature of an electrode and an inner wall of the reactive ion etching apparatus is controlled by the step of depositing the polymer.
The method for forming a fine pattern gap in a semiconductor device according to claim 6, wherein the temperature is 30 ° C to + 80 ° C.