JP3449907B2 - Data input / output device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a functional means such as a real-time clock (hereinafter abbreviated as "RTC") whose data input / output speed is relatively low. And a data input / output device that can be accessed from high-speed functional means such as a CPU. 2. Description of the Related Art Normally, when real-time processing is performed by various digital circuits such as a computer, for example, by using a dedicated function chip called an RTC while backing up the battery with a battery, it is possible to perform processing such as date and time. It is common practice to configure such that it can hold various time data in real time. [0003] By the way, data input / output to / from this chip has conventionally been configured so that 4- or 8-bit data can be read / written at once, but in recent years, the functional chip itself and an interface on the interface side with the chip have recently been used. In order to reduce the package size of the chip, and thus the overall size of the electronic device incorporating the chip, by reducing the number of pins in the device, the type of data input / output that is serialized one bit at a time has also increased. I have. [0004] However, in the chip having the serial interface as described above, the data transfer speed is further reduced in order to suppress the power consumption of the battery at the time of data backup. At most 1
As a result of being suppressed to a low speed of about 00 kHz, especially when an application that repeatedly reads and writes data is used, the delay in data transfer to this chip affects the data processing speed of the entire system. For example, in many cases, the year is represented by 8 bits, the month is represented by 5 bits, the hour is represented by 6 bits, and the minute and the second are represented by 7 bits, respectively. When the transfer is performed at the clock frequency of 10 bits, it takes 10 μs to transfer one bit, so that at least 320 μs for 32 bits. In recent CPUs, it takes less than 1 μs to read and write data of the bus width.
If it becomes necessary to repeat the access, this access causes a reduction in the data processing speed of the entire system. The present invention solves such a problem at once. Instead of directly reading / writing data from / to a low-speed side functional unit under control of a high-speed side functional unit, the present invention relates to a low-speed side functional unit. The object of the present invention is to provide a data input / output device capable of accessing data from a high-speed functional means such as a CPU at a high speed without requiring a waiting time by providing a function of automatically reading and writing data between the data input and output means. I do. A data input / output device 10 according to the present invention has an RTC having a serial interface as schematically shown in FIG.
The data input / output operation as described above is between the low-speed function means 12 and the high-speed function means 16 such as a CPU having a parallel interface, so that data can be exchanged with each other. Further, a low-speed interface enabling data transfer to and from the low-speed function means 12 and a high-speed interface enabling data transfer to and from the high-speed function means 16 described above. And a control unit 34 for periodically reading data from the low-speed function unit 12 to the data storage unit 32. The high-speed function unit 16 The low-speed function means 12 can be accessed at any time via the high-speed interface of the data storage means 32. As shown in FIG. 2, the data storage means 32 includes a shift register 36 for directly transferring data to and from the low-speed function means 12 in a serial manner. Buffer memory 38.4 for writing and reading for transferring data in parallel
0. On the other hand, the control means 34 continuously sends data into the shift register 36 at the data transfer speed of the low-speed function means 12 corresponding to the data reading time, and a series of data is stored in the shift register 36. When the data is read, the data is read out from the buffer memory 4 for reading.
Write to 0. In accordance with the timing of writing data from the high-speed function means 16 to the write buffer memory 38, the reading of data from the low-speed function means 12 to the shift register 36 is temporarily stopped, and the write buffer memory 38 After the data is transferred to the shift register 36, the data in the shift register 36 is serially transferred at the data transfer speed of the low-speed function means 12, and when the series of data has been transferred, the mode returns to the data read mode. As described above, the present invention is provided between the low-speed function means 12 such as the RTC 14 and the high-speed function means 16 such as the CPU 18 to read and write data from and to the low-speed function means 12. Equipped with buffer means to perform automatically,
By indirectly accessing the low-speed function means 12 from the high-speed function means 16 via the buffer means, the high-speed function means 16 can be accessed from the low-speed function means 12.
Can be accessed at high speed without delay in data input / output, and a high data processing speed can be maintained as a whole system. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIGS. 1 and 2, a data input / output device 10 according to the present invention includes an RTC 14 provided as a low-speed function unit 12 and a high-speed function unit 16. Between the equipped CPU 18 and the CP
It transfers data between U18 and RTC14. The RTC 14 can form in real time date data such as year, month and day, time data such as hour, minute and second, or time data such as 1/10 second and 1/100 second as required. A single-chip functional means having a circuit configuration substantially the same as that of the related art. Even when an electronic device in which the electronic device is incorporated stops its operation, the operation is backed up by the battery 20 so that the inside of the chip is The latest real-time data can always be maintained on the data holding unit 22 of the. The data holding unit 22 is a shift register having a data input terminal 24 and a data input terminal 26.
For example, in synchronization with a transfer clock signal 48 composed of a pulse signal of about 100 kHz, data is serially input and output bit by bit. That is, the read signal 4 for the chip
At the time of application of 4, data held in the data holding unit 22 in the chip is taken out serially one bit at a time via the output terminal 26. Conversely, when the write signal 46 is applied, a series of data is read from the outside via the input terminal 24 into the data holding unit 22 in a serial manner bit by bit, and the data on the data holding unit 22 is rewritten. The data change operation is automatically performed inside the chip based on the rewritten data. On the other hand, the C provided as the high-speed function means 16
The PU 18 is provided with various buses 30 such as a data bus 28 and an address bus in the same manner as in the prior art, and sends data via the data bus 28 to the data storage means 32 at the address specified by the address designation from the CPU 18. Can be delivered in parallel. The data input / output device 10 according to the present invention comprises:
A data storage means 32 and a control means 34;
4, the data is exchanged between the RTC 14 and the data storage means 32, while the data storage means 32 and the CPU 1 are linked with the access operation from the CPU 18.
Data can be exchanged between the eight. The data storage means 32 stores the RTC 1
4 and a shift register 36 for transferring data in a serial manner to and from the CPU 18 and write and read buffer memories 38 and 40 for transferring data to and from the CPU 18 in a parallel manner. The shift register 36 and the data holding unit 22 in the RTC 14 have the same number of bits, and
The input / output terminals 24 and 26 are connected to the shift register 36 in a loop, and the above-mentioned transfer clock signal 48 is formed by the oscillator 42 provided in the control means 34 so that the shift register 36 and the RTC 14 chip are , They operate in synchronization with the transfer clock signal 48, and can mutually transmit necessary data in a serial manner. The shift register 36 and the buffer memories 38 and 40 for writing and reading have the same number of bits, and each bit is connected in parallel with each other. Further, by the operation of the control means 34, the shift register 3
In conjunction with the reading of one set of data from the RTC 14 into the memory 6, the data can be transferred collectively in parallel from the shift register 36 to the reading buffer memory 40, and the data can be transferred to the writing buffer memory 38. In conjunction with the writing of data, contrary to the above case, the data can be collectively transferred from the write buffer memory 38 to the shift register 36 side. Next, the operation of the data input / output device 10 will be described in more detail with reference to the flowchart shown in FIG. When the apparatus is started in step S1, predetermined initial settings are made in step S2. This initialization involves, for example, clearing the shift register 36 and the buffer memories 38 and 40 for writing and reading, outputting the data read signal 44 to the RTC chip, and then entering the main routine starting from step S3. . In this apparatus, data is always read from the RTC 14 to the shift register 36 periodically, but when the CPU 18 issues a data write request, the data read operation is temporarily stopped. After performing a data write operation for one set on the RTC 14 from the shift register 36 side, the process returns to the data read operation described above. In step S3, it is determined whether or not there is data input from the CPU 18 to the buffer memory 38 for writing. If " NO ", the data reading operation starts from step S4. In step S4, it is determined whether or not one set of data has been input from the RTC 14 side.
If "O", the next 1-bit data is sent from the RTC 14 into the shift register 36 in step S5.
It returns to step S3. On the other hand, if the determination in step S4 is “Y
If "ES", the process proceeds to step S6 to read the data in the shift register 36 into the read buffer memory 40, thereby completing a series of data read operations. This data read operation is repeated in synchronization with the transfer clock signal 48, so that the read buffer memory 40 has a minimum time delay in the read buffer memory RT.
The data having the same content as that generated in C14 is RT
Read buffer memory 4 isolated from C14 side
It is kept within 0. Therefore, by simply accessing the read buffer memory 40 at an arbitrary timing from the CPU 18, all data is read at once with the bus width of the data bus 28. On the other hand, when writing data from the CPU 18 into the RTC 14, necessary data is written into the write buffer memory 38 via the data bus 28 at an arbitrary timing. Then, the determination in step S3 is "YES".
In step S7, the data write signal 46 to the RTC 14 is turned on, the data transfer direction between the RTC 14 and the shift register 36 is set to the data write side, and the write buffer memory 38 The data is transferred to the shift register 36. Further, in step S10, while data is sent from the shift register 36 side to the RTC 14 one bit at a time, the shift register 36
When it is confirmed that all of the series of data has been sent to the RTC 14 side, the write signal 46 is inverted in step S11 and returned to the read signal 44, and then the process returns to step S3, where the data from the RTC 14 side is returned. The read operation is repeated. The above-mentioned functional means is an example,
For example, instead of the RTC 14 provided as the low-speed side function unit 12, the function unit 1 whose data input / output standard is the high-speed side like a scanner having a serial data input / output circuit is used.
6 can be implemented in substantially the same manner when the speed is sufficiently lower than that in FIG. Further, the configurations of the data storage means 32 and the control means 34 can be changed as appropriate as long as the low-speed data and the high-speed data can be transferred while being buffered. Also, the frequency of reading data from the low-speed function means 12 to the data storage means 32 is 70% or more, so that data can be read in a nearly continuous state, and a data read request is issued from the high-speed function means 16 side. The data can be read out in conjunction with.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram schematically showing an overall configuration. FIG. 2 is a block diagram specifically showing a configuration of a data input / output device according to the present invention. FIG. 3 is a flowchart illustrating an example of an operation procedure of the data input / output device. DESCRIPTION OF SYMBOLS 10 Data input / output device 12 Low-speed function means 14 RTC 16 High-speed function means 18 CPU 20 Battery 22 Data holding unit 24 Data holding unit input terminal 26 Data holding unit output terminal 28 Data bus 30 Other Bus 32 data storage means 34 control means 36 shift register 38 write buffer memory 40 read buffer memory 42 oscillator 44 read signal 46 write signal 48 transfer clock signal

Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 13/38 320 G06F 5/06 JICST file (JOIS) WPI (DIALOG)

Claims (1)

(57) [Claims] (1)A library with a serial interface
Real-time clock (14) and parallel interface
CPU with face (18)Between each other
A data input / output device for transferring data,The real-time clock (14) BetweendirectlyDe
Low-speed interface that enables data transfer
When,The CPU (18)Data can be passed between and
Data storage with high speed interface
Means (32); The data storage means (32)And the real-time clock
Between (14)dataofreadingWritingcontrolDohand
Step (34)WhenWithThe data storage means (32) Data is exchanged with the real-time clock (14).
A shift register (36) for delivering in real form;
Data in parallel with the register (36)
Write and read buffer memory to be passed (38)
・ (40) is composed of The control means (34) Data transfer in the real-time clock (14)
The data is continuously transferred at the speed by the real-time clock (1).
4) into the shift register (36),
When the data is stored in the shift register (36),
In the read buffer memory (40).
The operation of writing and updating data is repeated periodically.
Meanwhile, The buffer memo for writing from the CPU (18).
According to the timing of writing data to the memory (38),
From the real-time clock (14) to the shift register
Suspends the data read operation for the star (36)
And the write buffer memory (38)
After transferring the data from to the shift register (36),
Data transfer speed in real time clock (14)
Serialize the data in the shift register (36)
Data transfer to the real-time clock (14)
When a series of data has been transferred, the real-time
A clock (14) is supplied to the shift register (36).
The read operation of the data to be restarted Characterized by
Data input / output device.