JP3448744B2 - Signal delay device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal delay device, and more particularly to a signal delay device for obtaining a highly accurate delay.

[0002]

2. Description of the Related Art Conventionally, when a certain signal has an arbitrary delay time, a commercially available delay line is generally used. As the internal structure of such a delay line, there are a distributed constant type structure such as a coaxial cable and a delay cable, and a lumped constant type structure composed of discrete L and C, so that an accurate delay signal can be obtained. .

[0003]

However, this type of delay line has the drawback of being very expensive. On the other hand, as a method of obtaining a delay signal at a low cost, it is possible to obtain a desired delay time by stacking a plurality of delay elements of an integrated circuit, but due to variations in the manufacturing process and fluctuations in temperature, humidity, and power supply voltage. Since the delay time is greatly affected, it is not possible to obtain the delay signal with the required accuracy.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a signal delay circuit capable of managing the delay time with high accuracy while using inexpensive circuit elements. To do.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal delay device for outputting a delay signal of a desired delay time from an input signal having one or more rectangular waves of a predetermined time length, the unit delay number The circuit element unit consisting of a plurality of, comprising a cascade connected circuit element group, the input signal is input to the circuit element group, according to the number of units passing through the circuit element unit, to the input signal Signal delay means for generating a plurality of delay signals having different delay times, and a delay signal having a phase synchronization relationship with the input signal from the plurality of delay signals generated by the signal delay means is used as a reference. The signal detecting means for detecting as a signal and the signal detecting means are
A mask processing unit for detecting one reference signal;
Based on the time when the reference signal is detected by the signal detection means
Based on the delay time per unit of the circuit element,
And an output signal determining unit configured to output a delay signal generated in a circuit element unit for generating a delay signal having a desired delay time .

[0006]

In the present invention described above, the relationship between the input signal and the phase synchronization is detected by the signal detecting means for detecting the reference signal from the plurality of delay signals generated and output by the signal delay means including a plurality of circuit element units. The delay signal of the desired delay time is detected when the delay signal generated in the circuit element unit is used as the reference signal in advance for the circuit element unit generating the reference signal. A desired delay signal is output from the output signal determining means that finds and correlates the circuit element unit that is generating the signal.

Therefore, even if the delay time greatly changes due to the fluctuations of temperature, humidity and power supply voltage, a highly accurate delay signal can be obtained in response to the fluctuations while using inexpensive circuit elements. .

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a configuration diagram showing the overall configuration of a first embodiment of the present invention. In FIG. 1, 1
Is for delaying the input signal to obtain multiple delayed signals,
It is a delay element group which constitutes the signal delay means of the present invention. Reference numeral 2 is a reference signal detecting section which constitutes the signal detecting means of the present invention, and 3 is an output signal determining group which constitutes the output signal determining means of the present invention. The reference signal detecting section 2 and the output signal determining group 3 are This constitutes signal selecting means for selecting a delayed signal having a predetermined delay time. Further, as described later, the output signal determination group 3 includes a plurality of output signal determination units 3a to 3a.
It is composed of 3n.

Here, as the input signal input to the signal delay device of the present invention, in order to obtain a highly accurate delayed signal, it is preferable to use a clock signal having a rectangular wave with a duty of 50%. In the following embodiments, description is given on the assumption that a clock signal is used as an input signal.

FIG. 2 is a configuration diagram showing an example of the internal configuration of the delay element group 1. In the example shown in FIG. 2, a delay element group is formed by stacking a plurality of stages using internal cells (inverters) of an integrated circuit. In the delay element group 1, two inverters are connected to each stage so that the duty of the clock signal does not collapse to the final stage. In addition, the number of branches and the number of fan-outs of each inverter are made uniform to minimize the variation in each stage. Therefore, in FIG. 2, DL0 to DLn are delay signals actually obtained by the delay element group 1, and dummy signals DL0D to DLnD for making the number of branches and the number of fan-outs are equal to the delay signal path and impedance. And the like are input to a dummy inverter or the like to make them equal. Also, there is no particular limitation on the number of stages of this delay element group, but the delay time in each delay element may change from 1/3 times to 3 times the typ value due to environmental changes such as temperature changes. Therefore, it is safe to set the number of stages so that the reference signal can be detected in consideration of the change in the delay time of each delay element and the desired delay time can be obtained. The signal delay means of the present invention is not limited to this, and may be any structure as long as it generates a plurality of delay signals having different delay times with respect to the clock signal, and for example, a counter or the like can be used. Is.

FIG. 3 is a block diagram showing an example of the internal configuration of the reference signal detecting section 2. The reference signal detection unit 2 receives the plurality of delayed signals obtained by the delay element group 1 and the input signal and detects the delayed signal having a specific relationship with the input signal. Here, the specific relationship detected by the reference signal detection unit 2 mainly means a relationship in which the delay signal has a specific amount of phase difference with respect to the input signal, but the present invention is not limited to this. Focusing on factors in the input signal and the delay signal that are substantially unaffected by external factors such as temperature that affect the delay time, and if there is any detectable relation there, the present invention is Applicable. In the present embodiment, focusing on wavelengths that are not substantially affected by temperature, the relationship between the wavelengths of the input signal and the delayed signal,
That is, the detection is performed based on the phase difference.

Further, in particular, when the input signal is a clock signal, it is preferable to detect the relationship of in-phase (phase difference is an integral multiple of one cycle) or opposite phase (phase difference is an odd multiple of half cycle). . Therefore, in this specification, the relationship of having the same phase or the opposite phase with respect to the clock signal is referred to as a phase synchronization relationship, and in the present embodiment,
It is configured to detect a delayed signal having an antiphase relationship.

In the example shown in FIG. 3, the clock signal CLK is input to one end of a plurality of flip-flops forming the flip-flop group 2a, and the delay signal DL from the delay element group 1 is connected to the other ends thereof. Has been done.
Then, AND circuits that receive the positive terminal of a certain flip-flop and the negative terminal of an adjacent flip-flop are connected to each other. Therefore, of the output signals from the flip-flops, only the output (select signal SL) from the AND circuit corresponding to the flip-flop that first becomes "H" becomes "H", and this select signal is phased with the clock signal. The detection result indicates the synchronized delayed signal. It should be noted that the circuit is not limited to the circuit configuration of FIG. 3 as long as it is a circuit capable of outputting such a select signal SL, and the flip-flop is replaced with another circuit or the logic of the logical product is inverted. However, a similar reference signal detection unit can be realized.

FIG. 4 is a time chart showing the basic timing of the phase synchronization detection in the reference signal detecting section 2. As an example, it is output from the nth stage to the (n + 3) th stage of the delay element group 1. The detection of the phase synchronization between the delay signals DLn to DLn + 3 and the clock signal (FIG. 4A) is shown.
In FIG. 4, it is understood that the delay signal DLn + 2 is in phase synchronization with the clock signal.

Further, depending on the number of stages of the delay element group 1, there is a possibility that a plurality of phase-synchronized signals are detected as shown in the time chart of FIG. That is, in FIG. 5, phase synchronization is performed at three points DLn + 2, DLn + m + 3, and DLn + m. However, it suffices to detect the phase synchronization at one place, and in this embodiment, the delay signal DLn + m having the same phase with respect to the clock signal is not detected.
A flip-flop and an AND circuit are combined. In addition, the delay signals DLn + 2 and DLn having the opposite phase relationship
It is preferable that + m + 3 is masked by a configuration described later so that only one of them is detected in order to prevent malfunction.

FIG. 6 is a block diagram showing an example of the internal configuration of the output signal determining section 3a shown in FIG. The output signal determination unit 3a is a unit that outputs a delay signal (which is pre-allocated by an allocation formula described later) corresponding to the detection result from the reference signal detection unit 2, and is composed of a plurality of AND circuits. Has been done. Therefore, the detection result “H” of the reference signal detection unit 2 is input and the delay signal DL from the delay element group 1 connected to the AND circuit is output as a delay signal having a desired delay time.

When only one delay signal having a desired delay time is output, the output signal determining means can be composed of only the output signal determining section 3a, but a plurality of outputs are required. In such a case, a plurality of output signal determining units 3b to 3n, which have different allocations, are connected in parallel to the delay element group 1 and the reference signal detecting unit 2. As a result, it becomes possible for one signal delay device to output delay signals having different delay times from the respective output signal determining sections. For example, the delay times are 10 ns, 20 ns, 30 n.
It is also possible to output three delayed signals of s at the same time.

Further, in this embodiment, the overall accuracy is determined by the delay element group 1 and the reference signal detecting section 2, and particularly in the delay element group, the accuracy is determined by the inverter and its wiring delay. Therefore, although not described in detail in this specification, in order to improve the accuracy of the delay time, it is preferable to design the circuit while paying attention to the following points. -Select the minimum inverter delay and its wiring delay.・ To reduce delay variation, use a fanout with a large fanout or one with a small wiring delay.
Design so that the fanout and the number of branches of each inverter are uniform.・ Combining the positive theory and the negative theory so that the duty does not collapse.・ Minimize unnecessary gates. -When laying out, delay elements are arranged in blocks. -The delay time per stage is designed with reference to the typ value after layout.

Since the present invention having the above-described configuration can be configured by only a digital circuit, for example, the delay element group, the reference signal detecting section, and the output signal determining section are provided in one integrated circuit. be able to. Alternatively, only the delay element group and the reference signal detection unit may be provided in one integrated circuit to form a signal delay device circuit.

The operation of the circuit of this embodiment having the above-mentioned structure is as follows. The clock signal CLK given from the outside is delayed by a plurality of stages of delay elements of the delay element group 1, and a plurality of delay signals DL having different delay times are generated. The plurality of delayed signals DL are
It is supplied to one terminal of each flip-flop of the flip-flop group 2a of the reference signal detection unit 2.

A clock signal CLK is supplied to the other terminal of each of the flip-flops, and each flip-flop detects the rising (or the falling) of the clock signal CLK and the delay signal DL. Thus, the delay signal DL in phase with the clock signal CLK is detected. Then, the logical product circuit group 2b
Then, only the select signal SL from the AND circuit corresponding to the detected delay signal becomes "H" level.

The select signal SL thus output from the reference signal detector 2 is input to one AND circuit with the delay signal DL from the delay element group 1 based on the following allocation formula, for example.

A = (B / C) × D−E / F (1) where A: path length from the point where the clock signal is input (or circuit element that passes from the point where the clock signal is input) ) B: Desired delay time C: One cycle of the clock signal when the reference signal detector detects a delay signal in phase with the clock signal, or
When the reference signal detecting unit detects a delay signal having a phase opposite to that of the clock signal, the delay signal detected by the reference signal detecting unit is output from the point where the clock signal is input in the half cycle D: the clock signal. Path length to the point in the delay element group (or the clock signal from the point where the clock signal is input to the point in the delay element group where the delay signal detected by the reference signal detection unit is output The number of circuit elements to be used) E: From the point at which the clock signal is input to the point at which the delay signal having the desired delay time B is output, excluding the delay time required for passage through the delay element group The total delay time F required to pass through the path of: is the standard delay required for the clock signal to pass through the signal path (or unit of delay elements) per unit length. Time extension Further, the above formula (1) is equivalent to the following formula (2) when limited to this embodiment.

G = (H / I) × J−K / L (2) where G: the number of stages in the delay element group from which the delayed signal is to be taken out H: desired delay time (ns) I: clock signal Half cycle (ns) J: The number of stages of the select signal K: A delay signal having a desired delay time H from the point where the clock signal is input, excluding the delay time required for the clock signal to pass through the delay element group The total delay time (ns) required to pass through the path up to the point where L is output: L: the standard delay time (ns) required for the clock signal to pass through the unit number of delay elements (that is, two inverters) The delay signal to be output can be obtained based on the detection result of the reference signal detecting section 2 by the above equation (1) or equation (2).

For example, now I: 100 ns, J: 100
In the second stage, K: 5 ns, L: 1 ns, and when a delayed signal having a delay time of H: 10 ns is desired, (2)
From the formula, G = 5 is obtained. That is, the select signal of the 100th stage (that is, 100 in the delay signal output determining unit 3a).
The logical product circuit of the stage is ANDed with the delay signal output from the delay element of the fifth stage of the delay element group 1. When the solution of the equation (2) is not an integer, it is needless to say that the first decimal place is rounded or truncated to handle it as an integer.

Since there are various possible ways of allocating the select signal and the delay signal, they may be selected according to the required accuracy of the delay time. As a result of the allocation as described above, a desired delayed signal is output from the output signal determination unit 3a. That is, even if the delay time of the delay signal from the delay element group 1 changes due to a change in the power supply voltage or temperature, the reference signal detection unit 2 always detects the phase synchronization. One clock after the timing, based on the new select signal,
The output signal determination unit 3a outputs a new delayed signal, and the delayed signal is corrected almost in real time.

The delay signal thus obtained is output to, for example, a PWM circuit, which will be described later, but the delay signal of the output signal determination group 3 is set so as not to output the delay signal when the PWM circuit does not need the delay signal. Even if it is configured to be able to control whether or not to output next (or inside), it is effective.

If the number of stages of the delay element group 1 is not sufficient, there is a possibility that the reference signal detector 2 may not detect a delay signal phase-synchronized with the clock signal. In this case, since the delay signal output from the final stage of the delay element group 1 should have the delay time closest to the desired delay time, the select signal SL is input to the output signal determination group 3. If not, the delay signal output from the final stage of the delay element group 1 may be configured to be output.

Further, as the output signal determining means, instead of the output signal determining group 3 described above, a CPU outside the signal delay device is used.
It is also possible to use such as. That is, by connecting the delay element group 1 and the reference signal detection unit 2 to an external CPU and controlling them by software, the allocation of the above formula (1) or (2) is sequentially calculated, and the desired delay time is obtained. It is also possible to output a delay signal.

Next, the delay signal DLn + 2 shown in FIG.
Like DLn + m + 3, since the delay element group 1 has a large number of stages, the output from the delay element group 1 includes a plurality of delayed signals delayed by one clock or more, and as a result, the reference signal detection means performs phase synchronization. A configuration for preventing malfunction when a plurality of signals to be detected is detected will be described.

In the reference signal detecting means in this case, the reference signal detecting blocks 2A to 2D shown in FIG. 7 are preferably constructed as shown in FIG. The configuration of this reference signal detection block will be described below.

First, in the reference signal detection block 2A, the clock signal CLK is applied to one end of a predetermined number of flip-flops.
Is input, and the delay signals DL from the delay element group 1 are connected to the other ends thereof. Then, a 2-input AND circuit that receives the positive terminal of a certain flip-flop and the negative terminal of an adjacent flip-flop is connected. Further, the output of the 2-input AND circuit is input to the delay signal output determination group 3 as the select signal SL, and is NORed to be output as the mask output signal CO.

On the other hand, reference signal detection blocks 2B to 2D
The clock signal CLK is input to one end of a predetermined number of flip-flops, and the delay signal DL from the delay element group 1 is connected to each other end. Then, the positive terminal of a certain flip-flop, the negative terminal of an adjacent flip-flop, and a 3-input AND circuit that receives the mask signal CT are connected. Further, the output of the 3-input AND circuit is input to the output signal determination group 3 as the select signal SL, and is NORed to be output as the mask output signal CO.

As shown in FIG. 8, the reference signal detection block 2A to 2D having the above-mentioned configuration has the mask output signal CO of the reference signal detection block 2A and the mask signal CT of each of the reference signal detection blocks 2B to 2D. And the mask output signal CO are all mask signals C after the next stage.
It is connected to the input of T by taking the logical product.

With this configuration, the select signal becomes "H" only in the first phase-synchronized portion of each of the reference signal detection blocks 2A to 2D, and in the following blocks, the input of the mask signal CT is "L". ", The phase synchronization is not detected. Therefore, the delay element group 1
By increasing the number of stages and widening the detection range of the reference signal detecting means, it is possible to sufficiently cope with the environment in which the temperature and the power supply voltage greatly vary. Although FIG. 8 shows the case of a 4-stage block configuration,
Of course, it is not limited to this. Further, as a different mask processing method, a reference signal detection block 2A is used.
The AND circuit in the inside is used as the reference signal detection blocks 2B to 2B.
It is also possible to use a 3-input AND circuit as in the case of D and perform mask processing by a mask signal from an external CPU or the like as shown in FIG.

Normally, with the circuit configurations shown in FIGS. 7 to 9, it is possible to eliminate an abnormal state in which a plurality of detection results are obtained in the reference signal detection section 2. However, in the case where the circuit in the masking portion has a failure, the internal element such as the reference signal detection unit 2 is defective, or the operation guaranteed range is greatly exceeded, the malfunction shown in FIGS. Cannot be avoided. In such a case, the delay signal from the output signal determining unit 3a becomes inaccurate, or the delay signal does not appear, which is an abnormal state. In order to avoid such an abnormal state, it is effective to provide the correction means shown in FIG.

That is, in FIG. 10, the monitoring unit 4 including an external CPU or the like selects the select signal S from the reference signal detecting unit 2.
In addition to monitoring the state of L, the selector unit 5 selects a predetermined select signal, masks the select signal, or writes the selected signal based on the monitoring result of the monitoring unit 4, and then outputs the output signal determination group 3 The configuration to output to is shown.

The monitoring unit 4 can monitor the abnormal state of the select signal by, for example, preparing a plurality of tables in the look-up table format inside. Then, for each abnormal state, for example, the following control is performed.

In an abnormal state where a plurality of select signals are selected, the monitoring section 4 gives the selector section 5 an instruction to mask all but the first select signal. Further, in an abnormal state where the reference signal detection unit 2 does not output the select signal, the monitoring unit 4 issues an instruction signal for generating a predetermined select signal (for example, a select signal output from the final stage of the reference signal detection unit 2). Is output to the selector unit 5. It is also possible to completely ignore the reference signal detection unit 2 and write an arbitrary select signal from the monitoring unit 4 when the reference signal detection unit 2 fails.

Further, the provision of the monitoring unit 4 is effective not only for coping with an abnormal condition, but also for manually obtaining a delay signal. That is, when it is desired to obtain a desired delay time that is not assigned in the output signal determination group 3, for example, even if only 10 ns and 20 ns are assigned as the desired delay signal, the select signal input to the monitoring unit 4 is selected. Therefore, it is also possible to calculate and select the select signal that outputs the delay signal having the delay time of 15 ns based on the above-mentioned allocation formula (1).

FIG. 11 is a block diagram showing the configuration of another embodiment for monitoring the select signal. As shown in the figure, the external variable combination section 6 constituting the preliminary output signal determining means is provided in the reference signal detection section 2. On the other hand, it is provided in parallel with the output signal determination group 3. The external variable combination section 6 has a pattern in advance regarding the abnormality of the select signal, and determines the output of the delay signal to be output by a predetermined combination according to the abnormality pattern. That is, the external combination unit 6 rewrites the detection result of the reference signal detection unit 2 and determines the output of the delay signal, and the output signal determination group 3 and the monitoring unit 4 in FIG.
Play the role of. Therefore, when the select signal is in an abnormal state or when a delayed signal that has not been allocated is desired, it is possible to determine the output of the delayed signal in place of the output signal determination group 3.

Further, the output of at least one of the output signal determination group 3 and the external variable combination section 6 is taken out to the outside by the selector 8 whose selection state is controlled by the external control section 7. The operation of this selector 8 is as follows.
It is also possible to output any one of the signals, output a plurality of signals at the same time, or make them variable (programmable) according to an instruction from the external control unit 7.

Further, the signal delay device of the present invention may have a network configuration as shown in FIG. A in the figure
The delay lines 11 to D delay lines 14 are delay element groups 11a to 14 having the same configurations as the delay element group 1 and the output signal determination group 3 shown in FIGS. 2 and 6, respectively.
a, output signal determination groups 11b to 14b. Then, based on the clock signal input to the delay element group 11a, the reference signal detector 2'detects the phase synchronization. The detection results are output signal determination groups 11b to 1 respectively.
4b is input to each output signal determination group, and a delay signal having a desired delay time is output from the delay element group based on the detection result.

The above network configuration is effective when the duty of the input clock signal is broken. That is, the duty is 5
The clock signal with the purest waveform of 0% or the pure clock signal from the external oscillator is used as the clock signal CL.
By inputting it as K1 to the reference signal detection unit 2 ',
A clock signal (C that enters the other delay lines (B to D)
Even if the duty of LK2 to 4) is broken, an accurate detection result can be obtained in the reference signal detection unit 2 '. That is, since the network configuration is adopted, accurate reference signal detection can be performed if only the clock signal input to the reference signal detection unit 2 is made pure, so that accurate operation can be performed as a whole. Also, the clock signal C
Even if LK1 is a clock whose duty is not 50%, it can be used as an accurate clock signal by performing frequency division. Further, by sharing the reference signal detection unit 2, the number of gates can be significantly reduced, the circuit configuration can be simplified, and the reliability can be improved and the cost can be reduced.

FIG. 13 shows a further embodiment of the present invention. Since the signal delay device described above is configured by an integrated circuit such as a gate array and can perform all digital processing, it can be used in combination with a circuit having another function,
Programmable processing such as rewriting data by software from outside and changing operation is possible.
For example, examples of combinations with circuits having other functions are: signal delay device + PWM modulation circuit, signal delay device + synchronization circuit, etc. Connected to.

For example, consider a case where a PWM modulation circuit is used as the other function circuit 12. Conventionally, since a large number of delay signals required for generating a PWM signal are supplied from the outside, the generated noise affects the outside or PW.
There has been a problem that the time width of the M output signal is limited to the number of delay line taps. However,
As shown in FIG. 13, if it is configured with the signal delay device of the present embodiment, not only the advantage of space saving is obtained, but also the noise radiation is greatly improved. Moreover, by writing a control signal (select signal) from the external CPU, the delay amount between taps can be easily changed, and the time width of the PWM output signal can be finely adjusted. Furthermore, it is possible to change the operation by changing the data due to a process factor or by externally rewriting data by software.

Next, consider the case where the synchronizing circuit and the signal delay device are combined. Conventionally, it has been necessary to increase the number of delay line taps in order to improve the accuracy of the dot clock. However, since an expensive delay line is used, there is a problem in that the cost increases if the accuracy is increased.

However, in the signal delay device of this embodiment, the number of taps can be easily increased only by increasing the delay signal output determining section, so that the accuracy of the dot clock can be improved at low cost. Moreover, for example, it can be configured by combining it on a single chip with a synchronous circuit as described in Japanese Patent Application No. 2-150425 (see Japanese Patent Application Laid-Open No. 4-150425) filed prior to the present application. Therefore, noise radiation is improved. Furthermore, by using the external variable combination circuit 6 and the like described above, it is possible to externally rewrite data by software to change the operation.

As described above, the signal delay device according to the present embodiment can be configured on one integrated circuit together with the other function circuit 12, and synchronization of data transmission in an image forming apparatus such as a laser beam printer, a copying machine or a facsimile can be performed. Is available for. Further, in a DRAM, a RAS signal for determining a row address, a CAS signal for determining a column address, and switching of the RAS and CAS signals are used to make three timings of an R / C signal, and a CCD reset. It is also possible to adapt to the generation of pulses. In addition, it can be used in a multi-phase clock generation circuit to perform high-speed processing, in a clock phase synchronization circuit to match the phase of an external clock with an internal clock, and in a synchronization signal generation circuit to generate a clock synchronized with external data. It can be applied to the places where the delay lines that have been used conventionally are applied, such as when they are generated.

[0050]

As described above in detail, according to the present invention, the signal detecting means for detecting the reference signal from the plurality of delayed signals generated and output by the signal delay means including a plurality of circuit element units is used. , A delay signal that is in phase synchronization with the input signal is detected, and for the circuit element unit that generates this reference signal, the delay signal that is generated in advance for that circuit element unit becomes the reference signal. In this case, the desired delay signal is output from the output signal determining means that finds and associates the circuit element unit that is generating the delay signal of the desired delay time. Therefore, while using inexpensive circuit elements,
Even if the delay time greatly changes due to changes in temperature, humidity, and power supply voltage, a highly accurate delay signal can be output according to the change.

Therefore, it is possible to realize a signal delay device capable of accurately controlling the delay time with a simple structure. Then, at the timing 1 when the reference signal is detected
Since selection of the delay signal is performed after the clock, a delay signal having an accurate delay time can be obtained in real time even if the delay amount varies.

Further, since all the circuits can be constructed by digital circuits, the price of the conventional delay line is 1 /
Cost reduction of about 4 can be realized, and it is easy to expand.

In an integrated circuit such as a gate array, 1
By using a chip, the problematic interference does not occur in the external delay line, the problem of signal noise is solved, and the circuit can be combined with a circuit having other functions on one chip.

Furthermore, in the case where the output signal determining means can output a plurality of delay signals having different desired delay times,
It is possible to change the delay time of the delay signal that is output as needed, or to simultaneously output a plurality of delay signals having different delay times.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a configuration diagram showing components of one embodiment of the present invention.

FIG. 3 is a configuration diagram showing components of an embodiment of the present invention.

FIG. 4 is a time chart for explaining the operation of the embodiment of the present invention.

FIG. 5 is a time chart for explaining the operation of the embodiment of the present invention.

FIG. 6 is a configuration diagram showing components of an embodiment of the present invention.

FIG. 7 is a configuration diagram showing components of one embodiment of the present invention.

FIG. 8 is a configuration diagram showing components of an embodiment of the present invention.

FIG. 9 is a configuration diagram showing components of one embodiment of the present invention.

FIG. 10 is a configuration diagram showing a configuration of another embodiment of the present invention.

FIG. 11 is a configuration diagram showing a configuration of another embodiment of the present invention.

FIG. 12 is a configuration diagram showing a configuration of another embodiment of the present invention.

FIG. 13 is a configuration diagram showing a configuration of another embodiment of the present invention.

[Explanation of symbols]

1 Delay element group 2 Reference signal detector 3 Output signal decision group 3a to 3n output signal determination unit 4 Monitor 5 Selector section 6 External variable combination section 7 External control unit 8 selector 11 delay line 12 Other functional circuits

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Claims (4)

(57) [Claims] 1. A signal delay device for outputting a delay signal having a desired delay time from an input signal having one or more rectangular waves of a predetermined time length, wherein a plurality of circuit element units each consisting of a unit number are cascaded. A plurality of delay signals each including a connected circuit element group, the input signal being input to the circuit element group, and having different delay times with respect to the input signal according to the number of units passing through the circuit element unit. and signal delay means for generating a, from a plurality of delay signals generated by said signal delay means, and a signal detecting means for detecting a delayed signal in the phase synchronization relationship with said input signal as a reference signal, the signal
Mask processing for detecting means to perform single reference signal detection
Means and the signal detecting means detects the reference signal
Based on the delay time per circuit element unit
Then, there is provided output signal determining means configured to output the delay signal generated for each circuit element that generates the delay signal having the desired delay time, and the signal delay device. 2. The output signal determining means is composed of a plurality of output signal determining sections for outputting delay signals having different delay times, one of which is a first output for outputting a first desired delay time. A delay signal output from the first and second output signal determining units when the signal determining unit and the other one is a second output signal determining unit that outputs a delay signal having a second desired delay time. The signal delay device according to claim 1, further comprising a selection unit that selects a delay signal to be output to the outside from among the above. 3. The signal delay device according to claim 1, wherein the signal delay means, the signal detection means, and the output signal determination means are configured on one integrated circuit. 4. The signal delay device according to claim 3, wherein the signal delay device is configured on one integrated circuit together with a circuit having a function other than signal delay.