JP3447835B2 - RAM chip identification method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system in which, for example, an internal memory and an extension memory are constituted by a plurality of memory banks, each of which has a different type. The present invention relates to a suitable RAM chip identification method applied to a computer system capable of mounting the RAM chip of the present invention, and in particular, by determining whether or not a RAM chip is mounted in each memory bank and the type of the mounted RAM chip at system startup, The present invention relates to a RAM chip identification method for automatically recognizing a memory configuration of an internal memory and an additional memory. 2. Description of the Related Art In recent years, various types of personal computers, such as a notebook type and a laptop type, which are easily portable and can be operated by a battery, have been developed. And
A plurality of RAM chips are used as a main memory of these personal computers. The main memory comprises an internal memory which is mounted on a system board as standard, and an additional memory which is mounted as needed by a user. The internal memory and the additional memory are usually constituted by a plurality of memory banks. ing. Also, the RAM mounted on these memory banks
A plurality of types of chips having different specifications including a configuration, a capacity, and the like exist. That is, in each of these memory banks,
Depending on which type of RAM chip is installed,
The memory configurations of the internal memory and the additional memory can be easily set, and more configuration patterns can be supported. [0005] However, conventionally,
In the case where the capacity of the main memory is set to a desired size, it is often necessary to attach a RAM chip having a predetermined capacity and configuration to a predetermined memory bank. This is because some mounting patterns are stored in the system in advance, and the type of the RAM chip mounted on the memory bank is specified in accordance with the patterns. That is, despite the existence of a plurality of types of RAM chips having different specifications including the configuration, capacity, etc., the system dynamically identifies the type of RAM chip mounted on each memory bank. Since there is no memory, the memory can be configured only within the range of the mounting pattern possessed by the system, and there is a problem that the configuration pattern of the memory that the computer system can support is limited. [0007] The present invention has been made in view of the above circumstances, and the RA of each memory bank at the time of system startup.
A RAM chip that automatically recognizes the memory configuration of the internal memory and the additional memory by determining whether or not the M chip is mounted and the type of the mounted RAM chip, so that the computer system can support more configuration patterns. The purpose is to provide an identification scheme. SUMMARY OF THE INVENTION The present invention is a computer system in which an internal memory and an additional memory are constituted by a plurality of memory banks, and different types of RAM chips can be mounted in these memory banks. Determining means for determining whether or not a RAM chip is mounted in each of the memory banks and the type of the mounted RAM chip, and the internal memory and the additional memory based on the determination result of the determining means. Means for recognizing the memory configuration of any one of the row address sizes,
RAM chip with column address size
For the first writable address, the first data
Write, and after this writing is completed,
With the above row address size or column address size
Write only the RAM chip to be written
Has a row address size or column address size
For RAM chips that do not have
A second address such that the first address is specified.
Write the second data to the
After the writing of the first and second data is completed, the first address
Reads the data held in the
Based on the contents of the data
Address size and column address of the RAM chip
And a means for detecting at least one of the dress sizes . According to the structure of the present invention, when the computer system starts up, R is set for each of the plurality of memory banks constituting the internal memory and the additional memory.
The presence or absence of the AM chip and the type of the mounted RAM chip are determined, and the memory configuration of the system memory is recognized based on the determination. That is, for example, when there is a possibility that a RAM chip having a different row address size may be mounted on a memory bank, first, a writable first address is applied to a RAM chip having any row address size. First data is written. Next, for a RAM chip having a row address size equal to or larger than a predetermined size, writing is possible, and for a RAM chip not having the row address size of the predetermined size, writing was performed earlier due to a lack of an upper address. The second data is written to a second address at which the first address is specified. That is, in this case, the second data is written assuming a RAM chip having a predetermined row address size. Here, when the data held at the first address is read and its contents are examined, RA
When the M chip is not mounted, a predetermined value (for example, high value) is confirmed. When a RAM chip having a row address size equal to or larger than a predetermined size is mounted, the first data written first is confirmed. On the other hand, if a RAM chip having no predetermined row address size is mounted, the second
Since this data is further written, this second data is confirmed. Also, when there is a possibility that a RAM chip having a different column address size may be mounted on a memory bank, it can be identified by the same procedure as in the case of the row address described above. That is, the type of each RAM chip having at least one of a row address size and a column address size can be determined, whereby the memory configuration of the system memory can be recognized. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a system configuration of a personal computer according to an embodiment of the present invention. This personal computer is a laptop or notebook type system, and includes a CPU local bus (processor bus) 10A, an ISA system bus 10B, a CPU 11, a level shift gate array 12, a system memory 13, Display controller 1
4, a video memory (VRAM) 15 and a flat panel display 16 such as an LCD. The CPU 11 controls the entire system, and executes a program to be processed stored in the system memory 13. As the CPU 11,
3.3 V / 5 V operable, such as microprocessor SL E manufactured and sold by Intel Corporation
An enhanced intelligent 486 or the like is used, and a power supply voltage of 3.3 V is supplied to the CPU 11 by a power supply controller 23 described later. This CP
The local bus 10A of U11 defines a 32-bit data bus, a 32-bit address bus, various status signal lines, and the like. The system memory 13 stores an operating system, an application program to be processed, user data created by the application program, and the like. This system memory 13
It comprises an internal memory and an additional memory composed of a plurality of memory banks, and any type of RAM chip is selectively mounted on these memory banks. The identification of the memory configuration of the system memory 13 is a feature of the present invention, and will be described in detail with reference to FIG. The level shift gate array 12 has a CP
It is connected between a 32-bit data bus defined in the U local bus 10A and the system memory 13, and converts the voltage level of a data signal transferred between the buses from 3.3V to 5V or from 5V to 3.3V. I do. The voltage level conversion of the data signal is performed by the level shift gate array 12.
This is performed by the buffer circuit inside. Further, in order to enable asynchronous execution of the CPU bus cycle and the read access cycle of the system memory 13, the buffer circuit is provided with a data latch function of latching read data from the system memory 13. The display controller 14 is for controlling the display of a flat panel display 16 composed of an STN monochrome, STN color or TFT color LCD panel and the like.
The display data is received from the CPU 11 via A and written into the video memory (VRAM) 15. The system bus 10B has a BIOS RO
M17, a system controller 18, and an I / O controller 19 are connected. BIOS ROM17
Is for storing a system BIOS (Basic I / O System), and is constituted by a flash memory so that a program can be rewritten. The system BIOS includes an IRT routine executed when the power is turned on, a device driver for controlling various I / O devices, a system management program, a setup program, and the like. The system controller 18 includes a bridge device for connecting the CPU local bus 10A and the system bus 10B, a memory control logic for controlling various memories in the system, and the like. The I / O controller 19 controls I / O devices and the like connected to the serial port 20, controls a printer / external FDD connected to the parallel port (printer port) 21, and 3.5 inches. Built-in FD
D22 is controlled. The I / O controller 19 has two DMA controllers for direct memory access control, and an interrupt controller (PIC; Pro).
2 grammable interrupters (controllers) and a system timer (PIT; Programmable Interrupter Timer)
), One serial I / O controller (SIO; S
Two serial input / output controllers and one floppy disk controller (FDC) are included. Further, the I / O controller 19 includes an I / O register group used for communication between the power supply controller (PSC) 23 and the CPU 11, and an I / O register for setting the environment of the parallel port 21. Groups are also provided. The system bus 10B further includes a built-in H
A DD 24, a real-time clock (RTC) 25, a keyboard controller (KBC) 26, a PCMCIA controller 27, a CD-ROM 34, and a sound card 35 are connected. The real-time clock (RTC) 25 is
The timepiece module has its own operation battery, and has a CMOS static RAM (referred to as CMOS memory) to which power is constantly supplied from the battery. This CMOS memory is used for storing environment setting information indicating the system operating environment. Keyboard controller (KBC) 26
Is for controlling the built-in keyboard 29 built in the computer main body.
9 is scanned to receive a signal corresponding to a pressed key and convert it into a predetermined key code (scan code). The keyboard controller 26 has a function of controlling an optional external keyboard 30 and a dedicated processor (IPS controller) 28.
Has a function of controlling the pointing stick 31 and the mouse 32 by using the mouse. The pointing stick 31 is provided integrally with the keyboard unit of the built-in keyboard 29. The PCMCIA controller 27 controls access to a PC card 33 of JEIDA / PCMCIA specifications which is installed as an option. The sound card 25 includes a PCM sound source, a digital signal processing circuit for audio signals, and the like. The sound card 25 includes a line input terminal 36, a line output terminal 37, and a headphone terminal 3.
8, microphone terminal 39 and joystick terminal 40
Is connected. Now, as shown in FIG. 2, it is assumed that the system memory 13 of the personal computer according to the present embodiment has ten memory types c to Ed, and each memory bank (FIG. 2 shows a row address strobe signal). Line (R
Assume that the type of the RAM chip to be mounted on the AS (shown by AS0 to RAS5) is one of the three types (1) to (3) shown in FIG. That is, the RAM chips (1) to (3)
This means that at least one of the row address size and the column address size is different. Here, FIG.
The operation procedure and operation principle of the embodiment will be described with reference to FIG. This RAM chip identification processing is performed at the time of starting up the system or the like. First, the memory bank (RASn) to be inspected is enabled to make it accessible (step S1 in FIG. 4). . Next, "5A5A5A5A" is added to the address "00000000H".
H "(step S2 in FIG. 4), and then" A5A5A5A5H "is written into the address" 00000400H "(step S3 in FIG. 4.) Note that these writes assume a RAM chip having a column address size of 9. Since the computer system of this embodiment assumes double word access, the arrangement of the row address and column address for each of the RAM chip types (1) to (3) is shown in FIG. Therefore, when writing to the address “00000400H”, the first bit is lost in the type (3) RAM chip, resulting in writing to the address “00000000H”. At this time, the data held at the address "00000000H" is read out (step S4 in FIG. 4), and its contents are checked (step S4 in FIG. 4). 5). If this memory bank in the RAM chip is not mounted, "FFFFF
FFFH "is confirmed, and as a result, it is found that no RAM chip of any type is mounted on this memory bank (step S6 in FIG. 4)." A5A5A5A5H " If confirmed, this indicates that the first bit was lost when writing to the address "00000400H". As a result, a RAM chip of type (3) was mounted in this memory bank. (Step S7 in FIG. 4) On the other hand, if "5A5A5A5AH" is confirmed, it indicates that the leading one bit was not lost when writing to the address "00000400H". As a result, either type (1) or type (2) RAM
The chip is found to be mounted, and the inspection is continued. That is, this time, the address “00000000H” is set to “5A5
"A5A5AH" is written (step S8 in FIG. 4), and subsequently "A5A5A5A5H" is written into the address "00400000H" (step S9 in FIG. 4) In these writes, the column address is 10 and the row address size is Is 1
This is performed on the assumption that the RAM chip is 1. Similar to FIG. 5, the layout of the row address and column address of each of the RAM chip types (1) to (3) is as shown in FIG. 6, and therefore, when writing to the address "00400000H", RA of type (1)
In the M chip, the first bit is lost, and as a result, data is written to the address “00000000H”. Here, the data held at the address "00000000H" is read out (step S10 in FIG. 4), and its contents are inspected (step S11 in FIG. 4). At this time, if "A5A5A5A5H" is confirmed, the address "004
00000H "indicates that the first bit has been lost. As a result, it is determined that a RAM chip of type (1) is mounted in this memory bank (step S12 in FIG. 4). On the other hand, if "5A5A5A5AH" is confirmed, it indicates that the leading one bit has not been lost when writing to the address "00400000H", and as a result, the type (2 (Step S13 in FIG. 4) It is found out that the RAM chip of the memory bank to be inspected is mounted.
Whether the AM chip is mounted and the type of the mounted RAM chip are identified. The RAM chip identification process is performed for all the memory banks (step S14 in FIG. 4). As a result, the memory configuration of the system memory 13 of the computer system is changed to the configuration shown in FIG.
It can be determined which of the configurations shown in FIG. As described above, in the system according to this embodiment, the memory configuration of the system memory 13 can be dynamically determined without having to specify the memory configuration, and a larger number of configuration patterns can be supported. . As described above in detail, according to the present invention, the presence / absence of the mounting of the RAM chip in each of the plurality of memory banks constituting the internal memory and the additional memory, and the mounted RA
The type of the M chip can be determined, and the memory configuration of the internal memory and the additional memory can be automatically recognized. Therefore, the computer system can support more system memory configuration patterns.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a system configuration of a personal computer according to an embodiment of the present invention. FIG. 2 is an exemplary view showing a configuration pattern of a system memory assumed in the personal computer according to the embodiment; FIG. 3 is an exemplary view showing a configuration pattern of a RAM chip mounted on each memory bank of the personal computer according to the embodiment. FIG. 4 is an exemplary flowchart for explaining the operation procedure of the personal computer according to the embodiment. FIG. 5 is an exemplary conceptual diagram for explaining the operation principle of the personal computer according to the embodiment. FIG. 6 is an exemplary conceptual view for explaining the operation principle of the personal computer according to the embodiment. [Description of Signs] 11 CPU, 13 system memory, 25 RTC.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/06

Claims (1)

(57) [Claim 1] A computer system in which an internal memory and an additional memory are constituted by a plurality of memory banks, each of which has a different type of R
RAM of computer system to which AM chip can be mounted
In the chip identification method, determining means for determining whether or not a RAM chip is mounted in each of the memory banks and the type of the mounted RAM chip, and recognizing a memory configuration of the internal memory and the additional memory based on a determination result of the determining means Means for determining which row address size or color
Write on a RAM chip with
Write first data to a writeable first address
After the end of this writing,
Has row address size or column address size
Only a RAM chip can be written and
-Does not have address size or column address size
For RAM chips, due to lack of upper address
A second address such that the first address is specified
The second data is written to the
After the writing of the second data, the first address
Read the data held in the
From the contents of the data, whether or not the RAM chip is
Row address size and column address of RAM chip
A means for detecting at least one of the size of the RAM chip.